ADC121S101 Single Channel, 0.5 to 1 Msps, 12-Bit A/D Converter General Description Features The ADC121S101 is a low-power, single channel CMOS 12-bit analog-to-digital converter with a high-speed serial interface. Unlike the conventional practice of specifying performance at a single sample rate only, the ADC121S101 is fully specified over a sample rate range of 500 ksps to 1 Msps. The converter is based upon a successiveapproximation register architecture with an internal trackand-hold circuit. The output serial data is straight binary, and is compatible with several standards, such as SPI™, QSPI™, MICROWIRE, and many common DSP serial interfaces. n n n n n The ADC121S101 operates with a single supply that can range from +2.7V to +5.25V. Normal power consumption using a +3V or +5V supply is 2.0 mW and 10 mW, respectively. The power-down feature reduces the power consumption to as low as 2.6 µW using a +5V supply. The ADC121S101 is packaged in 6-lead LLP and SOT-23 packages. Operation over the industrial temperature range of −40˚C to +125 ˚C is guaranteed. Specified over a range of sample rates. 6-lead LLP and SOT-23 packages Variable power management Single power supply with 2.7V - 5.25V range SPI™/QSPI™/MICROWIRE/DSP compatible Key Specifications n n n n DNL INL SNR Power Consumption — 3V Supply — 5V Supply +0.5 / −0.3 LSB (typ) ± 0.40 LSB (typ) 72.5 dB (typ) 2.0 mW (typ) 10 mW (typ) Applications n Portable Systems n Remote Data Acquisition n Instrumentation and Control Systems Pin-Compatible Alternatives by Resolution and Speed All devices are fully pin and function compatible. Resolution Specified for Sample Rate Range of: 50 to 200 ksps 200 to 500 ksps 500 ksps to 1 Msps 12-bit ADC121S021 ADC121S051 ADC121S101 10-bit ADC101S021 ADC101S051 ADC101S101 8-bit ADC081S021 ADC081S051 ADC081S101 Connection Diagram 20145005 Ordering Information Temperature Range Description ADC121S101CISD Order Code −40˚C to +125 ˚C 6-Lead LLP Package X1C ADC121S101CISDX −40˚C to +125 ˚C 6-Lead LLP Package, Tape & Reel X1C ADC121S101CIMF −40˚C to +125 ˚C 6-Lead SOT-23 Package X01C ADC121S101CIMF −40˚C to +125 ˚C 6-Lead SOT-23 Package, Tape & Reel X01C ADC121S101EVAL Top Mark Evaluation Board TRI-STATE ® is a trademark of National Semiconductor Corporation QSPI™ and SPI™ are trademarks of Motorola, Inc. © 2006 National Semiconductor Corporation DS201450 www.national.com ADC121S101 Single Channel, 0.5 to 1 Msps, 12-Bit A/D Converter April 2006 ADC121S101 Block Diagram 20145007 Pin Descriptions and Equivalent Circuits Pin No. Symbol Description ANALOG I/O 3 VIN Analog input. This signal can range from 0V to VA. DIGITAL I/O 4 SCLK Digital clock input. This clock directly controls the conversion and readout processes. 5 SDATA Digital data output. The output samples are clocked out of this pin on falling edges of the SCLK pin. 6 CS Chip select. On the falling edge of CS, a conversion process begins. 1 VA Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and bypassed to GND with a 1 µF capacitor and a 0.1 µF monolithic capacitor located within 1 cm of the power pin. 2 GND The ground return for the supply and signals. PAD GND For package suffix CISD(X) only, it is recommended that the center pad should be connected to ground. POWER SUPPLY www.national.com 2 Operating Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Operating Temperature Range VA Supply Voltage Voltage on Any Digital Pin to GND −0.3V to 6.5V Voltage on Any Analog Pin to GND −0.3V to (VA +0.3V) Package Input Current (Note 3) Power Consumption at TA = 25˚C 0V to VA Clock Frequency 1 MHz to 20 MHz Sample Rate See (Note 4) ESD Susceptibility (Note 5) Human Body Model Machine Model −0.3V to 5.25V Analog Input Pins Voltage Range ± 10 mA ± 20 mA Input Current at Any Pin (Note 3) +2.7V to +5.25V Digital Input Pins Voltage Range (regardless of supply voltage) −0.3V to 6.5V Analog Supply Voltage VA −40˚C ≤ TA ≤ +125˚C up to 1 Msps Package Thermal Resistance θJA Package 3500V 300V 6-lead LLP 94˚C / W Junction Temperature +150˚C 6-lead SOT-23 265˚C / W Storage Temperature −65˚C to +150˚C Soldering process must comply with National Semiconductor’s Reflow Temperature Profile specifications. Refer to www.national.com/packaging. (Note 6) ADC121S101 Converter Electrical Characteristics (Notes 7, 9) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 10 MHz to 20 MHz, CL = 15 pF, fSAMPLE = 500 ksps to 1 Msps, unless otherwise noted. Boldface limits apply for TA = -40˚C to +85˚C: all other limits TA = 25˚C unless otherwise noted. Symbol Parameter Conditions Typical Limits (Note 9) Units 12 Bits STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes VA = +2.7v to +3.6V −40˚C ≤ TA ≤ 125˚C −40˚C ≤ TA ≤ +85˚C VA = +2.7V to +3.6V INL VOFF GE LLP Integral Non-Linearity TA = 125˚C VA = +2.7v to +3.6V DNL SOT-23 Differential Non-Linearity +0.4 -0.4 −40˚C ≤ TA ≤ 125˚C VA = +2.7v to +3.6V Gain Error −40˚C ≤ TA ≤ 125˚C VA = +2.7 to +3.6V +1.0 -1.2 LSB (min) +1.0 LSB (max) -1.1 LSB (min) +1.0 LSB (max) LLP SOT-23 LLP LSB (min) -0.4 LSB (max) -1.3 LSB (min) +0.5 +1.0 LSB (max) −0.3 -0.9 LSB (min) ± 1.0 LSB (max) TA = 125˚C VA = +2.7v to +3.6V Offset Error LSB (max) +0.4 SOT-23 −40˚C ≤ TA ≤ +85˚C VA = +2.7V to +3.6V ± 1.0 LSB (max) ± 0.1 ± 1.2 ± 0.20 ± 0.20 ± 1.2 ± 1.5 LSB (max) 72 70 dB (min) 72.5 70.8 LSB (min) LSB (max) DYNAMIC CONVERTER CHARACTERISTICS SINAD SNR VA = +2.7 to 5.25V Signal-to-Noise Plus Distortion Ratio −40˚C ≤ TA ≤ 125˚C fIN = 100 kHz, −0.02 dBFS Signal-to-Noise Ratio VA = +2.7 to 5.25V −40˚C ≤ TA ≤ +85˚C fIN = 100 kHz, −0.02 dBFS VA = +2.7 to 5.25V TA = +125˚C fIN = 100 kHz, −0.02 dBFS 3 dB (min) 70.6 www.national.com ADC121S101 Absolute Maximum Ratings (Notes 1, 2) ADC121S101 ADC121S101 Converter Electrical Characteristics (Notes 7, 9) (Continued) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 10 MHz to 20 MHz, CL = 15 pF, fSAMPLE = 500 ksps to 1 Msps, unless otherwise noted. Boldface limits apply for TA = -40˚C to +85˚C: all other limits TA = 25˚C unless otherwise noted. Symbol Parameter Conditions Typical Limits (Note 9) Units DYNAMIC CONVERTER CHARACTERISTICS THD Total Harmonic Distortion VA = +2.7 to 5.25V fIN = 100 kHz, −0.02 dBFS −80 dB (max) SFDR Spurious-Free Dynamic Range VA = +2.7 to 5.25V fIN = 100 kHz, −0.02 dBFS 82 dB (min) ENOB Effective Number of Bits VA = +2.7 to 5.25V fIN = 100 kHz, −0.02 dBFS 11.6 Intermodulation Distortion, Second Order Terms VA = +5.25V fa = 103.5 kHz, fb = 113.5 kHz −78 dB Intermodulation Distortion, Third Order Terms VA = +5.25V fa = 103.5 kHz, fb = 113.5 kHz −78 dB VA = +5V 11 MHz VA = +3V 8 MHz IMD FPBW -3 dB Full Power Bandwidth 11.3 Bits (min) ANALOG INPUT CHARACTERISTICS VIN Input Range IDCL DC Leakage Current CINA Input Capacitance 0 to VA V ±1 µA (max) Track Mode 30 pF Hold Mode 4 pF DIGITAL INPUT CHARACTERISTICS VIH Input High Voltage VIL Input Low Voltage IIN Input Current CIND Digital Input Capacitance VA = +5.25V 2.4 V (min) VA = +3.6V 2.1 V (min) VA = +5V 0.8 V (max) VA = +3V 0.4 V (max) ± 0.1 ±1 µA (max) 2 4 pF (max) ISOURCE = 200 µA VA − 0.07 VA − 0.2 V (min) ISOURCE = 1 mA VA − 0.1 VIN = 0V or VA DIGITAL OUTPUT CHARACTERISTICS VOH Output High Voltage VOL Output Low Voltage IOZH, IOZL TRI-STATE ® Leakage Current COUT TRI-STATE ® Output Capacitance ISINK = 200 µA 0.03 ISINK = 1 mA 0.1 V 0.4 V (max) V ± 0.1 ± 10 µA (max) 2 4 pF (max) Output Coding Straight (Natural) Binary POWER SUPPLY CHARACTERISTICS VA Supply Voltage Supply Current, Normal Mode (Operational, CS low) IA Supply Current, Shutdown (CS high) www.national.com 2.7 V (min) 5.25 V (max) VA = +5.25V, fSAMPLE = 1 Msps 2.0 3.2 mA (max) VA = +3.6V, fSAMPLE = 1 Msps 0.6 1.5 mA (max) fSCLK = 0 MHz, VA = +5V, fSAMPLE = 0 ksps 500 nA fSCLK = 20 MHz, VA = +5V, fSAMPLE = 0 ksps 60 µA 4 (Continued) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 10 MHz to 20 MHz, CL = 15 pF, fSAMPLE = 500 ksps to 1 Msps, unless otherwise noted. Boldface limits apply for TA = -40˚C to +85˚C: all other limits TA = 25˚C unless otherwise noted. Symbol Typical Limits (Note 9) Units VA = +5V 10 16 mW (max) VA = +3V 2.0 4.5 mW (max) fSCLK = 0 MHz, VA = +5V fSAMPLE = 0 ksps 2.5 µW fSCLK = 20 MHz, VA = +5V, fSAMPLE = 0 ksps 300 µW Parameter Conditions POWER SUPPLY CHARACTERISTICS Power Consumption, Normal Mode (Operational, CS low) PD Power Consumption, Shutdown (CS high) AC ELECTRICAL CHARACTERISTICS fSCLK Clock Frequency (Note 8) fS Sample Rate (Note 8) tCONV Conversion Time DC SCLK Duty Cycle tACQ fSCLK = 20 MHz 50 Track/Hold Acquisition Time Throughput Time Acquisition Time + Conversion Time 10 MHz (min) 20 MHz (max) 500 ksps (min) 1 Msps (max) 16 SCLK cycles 40 % (min) 60 % (max) 400 ns (max) 20 SCLK cycles 50 ns (min) tQUIET (Note 10) tAD Aperture Delay 3 ns tAJ Aperture Jitter 30 ps ADC121S101 Timing Specifications The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 10.0 MHz to 20.0 MHz, CL = 25 pF, fSAMPLE = 500 ksps to 1 Msps, Boldface limits apply for TA = -40˚C to +85˚C; all other limits TA = 25˚C. Symbol Limits Units tCS Minimum CS Pulse Width Parameter Conditions Typical 10 ns (min) tSU CS to SCLK Setup Time 10 ns (min) tEN Delay from CS Until SDATA TRI-STATE ® Disabled (Note 11) 20 ns (max) tACC Data Access Time after SCLK Falling Edge (Note 12) VA = +2.7 to +3.6 40 ns (max) VA = +4.75 to +5.25 20 ns (max) ns (min) tCL SCLK Low Pulse Width 0.4 x tSCLK tCH SCLK High Pulse Width 0.4 x tSCLK ns (min) tH SCLK to Data Valid Hold Time VA = +2.7V to +3.6V 7 ns (min) VA = +4.75V to +5.25V 5 ns (min) 25 ns (max) tDIS tPOWER-UP SCLK Falling Edge to SDATA High Impedance (Note 13) VA = +2.7V to +3.6V VA = +4.75V to +5.25V Power-Up Time from Full Power-Down 1 6 ns (min) 25 ns (max) 5 ns (min) µs Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified. 5 www.national.com ADC121S101 ADC121S101 Converter Electrical Characteristics (Notes 7, 9) ADC121S101 ADC121S101 Timing Specifications (Continued) Note 3: When the input voltage at any pin exceeds the power supply (that is, VIN < GND or VIN > VA), the current at that pin should be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. The Absolute Maximum Rating specification does not apply to the VA pin. The current into the VA pin is limited by the Analog Supply Voltage specification. Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDmax = (TJmax − TA) / θJA. The values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through zero ohms. Note 6: Reflow temperature profiles are different for lead-free and non-lead-free packages. Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 8: This is the frequency range over which the electrical performance is guaranteed. The device is functional over a wider range which is specified under Operating Ratings. Note 9: Data sheet min/max specification limits are guaranteed by design, test, or statistical analysis. Note 10: Minimum Quiet Time required by bus relinquish and the start of the next conversion. Note 11: Measured with the timing test circuit shown in Figure 1 and defined as the time taken by the output signal to cross 1.0V. Note 12: Measured with the timing test circuit shown in Figure 1 and defined as the time taken by the output signal to cross 1.0V or 2.0V. Note 13: tDIS is derived from the time taken by the outputs to change by 0.5V with the timing test circuit shown in Figure 1. The measured number is then adjusted to remove the effects of charging or discharging the output capacitance. This means that tDIS is the true bus relinquish time, independent of the bus loading. www.national.com 6 ADC121S101 Timing Diagrams 20145008 FIGURE 1. Timing Test Circuit 20145006 FIGURE 2. ADC121S101 Serial Timing Diagram 7 www.national.com ADC121S101 order intermodulation products to the sum of the power in both of the original frequencies. IMD is usually expressed in dB. Specification Definitions ACQUISITION TIME is the time required to acquire the input voltage. That is, it is time required for the hold capacitor to charge up to the input voltage. MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC121S101 is guaranteed not to have any missing codes. APERTURE DELAY is the time between the fourth falling SCLK edge of a conversion and the time when the input signal is acquired or held for conversion. OFFSET ERROR is the deviation of the first code transition (000...000) to (000...001) from the ideal (i.e. GND + 0.5 LSB). SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or d.c. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. Aperture jitter manifests itself as noise in the output. CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input voltage to a digital word. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding d.c. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The specification here refers to the SCLK. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal amplitude to the amplitude of the peak spurious spectral component, where a spurious spectral component is any signal present in the output spectrum that is not present at the input and may or may not be a harmonic. TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB or dBc, of the rms total of the first five harmonic components at the output to the rms level of the input signal frequency as seen at the output. THD is calculated as FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. GAIN ERROR is the deviation of the last code transition (111...110) to (111...111) from the ideal (VREF − 1.5 LSB), after adjusting for offset error. INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from negative full scale (1⁄2 LSB below the first code transition) through positive full scale (1⁄2 LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in the second and third www.national.com where Af1 is the RMS power of the input frequency at the output and Af2 through Af6 are the RMS power in the first 5 harmonic frequencies. THROUGHPUT TIME is the minimum time required between the start of two successive conversion. It is the acquisition time plus the conversion time. 8 ADC121S101 Typical Performance Characteristics TA = +25˚C, fSAMPLE = 500 ksps to 1 Msps, fSCLK = 10 MHz to 20 MHz, fIN = 100 kHz unless otherwise stated. INL fSCLK = 10 MHz DNL fSCLK = 10 MHz 20145020 20145021 INL fSCLK = 20 MHz DNL fSCLK = 20 MHz 20145060 20145061 DNL vs. Clock Frequency INL vs. Clock Frequency 20145065 20145066 9 www.national.com ADC121S101 Typical Performance Characteristics TA = +25˚C, fSAMPLE = 500 ksps to 1 Msps, fSCLK = 10 MHz to 20 MHz, fIN = 100 kHz unless otherwise stated. (Continued) SNR vs. Clock Frequency SINAD vs. Clock Frequency 20145063 20145064 SFDR vs. Clock Frequency THD vs. Clock Frequency 20145067 20145068 Spectral Response, VA = 5.25V fSCLK = 20 MHz Spectral Response, VA = 5.25V fSCLK = 10 MHz 20145069 www.national.com 20145070 10 ADC121S101 Typical Performance Characteristics TA = +25˚C, fSAMPLE = 500 ksps to 1 Msps, fSCLK = 10 MHz to 20 MHz, fIN = 100 kHz unless otherwise stated. (Continued) Power Consumption vs. Throughput, fSCLK = 20 MHz 20145055 11 www.national.com ADC121S101 Figure 4 shows the device in hold mode: switch SW1 connects the sampling capacitor to ground, maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs the charge-redistribution DAC to add or subtract fixed amounts of charge from the sampling capacitor until the comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of the analog input voltage. The device moves from hold mode to track mode on the 13th rising edge of SCLK. Applications Information 1.0 ADC121S101 OPERATION The ADC121S101 is a successive-approximation analog-todigital converter designed around a charge-redistribution digital-to-analog converter core. Simplified schematics of the ADC121S101 in both track and hold modes are shown in Figure 3 and Figure 4, respectively. In Figure 3, the device is in track mode: switch SW1 connects the sampling capacitor to the input, and SW2 balances the comparator inputs. The device is in this state until CS is brought low, at which point the device moves to hold mode. 20145009 FIGURE 3. ADC121S101 in Track Mode 20145010 FIGURE 4. ADC121S101 in Hold Mode edge of CS. The converter moves from hold mode to track mode on the 13th rising edge of SCLK (see Figure 2). The SDATA pin will be placed back into TRI-STATE after the 16th falling edge of SCLK, or at the rising edge of CS, whichever occurs first. After a conversion is completed, the quiet time tQUIET must be satisfied before bringing CS low again to begin another conversion. Sixteen SCLK cycles are required to read a complete sample from the ADC121S101. The sample bits (including leading zeroes) are clocked out on falling edges of SCLK, and are intended to be clocked in by a receiver on subsequent falling edges of SCLK. The ADC121S101 will produce three leading zero bits on SDATA, followed by twelve data bits, most significant first. If CS goes low before the rising edge of SCLK, an additional (fourth) zero bit may be captured by the next falling edge of SCLK. 2.0 USING THE ADC121S101 The serial interface timing diagram for the ADC121S101 is shown in Figure 2. CS is chip select, which initiates conversions on the ADC121S101 and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of serial data. SDATA is the serial data out pin, where a conversion result is found as a serial data stream. Basic operation of the ADC121S101 begins with CS going low, which initiates a conversion process and data transfer. Subsequent rising and falling edges of SCLK will be labelled with reference to the falling edge of CS; for example, "the third falling edge of SCLK" shall refer to the third falling edge of SCLK after CS goes low. At the fall of CS, the SDATA pin comes out of TRI-STATE, and the converter moves from track mode to hold mode. The input signal is sampled and held for conversion on the falling www.national.com 12 5.0 ANALOG INPUTS (Continued) An equivalent circuit for the ADC121S101’s input is shown in Figure 7. Diodes D1 and D2 provide ESD protection for the analog inputs. At no time should the analog input go beyond (VA + 300 mV) or (GND − 300 mV), as these ESD diodes will begin conducting, which could result in erratic operation. 3.0 ADC121S101 TRANSFER FUNCTION The output format of the ADC121S101 is straight binary. Code transitions occur midway between successive integer LSB values. The LSB width for the ADC121S101 is VA/4096. The ideal transfer characteristic is shown in Figure 5. The transition from an output code of 0000 0000 0000 to a code of 0000 0000 0001 is at 1/2 LSB, or a voltage of VA/8192. Other code transitions occur at steps of one LSB. The capacitor C1 in Figure 7 has a typical value of 4 pF, and is mainly the package pin capacitance. Resistor R1 is the on resistance of the track / hold switch, and is typically 500 ohms. Capacitor C2 is the ADC121S101 sampling capacitor and is typically 26 pF. The ADC121S101 will deliver best performance when driven by a low-impedance source to eliminate distortion caused by the charging of the sampling capacitance. This is especially important when using the ADC121S101 to sample AC signals. Also important when sampling dynamic signals is an anti-aliasing filter. 20145014 20145011 FIGURE 7. Equivalent Input Circuit FIGURE 5. Ideal Transfer Characteristic 6.0 DIGITAL INPUTS AND OUTPUTS 4.0 TYPICAL APPLICATION CIRCUIT A typical application of the ADC121S101 is shown in Figure 6. Power is provided in this example by the National Semiconductor LP2950 low-dropout voltage regulator, available in a variety of fixed and adjustable output voltages. The power supply pin is bypassed with a capacitor network located close to the ADC121S101. Because the reference for the ADC121S101 is the supply voltage, any noise on the supply will degrade device noise performance. To keep noise off the supply, use a dedicated linear regulator for this device, or provide sufficient decoupling from other circuitry to keep noise off the ADC121S101 supply pin. Because of the ADC121S101’s low power requirements, it is also possible to use a precision reference as a power supply to maximize performance. The three-wire interface is shown connected to a microprocessor or DSP. The ADC121S101 digital inputs (SCLK and CS) are not limited by the same maximum ratings as the analog inputs. The digital input pins are instead limited to +5.25V with respect to GND, regardless of VA, the supply voltage. This allows the ADC121S101 to be interfaced with a wide range of logic levels, independent of the supply voltage. 7.0 MODES OF OPERATION The ADC121S101 has two possible modes of operation: normal mode, and shutdown mode. The ADC121S101 enters normal mode (and a conversion process is begun) when CS is pulled low. The device will enter shutdown mode if CS is pulled high before the tenth falling edge of SCLK after CS is pulled low, or will stay in normal mode if CS remains low. Once in shutdown mode, the device will stay there until CS is brought low again. By varying the ratio of time spent in the normal and shutdown modes, a system may trade-off throughput for power consumption, with a sample rate as low as zero. 7.1 Normal Mode The fastest possible throughput is obtained by leaving the ADC121S101 in normal mode at all times, so there are no power-up delays. To keep the device in normal mode continuously, CS must be kept low until after the 10th falling edge of SCLK after the start of a conversion (remember that a conversion is initiated by bringing CS low). If CS is brought high after the 10th falling edge, but before the 16th falling edge, the device will remain in normal mode, but the current conversion will be aborted, and SDATA will return to TRI-STATE (truncating the output word). Sixteen SCLK cycles are required to read all of a conversion word from the device. After sixteen SCLK cycles have 20145013 FIGURE 6. Typical Application Circuit 13 www.national.com ADC121S101 Applications Information ADC121S101 Applications Information To enter shutdown mode, a conversion must be interrupted by bringing CS high anytime between the second and tenth falling edges of SCLK, as shown in Figure 8. Once CS has been brought high in this manner, the device will enter shutdown mode; the current conversion will be aborted and SDATA will enter TRI-STATE. If CS is brought high before the second falling edge of SCLK, the device will not change mode; this is to avoid accidentally changing mode as a result of noise on the CS line. (Continued) elapsed, CS may be idled either high or low until the next conversion. If CS is idled low, it must be brought high again before the start of the next conversion, which begins when CS is again brought low. After sixteen SCLK cycles, SDATA returns to TRI-STATE. Another conversion may be started, after tQUIET has elapsed, by bringing CS low again. 7.2 Shutdown Mode Shutdown mode is appropriate for applications that either do not sample continuously, or it is acceptable to trade throughput for power consumption. When the ADC121S101 is in shutdown mode, all of the analog circuitry is turned off. 20145016 FIGURE 8. Entering Shutdown Mode 20145017 FIGURE 9. Entering Normal Mode When the VA supply is first applied, the ADC121S101 may power up in either of the two modes: normal or shutdown. As such, one dummy conversion should be performed after start-up, as described in the previous paragraph. The part may then be placed into either normal mode or the shutdown mode, as described in Sections 7.1 and 7.2. When the ADC121S101 is operated continuously in normal mode, the maximum throughput is fSCLK / 20. Throughput may be traded for power consumption by running fSCLK at its maximum specified rate and performing fewer conversions per unit time, raising the ADC121S101 CS line after the 10th and before the 15th fall of SCLK of each conversion. A plot of typical power consumption versus throughput is shown in the Typical Performance Curves section. To calculate the power consumption for a given throughput, multiply the fraction of time spent in the normal mode by the normal mode power consumption and add the fraction of time spent in shutdown mode multiplied by the shutdown mode power consumption. Note that the curve of power consumption vs. throughput is essentially linear. This is because the power consumption in the shutdown mode is so small that it can be ignored for all practical purposes. To exit shutdown mode, bring CS back low. Upon bringing CS low, the ADC121S101 will begin powering up (power-up time is specified in the Timing Specifications table). This power-up delay results in the first conversion result being unusable. The second conversion performed after power-up, however, is valid, as shown in Figure 9. If CS is brought back high before the 10th falling edge of SCLK, the device will return to shutdown mode. This is done to avoid accidentally entering normal mode as a result of noise on the CS line. To exit shutdown mode and remain in normal mode, CS must be kept low until after the 10th falling edge of SCLK. The ADC121S101 will be fully powered-up after 16 SCLK cycles. 8.0 POWER MANAGEMENT The ADC121S101 takes time to power-up, either after first applying VA, or after returning to normal mode from shutdown mode. This corresponds to one "dummy" conversion for any SCLK frequency within the specifications in this document. After this first dummy conversion, the ADC121S101 will perform conversions properly. Note that the tQUIET time must still be included between the first dummy conversion and the second valid conversion. www.national.com 14 noise in the substrate that will degrade noise performance if that current is large enough. The larger the output capacitance, the more current flows through the die substrate and the greater is the noise coupled into the analog channel, degrading noise performance. To keep noise out of the power supply, keep the output load capacitance as small as practical. It is good practice to use a 100 Ω series resistor at the ADC output, located as close to the ADC output pin as practical. This will limit the charge and discharge current of the output capacitance and improve noise performance. (Continued) 9.0 POWER SUPPLY NOISE CONSIDERATIONS The charging of any output load capacitance requires current from the power supply, VA. The current pulses required from the supply to charge the output capacitance will cause voltage variations on the supply. If these variations are large enough, they could degrade SNR and SINAD performance of the ADC. Furthermore, discharging the output capacitance when the digital output goes from a logic high to a logic low will dump current into the die substrate, which is resistive. Load discharge currents will cause "ground bounce" 15 www.national.com ADC121S101 Applications Information ADC121S101 Physical Dimensions inches (millimeters) unless otherwise noted 6-Lead LLP Order Number ADC121S101CISD or ADC121S101CISDX NS Package Number SDB06A 6-Lead SOT-23 Order Number ADC121S101CIMF, ADC121S101CIMFX NS Package Number MF06A www.national.com 16 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. 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