NSC LM9812CCV

N
LM9812 30-Bit Color Linear CCD Sensor Processor
General Description
Features
The LM9812 is a high performance integrated signal processor/digitizer for color linear CCD image scanners. The LM9812
performs all the signal processing (correlated double sampling,
pixel rate offset and shading correction, color balance control,
and 10-bit analog-to-digital conversion) necessary to maximize
the performance of a wide range of linear CCD sensors.
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The LM9812 can be digitally programmed to work with a wide
variety of CCDs from different manufacturers, including both 3
output RGB and 2 output GRGB CCDs. An internal Configuration Register sets CCD and sampling timing to maximize performance, simplifying the design and manufacturing processes. For
complementary voltage reference see the LM4041-ADJ.
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Applications
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6 million pixels/s conversion rate (2MHz/channel x 3)
Pixel rate shading (gain) correction for individual pixels
eliminates errors from PRNU, illumination, etc.
Digitally programmed color balance controls
Pixel rate offset correction for highest quality in dark regions
Correlated Double Sampling for lowest noise
Reference and signal sampling points digitally controlled in
20ns increments
2x and 4x analog fast preview/low resolution modes
Digital control of CCD integration time
Generates all necessary CCD clock signals
Compatible with a wide range of color linear CCDs and
Contact Image Sensors (CIS)
TTL/CMOS input/output compatible
Key Specifications
Color Flatbed Document Scanners
Color Sheetfed Scanners
Multifunction Imaging Products
Digital Copiers
General Purpose Linear CCD Imaging
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Output Data Resolution
Pixel Conversion Rate (total)
Supply Voltage
Supply Voltage (Digital I/O)
Power Dissipation (typical)
10 Bits
6MHz
+5V±5%
+3.3V±10% or +5V±5%
390mW
CD9
GCLK
VREF LO OUT
VREF LO IN
VREF MID OUT
VREF MID IN
VREF HI OUT
VREF HI IN
AGND
VREF IN
VA
OSB
TEST
D9
D8
D7
D6
D5
VDI/O
D4
DGNDI/O
D3
D2
D1
D0
RD PIXEL
EOC
OCLK
CD0
MCLK
CD1
WR
CD2
RD
CD3
CS
LM9812CCV
CD4
SYNC
VD
RUN/STOP
DGND
ø1
CD5
ø2
CD6
RS
CD7
TR1
7 6 5 4 3 2 1 52 51 50 49 48 47
46
8
45
9
44
10
43
11
42
12
41
13
40
14
39
15
16
38
17
37
18
36
19
35
20
34
21 22 23 24 25 26 27 28 29 30 31 32 33
CD8
TR2
OSG
OSR
Connection Diagrams
Ordering Information
Commercial (0°C ≤ TA ≤ +70°C)
LM9812CCV
Package
V52A 52 Pin Plastic Leaded Chip Carrier
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
©1997 National Semiconductor Corporation
1
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LM9812 30-Bit Color Linear CCD Sensor Processor
December 1997
Block Diagram
VD
VA
Coarse Color
Balance PGAs
OSR
RED OS
from Sensor
VDI/O
Static
Offset
DACs
+²
+
x1-x3
CDS
OSG
Offset
DACR
GREEN OS
from Sensor
Blue Gain
Boost
OSB
BLUE OS
from Sensor
x1-x3
CDS
10-Bit,
6MHz
ADC
+²
+
x1-x3
CDS
x1or x3
CLAMP
Offset
DACG
+²
+
Offset
DACB
VREF IN
VREF LO OUT
VREF LO IN
VREF MID OUT
VREF MID IN
VREF HI OUT
VREF HI IN
Pixel-Rate Offset Subtractor
+
10 bits
+
-
Pixel-Rate
Shading Multiplier
TEST
Gain/Offset
Coefficients
CD0-CD9
10
GCLK
OCLK
Pixel Data Output/
Control Data I/O
WR
10
Pixel Data
Latch
CS
D0-D9
RD
EOC
RD PIXEL
SYNC
ø1
ø2
Control
Logic
MCLK
RUN/STOP
Configuration
Register
RS
TR1
TR2
AGND
DGND
2
DGNDI/O
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Absolute Maximum Ratings (Notes 1 & 2)
Operating Ratings (Notes 1 & 2)
+
Operating Temperature Range
TMIN≤TA≤TMAX
LM9812CCV
0°C≤TA≤+70°C
VA Supply Voltage
+4.75V to +5.25V
VD Supply Voltage
+4.75V to +5.25V
VDI/O Supply Voltage
+3.0V to +5.25V
≤ 100mV
|VA-VD|
VA-VDI/O
< -100mV
OSR, OSG, OSB, VREF IN
Input Voltage Range
-0.05V to VA + 0.05V
CD0-CD9, D0-D9, MCLK, SYNC,
RUN/STOP, CS, RD, WR, RD PIXEL
Input Voltage Range
-0.05V to VDI/O + 0.05V
Positive Supply Voltage (V =VA=VD=VDI/O)
With Respect to GND=AGND=DGND=DGNDI/O
6.5V
Voltage On Any Input or Output Pin
0.3V to V++0.3V
Input Current at any pin (Note 3)
±25mA
Package Input Current (Note 3)
±50mA
Package Dissipation at TA = 25°C (Note 4)
ESD Susceptibility (Note 5)
Human Body Model
2000V
Soldering Information
Infrared, 10 seconds (Note 6)
300°C
Storage Temperature
-65°C to +150°
Electrical Characteristics
The following specifications apply for AGND=DGND=DGNDI/O=0V, VA=VD=+5.0VDC, VDI/O=+5.0 or +3.3VDC, VREF IN = +2.0VDC,
fMCLK=24MHz, Rs=25Ω. Boldface limits apply for TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. (Notes 7, 8, & 12)
CCD/CIS Source Requirements for Full Specified Accuracy and Dynamic Range (Note 12)
VOS PEAK
Sensor’s Maximum Peak Differential
Signal Range
Color Balance PGA gain = 0.933
Color Balance PGA gain = 3.0
Color Balance PGA gain = 9.0
(Blue Channel, BOOST on)
Sensor’s Maximum Correctable Range
of Pixel-to-Pixel VWHITE Variation/Color
Range 0
Range 1
Range 2
1.0
0.33
0.11
V (min)
V (min)
V (min)
67 (1:3)
50 (1:2)
33 (1:1.5)
%
%
%
Coarse Color Balance PGA Characteristics
Monotonicity
5
bits (min)
V/V (max)
V/V (min)
G0 (Minimum PGA Gain)
PGA Setting = 0
0.93
0.90
0.97
G31 (Maximum PGA Gain)
PGA Setting = 31
3.00
2.85
3.20
V/V (max)
V/V (min)
GBLUE BOOST
Blue PGA Boost Setting = x3
3.00
2.72
3.27
V/V (max)
V/V (min)
±1.0
±4.0
% (min)
% (max)
6
bits (min)
Gain Error at any gain (Note 14)
Static Offset DAC Characteristics
Monotonicity
Offset DAC LSB size
In units of ADC LSBs
4.2
1.3
7.2
LSB (min)
LSB (max)
Offset DAC Adjustment Range
In units of ADC LSBs
±130
±118
LSB (min)
10
Bits (min)
ADC Characteristics
Resolution with No Missing Codes
ILE
Integral Linearity Error (Note 11)
±0.4
±1.5
LSB (max)
DNL
Differential Non-Linearity
-0.14
+0.32
-0.5
+1.0
LSB (min)
LSB (max)
2.00
1.83
2.17
(min)
(max)
System Characteristics
C
Analog Channel Gain Constant
3
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Electrical Characteristics (Continued)
The following specifications apply for AGND=DGND=DGNDI/O=0V, VA=VD=+5.0VDC, VDI/O=+5.0 or +3.3VDC, VREF IN = +2.0VDC,
fMCLK=24MHz, Rs=25Ω. Boldface limits apply for TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. (Notes 7, 8, & 12)
VOS1
Pre-PGA Analog Channel Offset Error
CCD Mode
In units of ADC LSBs
+5
-40
+40
LSB (min)
LSB (max)
VOS1
Pre-PGA Analog Channel Offset Error
CIS Mode
In units of ADC LSBs
+32
-65
+135
LSB (min)
LSB (max)
VOS2
Post-PGA Analog Channel Offset Error
In units of ADC LSBs
-5
-40
+30
LSB (min)
LSB (max)
Reference and Analog Input Characteristics
OSR, OSG, OSB Input Capacitance
5
pF
OSR, OSG, OSB Input Leakage Current
Measured with OS = 2.5VDC
2
20
nA (max)
VREF IN Input Leakage Current
Measured with VREF IN = 2.0VDC
4
20
nA (max)
DC and Logic Electrical Characteristics
The following specifications apply for AGND=DGND=DGNDI/O=0V, VA=VD=+5.0VDC, VDI/O=+5.0 or +3.3VDC, VREF IN = +2.0VDC,
fMCLK=24MHz, Rs=25Ω. Boldface limits apply for TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. (Notes 7 & 8)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 10)
Units
(Limits)
D0-D9, CD0-CD9, MCLK, RUN/STOP, SYNC, CS, RD, WR, RD PIXEL Digital Input Characteristics
VIN(1)
Logical “1” Input Voltage
VDI/O=5.25V
VDI/O=3.6V
2.0
2.0
V (min)
V (min)
VIN(0)
Logical “0” Input Voltage
VDI/O=4.75V
VDI/O=3.0V
0.8
0.7
V (max)
V (max)
IIN
Input Leakage Current
VIN=VD
VIN=DGND
CIN
Input Capacitance
0.1
-0.1
µA
µA
5
pF
D0-D9, EOC, GCLK, OCLK, SYNC Digital Output Characteristics
VOUT(1)
Logical “1” Output Voltage
VDI/O=4.75V, IOUT=-360µA
VDI/O=4.75V, IOUT=-10µA
VDI/O=3.0V, IOUT=-360µA
VDI/O=3.0V, IOUT=-10µA
2.4
4.4
2.1
2.5
V (min)
V (min)
V (min)
V (min)
VOUT(0)
Logical “0” Output Voltage
VDI/O=5.25V, IOUT=1.6mA
VDI/O=3.6V, IOUT=1.6mA
0.4
0.4
V (max)
V (max)
TRI-STATE® Output Current
(D0-D9 only)
VOUT=DGND
VOUT=VD
IOUT
0.1
-0.1
µA
µA
Ø1, Ø2, RS, TR1, TR2 Digital Output Characteristics
VOUT(1)
Logical “1” Output Voltage
VD=4.75V, IOUT=-360µA
VD=4.75V, IOUT=-10µA
2.4
4.4
V (min)
V (min)
VOUT(0)
Logical “0” Output Voltage
VD=5.25V, IOUT=1.6mA
0.4
V (max)
Power Supply Characteristics
IA
Analog Supply Current
Operating
Standby
60
7
85
10
mA (max)
mA (max)
ID
Digital Supply Current
Operating
Standby
4.7
0.1
10
1.0
mA (max)
mA (max)
4
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DC and Logic Electrical Characteristics (Continued)
The following specifications apply for AGND=DGND=DGNDI/O=0V, VA=VD=+5.0VDC, VDI/O=+5.0 or +3.3VDC, VREF IN = +2.0VDC,
fMCLK=24MHz, Rs=25Ω. Boldface limits apply for TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. (Notes 7 & 8)
Symbol
IDI/O
Parameter
Digital I/O Supply Current
Conditions
Operating, VDI/O=5.0V
Standby, VDI/O= 5.0V
Operating, VDI/O=3.3V
Standby, VDI/O= 3.3V
Typical
(Note 9)
Limits
(Note 10)
Units
(Limits)
12
5
2
0.3
30
20
10
3
mA (max)
mA (max)
mA (max)
mA (max)
AC Electrical Characteristics, MCLK Independent
The following specifications apply for AGND=DGND=DGNDI/O=0V, VA=VD=VDI/O=+5.0VDC, VREF IN = +2.0VDC, fMCLK=24MHz,
tMCLK=1/fMCLK, tr=tf=5ns, Rs=25¾, CL (databus loading) = 50pF/pin.
Boldface limits apply for TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. (Notes 7 & 8)
Symbol
fMCLK
Limits
(Note 10)
Units
(Limits)
Maximum MCLK Frequency
Minimum MCLK Frequency
24
4
MHz (min)
MHz (max)
MCLK Duty Cycle
40
60
% (min)
% (max)
Parameter
Conditions
Typical
(Note 9)
tSETUP (OUT)
Coefficient Data valid before latching
edge of OCLK or GCLK
GCLK and OCLK as
outputs
12
20
ns (min)
tHOLD (OUT)
Coefficient Data held after latching
edge of OCLK or GCLK
GCLK and OCLK as
outputs
-10
0
ns (min)
tSETUP (IN)
Coefficient Data Valid before latching
edge of OCLK or GCLK
GCLK and OCLK as
inputs
0
5
ns (min)
tHOLD (IN)
Coefficient Data held after latching
edge of OCLK or GCLK
GCLK and OCLK as
inputs
0
5
ns (min)
tGCLK-EOC
Rising edge of GLCK to falling edge
of EOC (GCLK as output)
tGCLK-OCLK
Rising edge of GLCK to falling edge
of OCLK (GCLK and OCLK as
outputs)
2
ns
2 bus / 2 clock mode
1
ns
Rising edge of EOC to rising edge of
OLCK (OCLK as output)
2 clock mode
1
ns
Rising edge of OLCK to falling edge
of GLCK (GCLK and OCLK as
outputs)
2 clock mode
3
ns
tEOC-GCLK
Rising edge of EOC to falling edge of
GLCK (GCLK as output)
2 bus mode
2
ns
tDACC
RD or RD_PIXEL low to D0-D9 data
valid
15
41
ns (max)
tD1H, D0H
RD or RD_PIXEL high to D0-D9 data
tri-state
13
20
ns (max)
tCS SETUP
CS setup of RD or WR
0
ns (min)
tCS HOLD
CS hold after RD or WR
0
ns (min)
D0-D9 data valid before rising edge
of WR (setup time)
5
ns (min)
tEOC-OCLK
tOCLK-GCLK
tWR SETUP
5
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AC Electrical Characteristics, MCLK Independent (Continued)
The following specifications apply for AGND=DGND=DGNDI/O=0V, VA=VD=VDI/O=+5.0VDC, VREF IN = +2.0VDC, fMCLK=24MHz,
tMCLK=1/fMCLK, tr=tf=5ns, Rs=25¾, CL (databus loading) = 50pF/pin.
Boldface limits apply for TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. (Notes 7 & 8)
Symbol
Parameter
tWR HOLD
D0-D9 data valid after rising edge of
WR (hold time)
Conditions
Typical
(Note 9)
Limits
(Note 10)
Units
(Limits)
0
ns (min)
AC Electrical Characteristics, MCLK Dependent
The following specifications apply for AGND=DGND=DGNDI/O=0V, VA=VD=VDI/O=+5.0VDC, VREF IN = +2.0VDC, fMCLK=24MHz,
tMCLK=1/fMCLK, tr=tf=5ns, Rs=25Ω, CL (databus loading) = 50pF/pin. Refer to Table 2: Configuration Register Parameters for limits
labeled C.R. Boldface limits apply for TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. (Notes 7 & 8)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 10)
Units
(Limits)
MCLKs (max)
tR/S START
Rising edge of RUN/STOP to Rising
edge of SYNC
SYNC OUT mode
16
tSTART
Rising edge of SYNC to rising edge
of TR1
SYNC IN mode
SYNC IN mode
SYNC OUT mode
MCLKs (min)
1+tGUARDBAND
tGUARDBAND
13+tGUARDBAND 14+tGUARDBAND MCLKs (max)
tGUARDBAND
tGUARDBAND
MCLKs
tSYNC END
Falling edge of SYNC to last rising
edge of EOC
SYNC IN mode
SYNC OUT mode
tSYNC LOW
SYNC low time
SYNC IN mode
SYNC OUT mode
9
0
MCLKs (max)
MCLKs (max)
8
# of EOL
PIxels - 4
MCLKs (min)
TR1, TR2 Transfer Pulse Width
C.R.
MCLKs
TR1, TR2 Transfer Pulse Guardband
C.R.
MCLKs
tRS WIDTH
Reset Pulse Width
C.R.
MCLKs
tCLAMP ON
Start of Optical Black clamping
period
C.R.
MCLKs
tCLAMP OFF
End of Optical Black clamping period
C.R.
MCLKs
12
24
MCLKs
MCLKs
tTR1 WIDTH,
tTR2 WIDTH
tGUARD
Standard Mode
Even/Odd Mode
8
0
Pixel periods
tØ
Ø1, Ø2 clock period
tRS
RS pulse position from Ø1 edge
C.R.
MCLKs
tHOLD REF
Reference hold (sample) position
from RS edge
C.R.
MCLKs
tHOLD SIG
Signal hold (sample) position from
RS edge
C.R.
MCLKs
tOCLK LOW
OCLK low time (OCLK as Output)
2 bus mode
1bus mode
2*tMCLK
1*tMCLK
ns
tOCLK HIGH
OCLK high time (OCLK as Output)
2 bus mode
1 bus mode
2*tMCLK
3*tMCLK
ns
tGCLK LOW
GCLK low time (GCLK as Output)
2 bus mode
1 bus mode
2*tMCLK
1*tMCLK
ns
tGCLK HIGH
GCLK high time (GCLK as Output)
2 bus mode
1 bus mode
2*tMCLK
3*tMCLK
ns
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AC Electrical Characteristics, MCLK Dependent (Continued)
The following specifications apply for AGND=DGND=DGNDI/O=0V, VA=VD=VDI/O=+5.0VDC, VREF IN = +2.0VDC, fMCLK=24MHz,
tMCLK=1/fMCLK, tr=tf=5ns, Rs=25Ω, CL (databus loading) = 50pF/pin. Refer to Table 2: Configuration Register Parameters for limits
labeled C.R. Boldface limits apply for TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. (Notes 7 & 8)
Symbol
Parameter
Typical
(Note 9)
Conditions
Limits
(Note 10)
Units
(Limits)
tEOC LOW
EOC low time
2*tMCLK
ns
tEOC HIGH
EOC high time
2*tMCLK
ns
tDATA VALID
D0-D9 data valid from falling (Data
Read Phase = 0°) or rising (Data Read
Phase = 180°) edge of EOC
4*tMCLK-20ns
ns (min)
1 bus mode w/ext OCLK
tMCLK + 40ns
4*tMCLK
ns (min)
ns (max)
2 bus mode w/ext OCLK
40ns
3*tMCLK
ns (min)
ns (max)
w/ext GCLK
40ns
3*tMCLK
ns (min)
ns (max)
OCLK rising edge to EOC falling edge
tOCLK-EOC 1
(OCLK IN)
(Gain Coefficient Write Phase = 0°),
OCLK falling edge to EOC falling edge
(Gain Coefficient Write Phase = 180°)
OCLK rising edge to EOC rising edge
tOCLK-EOC 2
(OCLK IN)
(Gain Coefficient Write Phase = 0°),
OCLK falling edge to EOC rising edge
(Gain Coefficient Write Phase = 180°)
GCLK rising edge to EOC falling edge
tGCLK-EOC
(GCLK IN)
(Gain Coefficient Write Phase = 0°),
GCLK falling edge to EOC falling edge
(Gain Coefficient Write Phase = 180°)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional,
but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply
only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND=AGND=DGND=DGNDI/O=0V, unless otherwise specified.
Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (VIN<GND or VIN>VA or VD), the current at that pin should be limited to 25mA. The 50mA maximum package input current rating limits the number of pins that can simultaneously safely exceed the power supplies with an input current of 25mA to two.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, ΘJA and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJmax - TA) / ΘJA. TJmax = 150°C for this device. The typical thermal resistance (ΘJA) of this part when board mounted
is 52°C/W for the V52A PLCC package.
Note 5: Human body model, 100pF capacitor discharged through a 1.5kΩ resistor.
Note 6: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any post 1986 National Semiconductor Linear Data Book for other methods of soldering surface mount devices.
Note 7: A Zener diode clamps the OS analog inputs to AGND as shown below. This input protection, in combination with the external clamp capacitor and the output
impedance of the sensor, prevents damage to the LM9812 from transients during power-up.
To Internal
Circuitry
OS Input
AGND
Note 8: To guarantee accuracy, it is required that VA and VD be connected together to the same power supply with separate bypass capacitors at each supply pin.
Note 9: Typicals are at TJ=TA=25°C, fMCLK = 24MHz, and represent most likely parametric norm.
Note 10: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 11: Integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that best fits the actual transfer function of the ADC.
Note 12: VREF is defined as the CCD OS voltage for the reference period following the reset feedthrough pulse. VWHITE is defined as the peak CCD pixel output voltage for
a white (full scale) image with respect to the reference level, VREF . VRFT is defined as the peak positive deviation above VREF of the reset feedthrough pulse. The maximum
correctable range of pixel-to-pixel VWHITE variation is defined as the maximum variation in VWHITE (due to PRNU, light source intensity variation, optics, etc.) that the
7
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LM9812 can correct for using its internal PGA.
CCD Output Signal
VRFT
VWHITE
VREF
Note 13: Reference voltages below 1.80V may decrease SNR. Reference voltages above 2.20V may cause linearity (headroom) errors inside the LM9812. The
LM4041DIM3-ADJ (SOT-23 package) or the LM4041DIZ-ADJ (TO-92 package) bandgap voltage references are recommended for this application.
Note 14:
Gain
PGA Gain Error is the maximum difference between the measured gain for any PGA code and the ideal gain calculated by using the formula
PGA code
32
V
---- = G + X --------------------------- where X = ( G – G ) ------ .
0
31
0 31
PGA  V
32
8
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Pin Descriptions
General Digital I/O
Sensor Driver Signals
ø1
Digital Output. Clock signal, phase 1.
ø2
Digital Output. Clock signal, phase 2.
RS
Digital Output. Reset pulse.
TR1, TR2
Digital Output. Transfer pulses.
MCLK
Digital Input. This is the 24MHz (typical) master
system clock.
SYNC
Digital Input (SYNC_IN mode) /
Digital Output (SYNC_OUT mode).
In the SYNC_IN mode, a low-to-high transition
on this input begins a line scan operation. The
line scan operation terminates when SYNC is
taken low. In the SYNC_OUT mode, the rising
edge of this output indicates the start of a line
of data and the falling edge indicates the end of
a line of data.
RUN/STOP
Digital Input. In the SYNC_OUT mode, this
input should be taken high to begin converting
a series of lines, and taken low to stop converting a series of lines. In the SYNC_IN mode this
input is ignored.
Analog I/O
OSR, OSG,
OSB,
Analog Inputs. These inputs (for Red, Green,
and Blue) should be tied to the sensor’s OS
(Output Signal) through DC blocking capacitors.
VREF IN
Analog Input. This is the system reference voltage input and should be connected to a 2.0V
voltage source and bypassed to AGND with a
0.05µF monolithic capacitor.
VREF LO OUT,
VREF LO IN
Analog Output/Input. VREF LO OUT is a voltage
equal to 0.49VA - VREF IN/2 (1.45V for VREF
IN=2V) developed by the LM9812. It should be
tied to VREF LO IN and bypassed to AGND with
a 0.05µF monolithic capacitor.
Digital Coefficient I/O
CD0 (LSB) CD9 (MSB)
Digital Inputs. This is the 10 bit data path for
the pixel-rate gain coefficient and offset data.
OCLK
Digital Input/Output. This is the signal that is
used to clock the Offset coefficients into the
LM9812 through the CD0-CD9 databus. This
can be either an output or an input depending
on the state of bit 7 of Register 9. Data is
latched on the rising edge of OCLK.
GCLK
Digital Input/Output. This is the signal that is
used to clock the Shading (gain) coefficients
into the LM9812 through the CD0-CD9 databus. This can be either an output or an input
depending on the state of bit 7 of Register 9.
Data is latched on the rising edge of GCLK.
VREF MID OUT, Analog Output/Input. VREF MID OUT is a voltage
equal to 0.49VA (2.45V for VREF IN=2V) develVREF MID IN
oped by the LM9812. It should be tied to VREF
MID IN and bypassed to AGND with a 0.05µF
monolithic capacitor.
VREF HI OUT,
VREF HI IN
Analog Output/Input. VREF HI OUT is a voltage
equal to 0.49VA + VREF IN/2 (3.45V for VREF
IN=2V) developed by the LM9812. It should be
tied to VREF HI IN and bypassed to AGND with a
0.05µF monolithic capacitor.
Configuration Register I/O
CS
Digital Input. This is the Chip Select signal for
reading or writing to the Configuration Register
through the D0-D9 databus. This input must be
low in order to enable writing to or reading from
the Configuration Register.
RD
Digital Input. A low signal on this input, when
SYNC and CS are also low, places the data in
the currently addressed Configuration Register on the D0-D9 databus. A RD cycle also
resets the internal address latching state
machine. NOTE: If this pin is taken low when
CS is high, the D0-D9 databus will come out of
tri-state and drive random data onto the bus.
WR
Digital Output I/O
Digital Input. This input, when simultaneously
asserted along with CS, transfers the data on
the D0-D9 databus to the LM9812. If this is the
first write in the cycle, this data is the address
to be read or written to. If this is the second
write in the cycle, this data is the data to be
written to the Configuration Register at the currently latched address. Writing to the Configuration Register is independent of the state of
SYNC.
D0 (LSB)D9 (MSB)
Digital Inputs/Outputs. When SYNC is high and
RD PIXEL is low, this data bus outputs the 10
bit digital output data during line scan. This
databus is also used for reading or writing to
the Configuration Register using the RD, WR
and CS signals. Writing to the Configuration
Register can occur at any time. Reading from
the Configuration Register can only occur
when SYNC is low.
EOC
Digital Output. This is the End Of Conversion
signal from the LM9812 indicating that new
pixel data is available on the D0-D9 databus.
RD PIXEL
Digital Input. When SYNC is high, taking this
input low places the digital pixel data stored in
the output latch onto the D0-D9 bus. This input
is ignored when SYNC is low.
Test
TEST
9
Analog Output. This pin can be used to view
the CDS and Clamp signals. See Register 27,
bits 6 and 7.
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Analog Power
VA
This is the positive supply pin for the analog
supply. It should be connected to a voltage
source of +5V and bypassed to AGND with a
0.1µF monolithic capacitor in parallel with a
10µF tantalum capacitor.
AGND
This is the ground return for the analog supply.
Digital Power
VD
This is the positive supply pin for the digital
supply. It should be connected to a voltage
source of +5V and bypassed to DGND with a
0.1µF monolithic capacitor.
DGND
This is the ground return for the digital supply.
VDI/O
This is the positive supply pin for the digital
supply for the LM9812’s I/O. It should be connected to a voltage source of +3V to +5V and
bypassed to DGNDI/O with a 0.1µF monolithic
capacitor. If the supply for this pin is different
than the supply for VA and VD, it should also be
bypassed with a 10µF tantalum capacitor.
DGNDI/O
This is the ground return for the digital supply
for the LM9812’s I/O.
10
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Timing Diagrams
RUN/STOP
SYNC (OUTPUT)
Ø1
Line 1
Line 2
Line n
Diagram 1: SYNC OUT Mode Timing, Multiple Lines
SYNC (INPUT)
Ø1
Line 1
Line 2
Line n
(truncated)
Diagram 2: SYNC IN Mode Timing, Multiple Lines
RUN/
STOP
Transfer
Dummy
Black
Valid Pixels
Additional Integration Time
SYNC
(OUTPUT)
Ø1
TR1
RS
CLAMP
1
2
3
OCLK
GLCK
EOC
Diagram 3: SYNC OUT Mode Timing, One Line
11
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Transfer
Dummy
Black
Valid Pixels
SYNC
(INPUT)
Ø1
TR1
RS
CLAMP
1
2
3
OCLK
GLCK
EOC
Diagram 4: SYNC In Mode Timing, One Line
RUN/STOP
tR/S START
SYNC (OUTPUT)
tSTART
Ø1
TR1
Diagram 5: Start of Line Scan, SYNC OUT Mode, One TR Pulse
SYNC (INPUT)
tSTART
Ø1
TR1
Diagram 6: Start of Line Scan, SYNC IN Mode, One TR Pulse
tSYNC LOW
8MCLK min
SYNC
tSYNC END
8MCLK max
EOC
Diagram 7: Timing for End of Line/Start of Next Line
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tTR1 WIDTH
TR1 (TR1 Polarity = 0)
TR1 (TR1 Polarity = 1)
tGUARD
tGUARD
Ø1
Ø2
Diagram 8: TR Pulse Timing, One TR Pulse
tTR1 WIDTH
TR1 (TR1 Polarity = 0)
TR1 (TR1 Polarity = 1)
tGUARD
tTR2 WIDTH
tGUARD
TR1 (TR2 Polarity = 0)
TR2 (TR2 Polarity = 1)
tGUARD
tGUARD
Ø1
Ø2
Diagram 9: TR Pulse Timing, Two TR Pulses
tRS WIDTH
RS (RS Polarity = 0)
RS (RS Polarity = 1)
Diagram 10: RS Pulse Polarity
RS
n-1
n
n-1
n+1
n
n+1
OS
tCLAMP ON
Clamp Signal
(Internal)
n-1
n
tCLAMP OFF
Diagram 11: CCD Clamping Timing
13
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tØ
Ø1
(Even/Odd Mode)
Ø2
(Even/Odd Mode)
tØ
Ø1
(Standard Mode)
Ø2
(Standard Mode)
tRS
tRS WIDTH
RS
n-1
n
n-1
n+1
n
n+1
OS
t HOLD SIG
tHOLD REF
CDS
(Internal)
Hold Ref(n-1)
Hold Signal(n-1)
Hold Ref(n)
Hold Signal(n)
Hold Ref(n-1)
Diagram 12: CDS Timing
Ø1(Std Mode)
Ø2 (Std Mode)
Ø1(Even/Odd)
Ø2 (Even/Odd)
RS
OS
pixel 1
pixel i
(dummy)
(dummy)
pixel i +1
pixel i +j
(black)
(black)
(data)
CDS
Clamp
Note: i = value programmed in Dummy Pixel Register
j = value programmed in Optical Black Register
Diagram 13: Dummy Pixel and Optical Black Pixel Timing
14
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tSETUP
tGLCK-OCLK
tHOLD
tOCLK-GCLK
OCLK (from LM9812)
GCLK (from LM9812)
tSETUP
tGCLK-EOC
tHOLD
CD0-CD9 B Gainn-1
R Offn
R Gainn
G Offn
G Gainn
EOC
tEOC-OCLK
G Output Datan-1
D0-D9
B Output Datan-1
Diagram 14: Digital Data Timing, Output Data and Coefficient Data on separate buses, two clocks
(OCLK and GCLK) for coefficient data, OCLK and GCLK generated by LM9812, RD PIXEL held low.
tSETUP
tHOLD
GCLK (from LM9812)
tSETUP
tGCLK-EOC
CD0-CD9 B Gainn-1
tHOLD
R Offn
R Gainn
G Offn
G Gainn
EOC
tEOC-GCLK
G Output Datan-1
D0-D9
B Output Datan-1
Diagram 15: Digital Data Timing, output data and coefficient data on separate buses, one clock
(GCLK) for coefficient data, GCLK generated by LM9812, RD PIXEL held low.
tSETUP
tOCLK-GCLK
tHOLD
OCLK (from LM9812)
GCLK (from LM9812)
tSETUP
tEOC-OCLK
tGCLK-EOC
tHOLD
CD0-CD9
B Gainn-1
R Offsetn R Gainn
G Offsetn G Gainn
EOC = RD PIXEL
D0-D9
EXTERNAL DATABUS
G Output Datan-1
G Output Datan-1 R Offn
B Output Datan-1
R Gainn B Output Datan-1 G Offn
R Outn
B Gainn R Outn
Diagram 16: Digital Data Timing, output data and coefficient data on same buses, two clocks
(OCLK and GCLK) for coefficient data, OCLK and GCLK generated by LM9812.
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tSETUP
tSETUP
tHOLD
tGCLK-EOC
tHOLD
GCLK (from LM9812)
CD0-CD9
B Gainn-1
R Offsetn R Gainn
G Offsetn G Gainn
EOC = RD PIXEL
D0-D9
EXTERNAL DATABUS
G Output Datan-1
R Outn
B Output Datan-1
G Output Datan-1 R Offn
R Gainn B Output Datan-1 G Offn
G Gainn R Outn
Diagram 17: Digital Data Timing, output data and coefficient data on same buses, one clock
(GCLK) for coefficient data, GCLK generated by LM9812.
tSETUP
tHOLD
OCLK (to LM9812)
GCLK (to LM9812)
tSETUP
tGCLK-EOC (GCLK IN)
tHOLD
CD0-CD9 B Gainn-1
R Offn
R Gainn
G Offn
G Gainn
EOC
tOCLK-EOC 2 (OCLK IN)
G Output Datan-1
D0-D9
B Output Datan-1
Diagram 18: Digital Data Timing, output data and coefficient data on separate buses, two clocks (OCLK and
GCLK) for coefficient data, OCLK and GCLK input to LM9812, OCLK and GLCK phase = 0°, RD PIXEL held low.
tSETUP
tHOLD
OCLK (to LM9812)
GCLK (to LM9812)
tSETUP
tHOLD
CD0-CD9
R Gainn-1
G Offn
G Gainn
B Offn
B Gainn
EOC
tOCLK-EOC 2 (OCLK IN)
D0-D9
tGCLK-EOC (GCLK IN)
G Output Datan-1
B Output Datan-1
Diagram 19: Digital Data Timing, output data and coefficient data on separate buses, two clocks (OCLK and
GCLK) for coefficient data, OCLK and GCLK input to LM9812, OCLK and GLCK phase = 180°, RD PIXEL held low.
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tSETUP
tHOLD
OCLK (to LM9812)
GCLK (to LM9812)
tSETUP
tHOLD
CD0-CD9
B Gainn-1
R Offsetn R Gainn
G Offsetn G Gainn
tGCLK-EOC (GCLK IN)
tOCLK-EOC 1 (OCLK IN)
EOC
G Output Datan-1
D0-D9
R Outn
B Output Datan-1
Diagram 20: Digital Data Timing, output data and coefficient data on same bus, two clocks (OCLK and
GCLK) for coefficient data, OCLK and GCLK input to LM9812, OCLK and GLCK phase = 0°.
tSETUP
tHOLD
OCLK (to LM9812)
GCLK (to LM9812)
tSETUP
tHOLD
CD0-CD9
R Gainn-1
G Offsetn G Gainn
B Offsetn
tGCLK-EOC (GCLK IN)
B Gainn
tOCLK-EOC 1 (OCLK IN)
EOC
D0-D9
G Output Datan-1
R Outn
B Output Datan-1
Diagram 21: Digital Data Timing, output data and coefficient data on same bus, two clocks (OCLK and
GCLK) for coefficient data, OCLK and GCLK input to LM9812, OCLK and GLCK phase = 180°.
DATA (INTERNAL)
Green Internal Datan-1
Blue Internal Datan-1
EOC
RD PIXEL
tDATAVALID
tDACC
D0-D9
Green Output Datan-1
Bn-1
tD1H, tD0H
B Output Datan-1
Diagram 22: RD PIXEL Output Timing (Data Read Phase = 0°)
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Green Internal Datan-1
DATA (INTERNAL)
Blue Internal Datan-1
EOC
tDATAVALID
RD PIXEL
tDACC
Green Output Datan-1
D0-D9
tD1H, tD0H
B Output Datan-1
Bn-1
Diagram 23: RD PIXEL Output Timing (Data Read Phase = 180°)
tCS SETUP
tCS HOLD
tCS SETUP
tCS HOLD
CS
WR
tWR SETUP
tWR SETUP
tWR HOLD
D0-D7
ADDRESS
tWR HOLD
DATA
Note: To read from the Configuration Register, SYNC must be low, either by driving SYNC low (in SYNC IN mode), or taking RUN/STOP low and waiting for SYNC to go low at the end of a line (in SYNC OUT mode). The Configuration Register can be written to independent of the state of SYNC.
Diagram 24: Writing to the Configuration Register, RD held high.
SYNC
tCS SETUP
tCS HOLD
tCS SETUP
tCS HOLD
CS
WR
RD
tWR SETUP
tWR HOLD
D0-D7
tDACC
ADDRESS
tD1H, tD0H
DATA
Note: To read from the Configuration Register, SYNC must be low, either by driving SYNC low (in SYNC IN mode), or taking RUN/STOP low and waiting for SYNC to go low at the end of a line (in SYNC OUT mode). The Configuration Register can be written to independent of the state of SYNC.
Diagram 25: Reading the Configuration Register
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Table 1: Configuration Register Address Table
Address
(Decimal)
Address
(Binary)
Data Bits
A4 A3 A2 A1 A0
0
1
2
3
4
5
6
7
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
D7
D6
D5
-
-
Sign
D3
D2
D1
D0
MSB
LSB
Static Offset (Green)
-
-
Sign
MSB
LSB
Static Offset (Blue)
-
-
Sign
MSB
LSB
Coarse Color Balance PGA (Red)
-
-
-
MSB
LSB
Coarse Color Balance PGA (Green)
-
-
-
MSB
LSB
Coarse Color Balance PGA (Blue)
x3
-
-
MSB
LSB
Internal Offset Subtractor Coefficient
MSB
LSB
Internal Gain Multiplier Coefficient
1
0
D4
Static Offset (Red)
LSB
Internal Gain Multiplier Coefficient (LM9812 only)
-
-
-
-
-
-
MSB
Misc Group 1
9
10
11
12
13
14
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
0
1
1
0
0
1
1
0
1
1
1
1
1
1
16
1
0
0
0
0
18
19
20
1
1
1
0
0
0
0
0
0
0
1
0
1
1
0
Number of Number of Multiplier
Multiplier
Multiplier
Offset
Coefficient Databusses Gain Range Gain Range Coefficient Coefficient
Clocks
in System
1
0
Source
Source
Number of Dummy Pixels
MSB
LSB
Number of Optical Black Pixels
MSB
LSB
Number of Active Pixels (LSB)
LSB
Number of Active Pixels (MSB)
-
-
1
0
1
0
MSB
Number of End of Line Integration Pixels (LSB)
0
0
1
-
0
15
17
Internal
External
Coefficient
Clock
LSB
Number of End of Line Integration Pixels (MSB)
-
-
MSB
-
-
MSB
TR1 Pulse Duration
LSB
TR2 Pulse Duration
-
-
MSB
LSB
TR1/TR2 Guardbands
-
-
MSB
LSB
Optical Black Clamp Start
-
-
-
MSB
LSB
Optical Black Clamp End
-
-
-
19
MSB
LSB
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Address
(Decimal)
Address
(Binary)
Data Bits
A4 A3 A2 A1 A0
21
22
23
1
1
1
0
0
0
1
1
1
0
1
1
1
0
1
D7
D6
D5
D4
D3
Reset Pulse Width
Bit 2
D2
D1
D0
Reset Pulse Position
Bit 0
Bit 4
Bit 0
Reference Sample Position
-
-
-
Bit 4
Bit 0
Signal Sample Position
-
-
-
Bit 4
Bit 0
Misc Group 2
24
1
1
0
0
0
Signal
Polarity
Preview 1
Power
Down
8 or 10 bit
Coefficient
Bus
Preview 2
Internal/
External
SYNC
pulse
TR Pulse
Mode
(1 or 2
Pulses)
Red/Blue
Order for
2 Output
sensors
3 or 2
Output
sensor
Standard
or
Odd/Even
sensor
Misc Group 3
25
1
1
0
0
1
-
TR2 Enable TR1 Enable RS Enable Ø2 Enable Ø1 Enable
Misc Group 4
26
1
1
0
1
0
27
1
1
0
1
1
28
1
1
1
0
0
Gain
Offset
Coefficient Coefficient Data Read Ø1 Polarity TR2 Pulse
Write
Write
Phase
During TR1 Polarity
Phase
Phase
TR1 Pulse
Polarity
RS Pulse
Polarity
Ø1/Ø2
Polarity
0
0
0
0
0
0
Test Mode 1
TB7
TB6
0
0
0
Test Mode 2
0
0
0
0
0
Table 2: Configuration Register Parameters
Note: tMCLK = 1/fMCLK = 1 MCLK period. Examples given in parenthesis are for fMCLK = 24MHz (tMCLK = 41.66ns).
Parameter
(Address)
Red
Offset DAC (0)
Green
Offset DAC (1)
Blue
Offset DAC (2)
Control Bits
D5
(SIGN)
0
0
0
•••
0
0
1
1
1
•••
1
1
D4
(MSB)
0
0
0
•••
1
1
0
0
0
•••
1
1
D3
D2
D1
0
0
0
•••
1
1
0
0
0
•••
1
1
0
0
0
•••
1
1
0
0
0
•••
1
1
0
0
1
•••
1
1
0
0
1
•••
1
1
20
Result
D0
(LSB)
0
1
0
•••
0
1
0
1
0
•••
0
1
Typical Offset
(in ADC LSBs)
0.00
+4.2
+8.4
•••
+126.0
+130.2
0.00
-4.2
-8.4
•••
-126.0
-130.2
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Table 2: Configuration Register Parameters (Continued)
Note: tMCLK = 1/fMCLK = 1 MCLK period. Examples given in parenthesis are for fMCLK = 24MHz (tMCLK = 41.66ns).
Parameter
(Address)
Red PGA
(3)
Green PGA
(4)
Blue PGA
(5)
Control Bits
D7
D4
(MSB)
0
0
0
•••
1
1
1
0
0
0
•••
0
0
0
D7
Coarse Color
Balance PGA
(Blue with x3
multiplier bit set)
(5)
1
1
1
•••
1
1
1
Result
D3
D2
D1
0
0
0
•••
1
1
1
0
0
0
•••
1
1
1
0
0
1
•••
0
1
1
D4
(MSB)
0
0
0
•••
1
1
1
D3
D2
D1
0
0
0
•••
1
1
1
0
0
0
•••
1
1
1
0
0
1
•••
0
1
1
D0
(LSB)
0
1
0
•••
1
0
1
Typical Gain
(V/V)
0.93
1.00
D0
(LSB)
0
1
0
•••
1
0
1
Typical Gain
(V/V)
2.79
3.00
D0
(LSB)
0
1
0
•••
1
0
1
Offset
(in ADC LSBs)
0
1
2
•••
253
254
255
•••
3.00
•••
9.00
Internal
Offset
Subtractor
Coefficient
(6)
D7
(MSB)
0
0
0
•••
1
1
1
Internal
Multiplier
Gain
Coefficient
(7, 8)
D9
(MSB)
0
0
0
•••
1
1
1
Internal/External
Coefficient
Clocks (9)
D7
0
1
External Coefficient Clock Source
Internal Coefficient Clock Source
Number of
Coefficient
Clocks (9)
D5
0
1
GCLK and OCLK
GCLK only
Number of
Databuses in
System (9)
D4
0
1
2 Databuses
1 Databus
D6
D5
D4
D3
D2
D1
0
0
0
•••
1
1
1
0
0
0
•••
1
1
1
0
0
0
•••
1
1
1
0
0
0
•••
1
1
1
0
0
0
•••
1
1
1
0
0
1
•••
0
1
1
D8
D7
•••
•••
D2
D1
0
0
0
•••
1
1
1
0
0
0
•••
1
1
1
•••
0
0
0
•••
1
1
1
0
0
1
•••
0
1
1
•••
21
D0
(LSB)
0
1
0
•••
1
0
1
Gain
(V/V)
See
Equation 5
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Table 2: Configuration Register Parameters (Continued)
Note: tMCLK = 1/fMCLK = 1 MCLK period. Examples given in parenthesis are for fMCLK = 24MHz (tMCLK = 41.66ns).
Parameter
(Address)
Control Bits
Result
D2
0
1
0
1
Multiplier Gain
Range
(9)
D3
0
0
1
1
Multiplier
Coefficient
Source
(9)
D1
0
1
External CD0-CD9 Bus
Internal Register
Offset Coefficient
Source
(9)
D0
0
1
External CD0-CD9 Bus
Internal Register
Dummy Pixels
(Minimum Value
is 0)
(10)
D7
0
0
0
•••
1
1
1
D6
0
0
0
•••
1
1
1
D5
0
0
0
•••
1
1
1
D4
0
0
0
•••
1
1
1
D3
0
0
0
•••
1
1
1
D2
0
0
0
•••
1
1
1
D1
0
0
1
•••
0
1
1
D0
0
1
0
•••
1
0
1
0
1
2
•••
253
254
255
Optical Black
Pixels
(Minimum Value
is 1)
(11)
D7
0
0
0
•••
1
1
1
D6
0
0
0
•••
1
1
1
D5
0
0
0
•••
1
1
1
D4
0
0
0
•••
1
1
1
D3
0
0
0
•••
1
1
1
D2
0
0
0
•••
1
1
1
D1
0
1
1
•••
0
1
1
D0
1
0
1
•••
1
0
1
1
2
3
•••
253
254
255
D12
D11
•••
•••
D2
D1
0
0
0
•••
1
1
1
0
0
0
•••
1
1
1
•••
•••
0
0
0
•••
1
1
1
0
0
1
•••
0
1
1
D0
(LSB)
0
1
0
•••
1
0
1
Active Pixels
Active Pixels
(Minimum Value
is 0)
(12, 13)
D13
(MSB)
0
0
0
•••
1
1
1
D12
D11
•••
•••
D2
D1
0
0
0
•••
1
1
1
0
0
0
•••
1
1
1
•••
1
1
1
•••
1
1
1
0
1
1
•••
0
1
1
D0
(LSB)
1
0
1
•••
1
0
1
End-of-Line Pixels
End of Line
Integration Pixels
(Minimum Value
is 5)
(14, 15)
D13
(MSB)
0
0
0
•••
1
1
1
Range 0, 67% (1:3)
Range 1, 50% (1:2)
Range 2, 33% (1:1.5)
Not Used
•••
22
0
1
2
•••
16381
16382
16383
5
6
7
•••
16381
16382
16383
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Table 2: Configuration Register Parameters (Continued)
Note: tMCLK = 1/fMCLK = 1 MCLK period. Examples given in parenthesis are for fMCLK = 24MHz (tMCLK = 41.66ns).
Parameter
(Address)
TR1
Pulse Duration
(16)
TR2
Pulse Duration
(17)
Control Bits
D5
(MSB)
0
0
0
•••
1
1
1
TR1/TR2 - Ø1
Guardband
(18)
D5
(MSB)
0
0
0
•••
1
1
1
Optical Black
Clamp Start
Position
(Must be Š
RS Pulse Width)
(19)
D4
(MSB)
0
0
0
•••
1
1
1
Optical Black
Clamp Stop
Position
(20)
D4
(MSB)
0
0
0
•••
1
1
1
Reset Pulse
Width
(Minimum Value
Is 1)
(21)
D7
(MSB)
0
0
0
1
1
1
1
Result
D4
D3
D2
D1
0
0
0
•••
1
1
1
0
0
0
•••
1
1
1
0
0
0
•••
1
1
1
0
0
1
•••
0
1
1
D4
D3
D2
D1
0
0
0
•••
1
1
1
0
0
0
•••
1
1
1
0
0
0
•••
1
1
1
0
0
1
•••
0
1
1
D3
D2
D1
0
0
0
•••
1
1
1
0
0
0
•••
1
1
1
0
0
1
•••
0
1
1
D0
(LSB)
0
1
0
•••
1
0
1
Clamp Start
(1/(2*fMCLK))
0
1
2
•••
29
30
31
D3
D2
D1
0
0
0
•••
1
1
1
0
0
0
•••
1
1
1
0
0
1
•••
0
1
1
D0
(LSB)
0
1
0
•••
1
0
1
Clamp Stop
(1/(2*fMCLK))
0
1
2
•••
29
30
31
D6
D5
(LSB)
1
0
1
0
1
0
1
0
1
1
0
0
1
1
D0
(LSB)
0
1
0
•••
1
0
1
= (x/2)tpixel, where
tpixel = 12tMCLK for
3 channel mode,
tpixel = 8tMCLK for 2
channel mode
(except for x = 0:
duration for x = 0 is
0.5tpixel, same as
for x = 1)
TR Pulse Width
D0
(LSB)
0
1
0
•••
1
0
1
= (x/2)tpixel, where
tpixel = 12tMCLK for
3 channel mode,
tpixel = 8tMCLK for 2
channel mode
(except for x = 0:
guardband for x = 0
is 0.5tpixel, same
as for x = 1)
TR Guardband
0.5 tpixel
0.5 tpixel
1.0 tpixel
•••
30.5 tpixel
31.0 tpixel
31.5 tpixel
0.5 tpixel
0.5 tpixel
1.0 tpixel
•••
30.5 tpixel
31.0 tpixel
31.5 tpixel
RS Pulse Width
(1/(2*fMCLK))
1
2
3
4
5
6
7
23
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Table 2: Configuration Register Parameters (Continued)
Note: tMCLK = 1/fMCLK = 1 MCLK period. Examples given in parenthesis are for fMCLK = 24MHz (tMCLK = 41.66ns).
Parameter
(Address)
Control Bits
D3
D2
D1
0
0
0
•••
1
1
1
0
0
0
•••
1
1
1
0
0
1
•••
0
1
1
D3
D2
D1
0
0
0
•••
1
1
1
0
0
0
•••
1
1
1
0
0
1
•••
0
1
1
D3
D2
D1
0
0
0
•••
1
1
1
0
0
0
•••
1
1
1
0
0
1
•••
0
1
1
Result
D0
(LSB)
0
1
0
•••
1
0
1
Reset Position
(1/(2*fMCLK))
0
1
2
•••
29
30
31
D0
(LSB)
0
1
0
•••
1
0
1
Reference Position
(1/(2*fMCLK))
0
1
2
•••
29
30
31
D0
(LSB)
0
1
0
•••
1
0
1
Signal Position
(1/(2*fMCLK))
0
1
2
•••
29
30
31
Reset Pulse
Position
(21)
D4
(MSB)
0
0
0
•••
1
1
1
Reference
Sample
Position
(22)
D4
(MSB)
0
0
0
•••
1
1
1
Signal
Sample
Position
(23)
D4
(MSB)
0
0
0
•••
1
1
1
Signal Polarity
(24)
D7
0
1
Preview Mode
(24)
D6
0
0
1
1
SYNC Pulse
(24)
D4
0
1
Externally Supplied (SYNC is Input)
Internally Generated (SYNC is Output)
TR Pulses
(24)
D3
0
1
1 TR Pulse (TR1)
2 TR Pulses (TR1 and TR2)
Red/Blue Order
for GRGB CCDs
(24)
D2
0
1
GR First
GB First
Sensor Type
(24)
D1
0
1
Dual Output (RG-BG)
Triple Output (R-G-B)
Negative, CDS On (CCD)
Positive, CDS Off (CIS)
D5
0
1
0
1
Normal Operation
Normal Operation
2x Speed
4x Speed
24
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Table 2: Configuration Register Parameters (Continued)
Note: tMCLK = 1/fMCLK = 1 MCLK period. Examples given in parenthesis are for fMCLK = 24MHz (tMCLK = 41.66ns).
Parameter
(Address)
Control Bits
Result
Sensor Type
(24)
D0
0
1
Standard
Even/Odd
Power Down
(25)
D7
0
1
Operating
Low Power Standby Mode
Coefficient Bus
Width
(25)
D6
0
1
TR2 Enable
(25)
D4
0
1
TR2 Enabled
TR2 Disabled
TR1 Enable
(25)
D3
0
1
TR1 Enabled
TR1 Disabled
RS Enable
(25)
D2
0
1
RS Enabled
RS Disabled
Ø2 Enable
(25)
D1
0
1
Ø2 Enabled
Ø2 Disabled
Ø1 Enable
(25)
D0
0
1
Ø1 Enabled
Ø1 Disabled
Gain Coefficient
Write Phase
(26)
D7
0
1
0°
180°
Offset Coefficient
Write Phase
(26)
D6
0
1
0°
180°
Data Read Phase
(26)
D5
0
1
0°
180°
Ø1 Polarity
During TR1
(26)
D4
0
1
High
Low
TR2 Pulse
Polarity
(26)
D3
0
1
High
Low
TR1 Pulse
Polarity
(26)
D2
0
1
High
Low
In 8 bit mode, coefficient data is 8 bits wide,
input through CD0-CD7.
25
10 bit
8 bit
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Table 2: Configuration Register Parameters (Continued)
Note: tMCLK = 1/fMCLK = 1 MCLK period. Examples given in parenthesis are for fMCLK = 24MHz (tMCLK = 41.66ns).
Parameter
(Address)
Control Bits
Result
RS Pulse Polarity
(26)
D1
0
1
High
Low
Ø1/Ø2 Polarity
(26)
D0
0
1
Ø1 High/Ø2 Low
Ø1 Low/ Ø2 High
Test Mode
(27)
TB7
0
0
1
TB6
0
1
1
Test Mode
(28)
0
0
Test Output Low
Test Output Is CDS Signal
Test Output is Clamp Signal
Set bits D0-D5 to 0
0
0
0
26
0
0
0
Set all bits to 0
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Applications Information
(Ø1) makes a low to high transition (period 4), the electrons from
the next pixel flow into C1. The charge across C1 now contains
the voltage proportional to the number of electrons plus VRESIDUAL, an error term. If OS is sampled at the end of period 3 and
that voltage is subtracted from the OS at the end of period 4, the
VRESIDUAL term is canceled and the noise on the signal is
reduced ([VSIGNAL+VRESIDUAL]-VRESIDUAL = VSIGNAL). This is the
principal of Correlated Double Sampling.
1.0 THEORY OF OPERATION
The LM9812 removes errors from and digitizes up to 3 channels
of linear sensor pixel streams, while providing all the necessary
clock signals to drive the sensor. Offset and gain errors are
removed at the pixel rate, for individual pixels. Offset errors are
removed through correlated double sampling (CDS), an analog
offset DAC for large DC offsets, and finally a pixel-rate digital offset subtractor for individual pixel offsets. Gain errors (which may
come from any combination of PRNU, uneven illumination, cos4
effect, RGB filter mismatch, etc.) are removed through the use of
a 5 bit PGA in front of the ADC (for coarse gain correction) and a
10x10bit pixel-rate digital multiplier for individual pixel gain errors.
The LM9812’s CDS circuit acquires a signal within a 1 MCLK window which can be placed anywhere in the pixel period with 0.5
MCLK precision. See Diagram 12 for more detailed timing information.
1.2 CIS Mode
The LM9812 provides some support for CIS (Contact Image Sensor) devices by offering a sampling mode for capturing positive
going signals, as opposed to the CCD’s negative going signal.
The output signal of a CIS sensor (Figure 2) differs from a CCD
signal in two primary ways: its output increases with increasing
signal strength, and it does not usually have a reference level as
an integral part of the output waveform of every pixel.
1.1 ANALOG SIGNAL PATH (See Functional Block Diagram)
1.1.1 Clamping and Buffering
The Output Signals (OS) from the image sensor are capacitively
coupled to the three (OSR, OSG, OSB) analog inputs of the
LM9812. Inside the LM9812, a DC restore operation is performed
by clamping the input signal to 2.5V when the input signal is
known to be black (during the start of a new line of image data).
To eliminate loading of the input signal, the signal is buffered
through a source follower before being sent to the CDS section.
OS (CIS)
1.1.2 CDS
The LM9812 uses a high performance CDS (Correlated Double
Sampling) circuit to remove many sources of noise and error from
the CCD signal. It also supports CIS image sensors with a single
sampling mode for positive-going signals.
OS (CCD)
1
Figure 1 shows the output stage of a typical CCD and the resulting output waveform:
VDD
Q1
C1
RS (RESET)
e-
2
3
4
5
Figure 2: CIS vs. CCD Output signals
When the LM9812 is in CIS mode (Register 24, bit 7=1), it uses
the VREF MID level as the reference (or black) voltage for each
pixel. Since the LM9812 clamps the input signal to VREF MID at
the black portion at the beginning of every line, the output of the
sampler is an accurate and repeatable representation of the that
pixel’s brightness.
Q2
OS
(from shift register)
1.2.1 Static PGAs
The output of the CDS stage drives the PGAs (Programmable
Gain Amplifiers). Each PGA provides 5 bits of fixed gain correction over a 0.93V/V to 3V/V (-0.6 to 9.5dB) range. The Blue channel has an optional x3 stage for a gain range of 2.8V/V to 9.0V/V
(8.9 to 19dB). The gain of each PGA should be set during calibration to bring the maximum amplitude of the strongest pixel to a
level just below the desired maximum output from the ADC. The
gain is determined by the following equation:
VSS
Ø1
RS
OS
1
2
3
4
5
PGA code
V
Gain  ---- = 0.93 + --------------------------- 2.137
32
V
Equation 1: PGA Gain
Figure 1: CDS
Capacitor C1 converts the electrons coming from the CCD’s shift
register to an analog voltage. The source follower output stage
(Q2) buffers this voltage before it leaves the CCD. Q1 resets the
voltage across capacitor C1 in between every pixel at intervals 2
and 5. When Q1 is on, the output signal (OS) is at its most positive voltage. After Q1 turns off (period 3), the OS level represents
the residual voltage across C1 (VRESIDUAL). VRESIDUAL includes
charge injection from Q1, thermal noise from the ON resistance
of Q1, and other sources of error. When the shift register clock
The Blue Channel has an additional gain stage with a gain of
3V/V that may be switched on to compensate for the low amplitude blue output of some sensors. With the x3 bit set (Register 2,
bit 7=1), the blue gain is:
PGA code
V
Gain  ---- = 02.79 + --------------------------- 6.411
32
V
Equation 2: Blue Channel PGA Gain with x3 Bit Set
27
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Gain Correction Coefficient
Multiplier Gain(V/V) = 1 + -----------------------------------------------------------------------N
Equation 5: Shading Multiplier Gain
plier gain range setting of 1:1.5 provides very accurate control of
the gain of each pixel. Systems with larger variation can use gain
ranges of 1:2 or 1:3.
This PGA is static - it does not change at the pixel rate. The PixelRate Shading Multiplier is used to eliminate pixel-to-pixel gain
errors (typically sensor PRNU and shading errors).
1.2.2 Static Offset DACs
The Static Offset DACs remove DC offsets generated by the sensor and the LM9812’s analog signal chain. The DACs should be
set during calibration to the lowest value that still results in an
ADC output code > 0 for all the pixels. Each LSB of the offset
DAC is typically 4.2 ADC LSBs, providing a total offset adjustment range of ±130 ADC LSBs. The equation for the offset DAC
is:
Offset ( ADC LSBs ) = 4.2 ( DAC Code )
Equation 3: Offset DAC
Like the PGA, the Offset DAC is static - it does not change at the
pixel rate. The Pixel Rate Offset Subtractor is used to eliminate
pixel-to-pixel offset errors.
Multiplier Gain Range
1:1.5
(33%)
1:2.0
(50%)
1:3.0
(67%)
Minimum Gain
(V/V, Multiplier Input = 0)
1
1
1
Maximum Gain
(V/V, Multiplier Input = 1024)
1.5
2.0
3.0
N (used in Equation 5)
2048
1024
512
Bits D3, D2 of Register 9
1, 0
0, 1
0,0
Table 1:Shading Multiplier: 10 bit Coefficient Bus Width
When the 8 bit Coefficient Bus Width is selected (Register 25, bit
6=1), the coefficient data is only 8 bits wide, supplied on CD0CD7. This reduces the accuracy of the gain correction, but allows
the use of an 8 bit path to store coefficient data, instead of a 10 or
16 bit wide path.
1.2.3 ADC
The 10 bit ADC quantizes the output from the analog chain and
passes the result to the digital section for pixel rate error correction. The ADC’s input range is equal to VREF IN/C, where C is the
gain constant compensating for all sources of gain error throughout the entire analog signal path.
Multiplier Gain Range
1:1.5
(33%)
1:2.0
(50%)
1:3.0
(67%)
Minimum Gain
(V/V, Multiplier Input = 0)
1
1
1
Maximum Gain
(V/V, Multiplier Input = 256)
1.5
2.0
3.0
1.3 DIGITAL SIGNAL PATH
1.3.1 Pixel-Rate Offset Subtractor
The output of the ADC is fed to the Pixel-Rate Offset Subtractor.
Each pixel of image data may have a different offset error. If bit 0
of Register 9 is set to a 0 and a byte representing the offset error
code is fed to the Pixel-Rate Offset Subtractor through the CD0CD9 databus, the offset for each pixel can be subtracted from the
ADC output code at the pixel conversion rate. If this feature is not
desired, the Offset Subtractor can be set to a fixed value by writing the desired value to Register 6 and setting bit 0 of Register 9
to a 1.
N (used in Equation 5)
512
256
128
Bits D3, D2 of Register 9
1, 0
0, 1
0,0
Table 2:Shading Multiplier: 8 bit Coefficient Bus Width
1.4 SENSOR CLOCK GENERATION
Offset Subtractor Out = ADC Output – Offset Error Code
Equation 4: Offset Subtractor
The offset subtractor input is 8 bits wide, input on CD0-CD7, for a
correction range of 0 to 255. Information on bits CD8 and CD9 is
ignored.
The LM9812 generates all of the clock signals required to directly
drive most commercial linear CCDs and some CIS - no external
clock buffers are necessary. Most linear CCDs designed for scanner applications require 0 to 5V signal swings into 20 to 500pF
input loading. Series resistors are typically inserted between the
driver and the CCD to control slew rate and isolate the driver from
the large load capacitances. The values of these resistors are
given in the CCD’s datasheet.
1.3.2 Pixel-Rate Shading Multiplier
The Pixel Rate Shading Multiplier follows the Offset Subtractor.
This stage compensates for nonuniformities between individual
pixels (shading error). Each pixel of image data may have a different gain error. If bit 1 of Register 9 is set to a 0 and a word representing the gain correction coefficient is fed to the Pixel-Rate
Shading Multiplier through the CD0-CD9 databus, the gain for
each pixel is changed at the pixel rate to eliminate pixel-to-pixel
gain errors. If this feature is not desired, the Shading Multiplier
can be set to a fixed value by writing the desired gain value to
Registers 7 and 8 and setting bit 1 of Register 9 to a 1.
1.4.1 TR1 and TR2
The LM9812 supports one or two TR (transfer, or shift) pulses as
shown in Diagrams 8 and 9. This pulse is used to transfer the
contents of each pixel’s photodiode to the CCD’s serial shift register for clocking out of the CCD. Configuration Registers 16, 17,
and 18 control the TR1, TR2, and TR guardband pulse widths,
while Register 24, bit 3 determines whether the LM9812 generates TR1 only or both TR1 and TR2 at the beginning of a line.
The polarities of the TR pulses are determined by Register 26,
bits 2 and 3. If not needed, one or both TR pulses can be disabled by setting Register 25, bits 3 and 4 to the appropriate value.
The equation for calculating the gain of the multiplier is given in
Equation 5. The Pixel Rate Shading Multiplier has three different
gain ranges as shown in Table 1. For systems where the ratio of
the strongest pixel to the weakest pixel is less than 1.5, the multi-
28
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1.4.2 RS
for tDATAVALID. The D0-D9 databus comes out of tri-state when
SYNC is high and RD PIXEL is low. If SYNC is low, RD PIXEL will
have no effect.
The LM9812 also generates the RS (reset) pulse required to
clear the CCD’s output capacitor of the previous pixel’s charge.
The RS pulse’s width and position (relative to the edge of the ø1
pulse) is determined by the value in Configuration Register 21.
See Diagrams 10 and 12. The polarity of the RS pulse is determined by Register 26, bit 1. If not needed, this pulse can be disabled by setting Register 25, bit 2 to a 1.
When reading pixel data, RD PIXEL may be driven by EOC, putting the data on the bus only when EOC is low, and allowing other
data on the bus (such as CD0-CD9 correction data) at other
times. In this way the output data and correction coefficient data
can share the same databus (See Diagrams 16, 17, 20, and 21).
1.4.3 ø1 and ø2
1.5.3 Correction Coefficient Data I/O
ø1 and ø2 are the two phase clock for the CCD shift register. ø2
is always the inverse of ø1. For “standard” CCDs, the ø1 and ø2
frequency is equal to the pixel rate, the same frequency as the
RS pulse. In Standard Mode, the RS pulse position and Sample
Reference/Sample Signal edges are set with respect to the falling
edge of ø1. For “even/odd” CCDs, the ø1 and ø2 frequency is
equal to one half the pixel rate, a pixels is sampled after both the
rising and falling edges of the ø clock. In Even/Odd Mode, the RS
pulse position and Sample Reference/Sample Signal edges are
set with respect to the either edge of ø1. Standard or Even/Odd
mode is selected by setting bit 0 of Register 24. The absolute
polarity of the ø pulses is determined by Register 26, bits 0 and 4
(both bits perform the same function). If not needed, one or both
ø pulses can be disabled by setting Register 25, bits 0 and 1 to
the appropriate value.
Coefficient data for the pixel rate Offset Subtractor and Shading
Multiplier enters the LM9812 through the CD0-CD9 databus. To
maximize flexibility for the system designer, there are several
clocking options available in this mode: separate or combined
buses for the CD0-CD9 and the D0-D9 data, one (GLCK) or two
(GLCK and OCLK) clock signals to latch the Correction Coefficient data, and the option to have the LM9812 generate the clock
signals or have them supplied to the LM9812. Timing for these
different options is shown in Diagrams 14 through 21, and
described below.
1.5 DIGITAL INTERFACE
There are three main sections to the digital interface of the
LM9812: the Configuration Register interface (through which all
device programming is done), the Correction Coefficient Data
interface (the 10 bit-wide input databus for gain and offset correction coefficients), and the 10 bit-wide Pixel Data output databus
(where the corrected digital output data appears).
CD0-CD9 tied to
D0-D9
(1 bus)
CD0-CD9
separate from
D0-D9
(2 bus)
GLCK, OCLK are
outputs (2 Clock)
Diagram 16
Diagram 14
GLCK is output
(1 Clock)
Diagram 17
Diagram 15
Diagrams 20, 21
Diagrams 18, 19
GLCK, OCLK are
inputs
Table 3:Correction Databus Options
1.5.1 Configuration Register I/O
The Configuration Register is written to and read from through
the D0-D9 databus, using the CS, WR, and RD signals. To write
to the Configuration Register, follow the timing shown in Diagram
24. The first byte is the address of the Configuration Register to
be written to, the second byte is the data to be stored at that
address. Configuration Register writes can occur at any time,
independent of the state of the SYNC pin.
Diagram 14 shows the case where the correction data (CD0CD9) is on a separate bus from the output data (D0-D9) (Register
9, bit 4=0). The GLCK and OCLK signals are generated by the
LM9812 (Register 9, bit 5=0, bit 7=1). Gain correction data is
latched on the rising edge of GCLK, and offset correction data is
latched on the rising edge of OCLK. There is a one EOC clock
latency between the latching of the gain coefficient for a particular
pixel and the output of that pixel on the D0-D9 databus.
To read from the Configuration Register, follow the timing shown
in Diagram 25. The first byte is the address of the Configuration
Register to be written to, the second byte is the data stored at that
address. The SYNC pin must be low in order to read from the
Configuration Register. To ensure that SYNC is low when in the
SYNC out mode, RUN/STOP must be low until the end of the
active pixels.
Diagram 15 shows the case where the correction data (CD0CD9) is on a separate bus from the output data (D0-D9) (Register
9, bit 4=0). The LM9812 generates the GCLK signal only (Register 9, bit 5=1, bit 7=1). Gain correction data is latched on the rising edge of GCLK, and offset correction data is latched on the
falling edge of GCLK. There is a one EOC clock latency between
the latching of the gain coefficient for a particular pixel and the
output of that pixel on the D0-D9 databus.
If the LM9812’s RD pin is taken low, even if the CS pin is high, the
D0-D9 databus will be driven. Never take the RD pin low unless
you are actually doing a Configuration Register read.
Diagram 16 shows the case where the correction data (CD0CD9) is on the same bus as the output data (D0-D9) (Register 9,
bit 4=1). The GLCK and OCLK signals are generated by the
LM9812 (Register 9, bit 5=0, bit 7=1). Gain correction data is
latched on the rising edge of GCLK, and offset correction data is
latched on the rising edge of OCLK. Using the EOC output to
control the RD PIXEL input allows the CD0-CD9 and the D0-D9
data to exist on the same bus with no contention. There is a one
1.5.2 Pixel Data I/O
The output of the multiplier is available on the D0-D9 databus. If
the Data Read Phase bit (bit 5 of Register 26) is set to a 0, Data
changes shortly before the falling edge of EOC and remains valid
for tDATAVALID. If the Data Read Phase bit is set to a 1, Data
changes shortly before the rising edge of EOC and remains valid
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To operate the LM9812 with an externally supplied OCLK and
GCLK, set bit D7 of register 9 to a 0 and set the phase bit for
each clock. The procedure to determine the state of the phase bit
is described at the end of this section.
EOC clock latency between the latching of the gain coefficient for
a particular pixel and the output of that pixel on the D0-D9 databus.
Diagram 17 shows the case where the correction data (CD0CD9) is on the same bus as the output data (D0-D9) (Register 9,
bit 4=1). The LM9812 generates the GCLK signal only (Register
9, bit 5=1, bit 7=1). Gain correction data is latched on the rising
edge of GCLK, and offset correction data is latched on the falling
edge of GCLK. Using the EOC output to control the RD PIXEL
input allows the CD0-CD9 and the D0-D9 data to exist on the
same bus with no contention. There is a one EOC clock latency
between the latching of the gain coefficient for a particular pixel
and the output of that pixel on the D0-D9 databus.
DIagrams 18 through 21 show the timing required when GCLK
and OCLK are configured as inputs to the LM9812 (Register 9, bit
5=0, bit 7=0). This option exists to allow the LM9812 to work with
ASICs designed for earlier systems, where the ASIC generates
the SRAM timing (instead of the LM9812). Diagrams 18 and 19
show the 2 bus mode (Register 9, bit 4=0), diagrams 20 and 21
show the 1 bus mode (Register 9, bit 4=1).
In these modes, GLCK and OCLK come from an external source
that may be asynchronous to the internally generated OCLK and
GCLK. While these clocks may be asynchronous, they will be the
same frequency, the ADC conversion rate (since offset and gain
coefficients are needed for every pixel, and the pixel data rate is
fixed by the ADC conversion rate).
In the previous modes of operation, the offset correction clock
(OCLK) and the gain (shading) correction clock (GCLK) are generated by the LM9812 and used to generate the RD pulses to
coefficient RAM. These clocks can also be configured as inputs
to allow compatibility with some existing ASICs or designs where
it is preferred to let the ASIC generate all the timing. The offset
data is always latched on the rising edge of OCLK. The gain data
is always latched on the rising edge of GCLK.
The circuit shown in Figure 3 is implemented inside the LM9812
to synchronize (by delaying) the external coefficient clocks and
CD0-9 data with the internal LM9812 clocks.
Internal OLCK
phase = 0°
D
Q
FF1O
Q
D
Q
FF2O
Q
3:1
Mux
Latched
Offset
Correction
Data to
Offset Subtractor
D
Q
FF3O
Q
phase = 180°
Ext OCLK
Internal GLCK
phase = 0°
CD0-9
D
Q
FF1G
Q
D
Q
FF2G
Q
phase = 180°
3:1
Mux
D
Q
FF3G
Q
Latched
Gain
Correction
Data to
Multiplier
Ext GCLK
EOC
Figure 3: Using An External OCLK and GCLK
clock and EOC (the LM9812’s internal coefficient clock) is known,
then by selecting Q1 or Q2 as the input to FF3, the designer can
guarantee that the data will be valid on the rising edge of
GCLKINT, where it is latched into FF3 and synchronized to the
LM9812.
CD0-9 data is always latched into register FF1 on the rising edge
of the external clock. The output of FF1 is then latched by FF2 on
the falling edge of the external clock. So the latched data is available at the output of FF1 between the rising edges of the external
clock, and is valid at the output of FF2 between the falling edges
of the external clock. If the phase difference between the external
GCLKINT is not externally available to the user but it is basically
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CCD sensors (this mode will not work for CIS sensors). In these
modes, adjacent pixels are averaged together in the analog
domain and converted at the maximum ADC conversion rate.
This allows the CCD data to be clocked out and digitized 2 or 4
times faster (corresponding to a 2 to 4 times faster image scan).
The image will be 1/2 or 1/4 the resolution. For example, a 600dpi
sensor will look like a 300dpi sensor in the x2 preview mode, or a
150dpi sensor in the x4 preview mode. This is useful because it
allows faster scans for lower resolution images and scan preview
images. The quality of the lower resolution image is also significantly improved because this technique averages pixels to
reduce the resolution instead of discarding pixels (which often
results in a loss of image information).
the inverse of EOC, plus or minus a few ns of gate delay. To use
an external GLCK and OCLK, determine the phase of the external OCLK and GLCK with respect to EOC. Then look at Diagrams
18 and 19 (2 bus mode) or 20 and 21 (1 bus mode). Choose a
phase setting (0° or 180°, register 26 bits 6 and 7) for OCLK and
GCLK that provides the most margin with respect to the tOCLKEOC1 (OCLK IN), tOCLK-EOC2 (OCLK IN), and tGCLK-EOC (GCLK IN)
specifications.
It is entirely possible that either setting (0° or 180°) will work
equally well. The condition that must be avoided is when FF3 is
clocked (falling edge of EOC) at the same time the input data to
FF3 is changing (rising edge of OCLK/GCLK for 0° phase, or falling edge of OCLK/GCLK for 180° phase). As long as this does
not occur simultaneously, the data will be correctly latched.
Ø1
3
(Even/Odd Mode)
Note that the coefficient data must appear sooner (relative to the
pixel output data) for the Clock In modes, to account for the extra
latency through FF1 and FF2. This additional time is shown in
Diagrams 18 through 21.
9
Ø2
(Even/Odd Mode)
Ø1
(Standard Mode)
This mode of operation may seem confusing at first, but it is necessary to allow the synchronous LM9812 to phase lock to external coefficient data of unknown phase.
6
1.5 1.5
3
6
Ø2
(Standard Mode)
All lengths given in units of MCLK periods
RS
1.5.4 MCLK
This is the master clock input for the LM9812. The ADC conversion rate is fixed at 1/4 of this frequency. The pixel rate in 3 channel mode is 1/12 of the MCLK frequency. Many of the timing
parameters are also relative to the frequency of this clock.
OS
pn
pn+1
CDS
(Internal)
1.5.5 SYNC
Hold Ref
Hold Signal
Diagram 4: x2 Preview Mode Timing
This input signals the beginning of a line. When SYNC goes high,
the LM9812 generates a TR pulse, then begins converting pixels
until the SYNC line is brought low again. If SYNC is externally
applied, the LM9812 will work with sensors with any number of
pixels. If SYNC is internally generated (in combination with the
RUN/STOP input), sensors with up to 3 channels of 16383 pixels/channel can be used.
In the x2 preview mode, the Ø clock is clocked at 2 times the normal Ø clock frequency, while the RS pulse stays at the ADC’s
conversion rate. By skipping every other RS pulse, the charge for
pixel n+1 will be added to the charge for pixel n on the CCD itself.
Since the CCD is being clocked at 2 times the normal rate, the
period between lines (and therefore the integration time) will be
half as long, causing the amplitude of each pixel to be half as
large. Since the output of the CCD is the sum of two pixels, the
final amplitude seen by the LM9812 is very similar to what it is in
normal mode. The final pixel amplitude will be equal to (pn/2 +
pn+1/2) = (pn + pn+1)/2 = the average of pn and pn+1.
1.5.6 RUN/STOP
The LM9812 has a “SYNC OUT” mode (Register 24, bit 4=1) that
automatically generates a SYNC pulse stream based on the number of active pixels and the number of additional end-of-line integration pixels programmed into registers 12-15. When the
RUN/STOP pin is brought high, the LM9812 begins generating
the periodic SYNC pulse. When RUN/STOP goes low, the
LM9812 will continue converting the remaining active pixels, then
SYNC will go low and the part will “idle” until the next rising edge
of RUN/STOP.
The same principle applies in the x4 preview mode. Here the Ø
clock is clocked at 4 times the normal Ø clock frequency, while
the RS pulse stays at the ADC’s conversion rate. By skipping 3
out of 4 RS pulses, the charge for pixels n, n+1, n+2, and n+3 will
be averaged in the CCD’s output stage. Since the CCD is being
clocked at 4 times the normal rate, the period between lines (and
therefore the integration time) will be one quarter as long. The
final pixel amplitude will be equal to (pn + pn+1+ pn+2+ pn+3)/4 =
the average of pn, pn+1, pn+2, and pn+3.
Using the SYNC OUT mode provides a simple way to clock the
sensor continuously with a repeatable, user-programmed integration period. By varying the number of end-of-line integration pixels (in registers 14 and 15), the integration time (and thus the
amplitude of the output signal from the sensor) can be adjusted
with very high accuracy (about 1 part in 5400, or 0.02%, for a
600dpi sensor).
Getting the optimum performance out of the preview modes with
a particular CCD may require adjusting the RS pulse width, RS
pulse position, Sample Reference, and Sample Signal timing
(Registers 21, 22, and 23).
2.0 PREVIEW MODE OPERATION
The LM9812 supports two “preview” or low resolution modes for
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Ø1
1.5 1.5 1.5
7.5
(Even/Odd Mode)
drives a transconductance amplifier with two output currents, VREF IN/2 and +VREF IN/2. These currents go into the VREF HI and
VREF LO reference voltage buffers, which generate a nominal
3.45V (VREF HI = VREF MID + VREF IN/2), and 1.45V (VREF LO =
VREF MID - VREF IN/2). To minimize noise, the reference amplifiers
sense (IN) inputs are brought out to the chip for bypassing. Each
buffer’s output and input should be tied together and decoupled to
AGND through a 0.1µF monolithic capacitor.
7.5
Ø2
(Even/Odd Mode)
0.5
Ø1
6
(Standard Mode)
1
1
1
1.5
6
Ø2
(Standard Mode)
3.2 Clamp Capacitor Selection
All lengths given in units of MCLK periods
This section is very long because it is relatively complicated to
explain, but the answer is short and simple: A clamp capacitor
value of 0.01µF should work in almost all applications. The rest of
this section describes exactly how this value is selected.
RS
pn
OS
pn+1
pn+2
pn+3
CCLAMP
CDS
(Internal)
Hold Ref
OS
SENSOR
Hold Signal
Diagram 5: x4 Preview Mode Timing
DOS
OS
NC
2.450V
3.0 ANALOG INTERFACE
LM9812
3.1 Voltage Reference
The VREF IN pin should be connected to a 2V±5% reference voltage. The LM4041-ADJ adjustable bandgap reference is recommended for this application, as shown in Figure 6. The
inexpensive “D” grade meets all the requirements of the application and is available in a TO-92 (LM4041DIZ-ADJ) package as
well as a SOT-23 package (LM4041DIM3-ADJ) to minimize board
space. To reduce noise, the VREF IN pin should be bypassed to
Figure 7: OS Clamp Capacitor and Internal Clamp
The output signal of many sensors rides on a DC offset (greater
than 5V for many CCDs) which is incompatible with the LM9812’s
5V operation. To eliminate this offset without resorting to additional higher voltage components, the output of the sensor is AC
coupled to the LM9812 through a DC blocking capacitor, CCLAMP
(the CCD’s DOS output, if available, is not used). The value of
this capacitor is determined by the leakage current of the
LM9812’s OS input and the output impedance of the sensor. The
leakage through the OS input determines how quickly the capacitor value will drift from the clamp value of VREF MID, which then
determines how many pixels can be processed before the droop
causes errors in the conversion (±0.1V is the recommended
limit). The output impedance of the sensor determines how
quickly the capacitor can be charged to the clamp value during
the black reference period at the beginning of every line.
Reference
Amplifiers
VREF HI OUT
VA
VREF HI IN
R
10.5k
0.1µF
VREF MID OUT
10.1k
VREF MID IN
The minimum clamp capacitor value is determined by the maximum droop the LM9812 can tolerate while converting one sensor
line. The following equation takes the maximum leakage current
into the OS input, the maximum allowable droop (100mV), the
number of pixels on the sensor, and the pixel conversion rate
(fMCLK/12 for triple output sensors or fMCLK/8 for dual output sensors) and provides the minimum clamp capacitor value:
0.1µF
VREF LO OUT
VREF LO IN
R
-I
+I
I=VREF IN/2R
0.1µF
VA
VREF IN
0.1µF
3k
i
C CLAMP MIN = --------- dt
dV
leakage current (A) number of pixels
= --------------------------------------------------- -----------------------------------------------------max droop(V) conversion rate (Hz)
Equation 6: CCLAMP MIN Calculation
4.7k
LM9812
LM4041-ADJ
3k
For example, if the OS input leakage current is 20nA worst-case,
the sensor has 2700 active pixels, the conversion rate is 2MHz
(fMCLK = 24MHz, triple output sensor), and the max droop desired
is 0.1V, the minimum clamp capacitor value is:
20nA 2700
C CLAMP MIN = -------------- --------------0.1V 2MHz
= 270pF
Equation 7: CCLAMP MIN Example
Figure 6: Voltage Reference Generation
AGND with a 0.1µF monolithic capacitor.
The LM9812 generates three internal reference voltages for its
analog front end: VREF MID, VREF HI, and VREF LO. VREF MID is
equal to 0.49*VA, or 2.45V with a nominal 5V supply. VREF IN
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The maximum size of the clamp capacitor is determined by the
amount of time available to charge it to the desired value during
the optical black portion of the sensor output. The internal clamp
is on for each pixel for the time specified in Registers 19 and 20
(see Diagram 11). This time can be calculated using this equation:
Start-Stop
t
(s) = ----------------------------------DARK
2f
(Hz)
MCLK
Equation 8: tDARK Calculation
In this example a 0.01µF capacitor takes 14ms after power-up to
charge to its final value, but its droop across all subsequent lines
is now less than 3mV (using the previous example’s values). This
wide margin is the reason a CCLAMP value of 0.01µF will work in
most applications.
4.0 CALIBRATION
System calibration is required to correct the many sources of
error in a scanner and optimize image quality. There are many different ways to calibrate a system, some take a long time but produce better results, others are faster with potentially lower quality
images. The method described below should produce very good
results, but it is by no means the only way to approach scanner
calibration. Some calibration steps could be eliminated to speed
up the calibration procedure. Other steps could be improved by
iteratively repeating them, verifying that the previous calculation
achieved the desired result. Every scanner system is different, so
every system may benefit from optimization of the calibration routine.
Where Start is the Optical Black Clamp Start Position (Register
19), Stop is the Optical Black Clamp Stop Position (Register 20),
fMCLK is the MCLK frequency, and tDARK is the amount of time
(per pixel) that the clamp is on.
The following equation takes the number of optical black pixels,
the amount of time (per pixel) that the clamp is closed, the sensor’s output impedance, and the desired accuracy of the final
clamp voltage and provides the maximum clamp capacitor value
that allows the clamp capacitor to settle to the desired accuracy
within a single line:
t
1
C CLAMP MAX = ------ -------------------------------R ln(accuracy)
t
(s)
n
DARK
= ------------------ -------------------------------R OUT ln(accuracy)
Equation 9: CCLAMP MAX Calculation
4.0.1 LM9812 Configuration Sequence After Power-On
The power-on reset circuit of the LM9812 may take several hundred microseconds. Wait 1ms after power-on before writing to the
Configuration Registers.
Where n = the number of optical black pixels, tDARK is the amount
of time (per pixel) that the clamp is on, ROUT is the output impedance of the CCD, and accuracy is the ratio of the worst-case initial capacitor voltage to the desired final capacitor voltage. For
example, if a sensor has 18 black reference pixels, the output
impedance of the sensor is 1500Ω, the LM9812 is configured to
clamp for 375ns, the worst case initial voltage across the capacitor is 10V, and the desired voltage after clamping is 0.1V (accuracy = 10/0.1 = 100), then:
18 375ns
C CLAMP MAX = ------------- -----------------1500 ln(100)
= 977pF
Equation 10: CCLAMP MAX Example
The final value for CCLAMP should be less than or equal to
CCLAMP MAX, but no less than CCLAMP MIN. A value of 470pF will
work in this example.
Make sure the SYNC and RUN/STOP inputs are low before writing to the Configuration Registers. When SYNC is high, you can
not read the configuration register (but you can still write to it).
The LM9812 configuration sequence:
• Set bit 2 of Test Register 28 to 0 (to allow writing of
configuration data). This register is reset to 0 by the power-on
reset, but this step is still recommended to ensure that writes
will work even if this register was corrupted.
• Program bit 4 of register 24 to determine if the LM9812 will be
used in the SYNC OUT or SYNC IN mode.
• Cycle the Powerdown bit to reset the LM9812’s state
machines. (Take bit 7 of register 25 to a 1, then back to a 0).
This procedure will completely reset the part. At this time the
LM9812 is ready for data to be written to all 28 configuration registers. Data can also be read back from all 28 registers if write
confirmation is desired.
In some cases, depending primarily on the choice of sensor,
CCLAMP MAX may actually be less than CCLAMP MIN, meaning that
the capacitor can not be charged to its final voltage during the
black pixels at the beginning of a line and hold it’s voltage without
drooping for the duration of that line. This is usually not a problem
because in most applications the sensor is clocked continuously
as soon as power is applied. In this case, a larger capacitor can
be used (guaranteeing that the CCLAMP MIN requirement is met),
and the final clamp voltage is forced across the capacitor over
multiple lines. This equation calculates how many lines are
required before the capacitor settles to the desired accuracy:
 R OUT C CLAMP
Initial Voltage
lines =  ----------------- ------------------------- ln  -------------------------------------
t DARK   Final Voltage 
 n
Equation 11: Line Settling Formula
After all 28 configuration registers have been programmed, scanning can begin by taking SYNC high (in the SYNC IN mode) or
RUN/STOP high (in the SYNC OUT mode).
4.1 Calibration Initialization
• Set the Offset DACs to their maximum positive value (Offset
DAC registers 0, 1, and 2 =31)
• Set the PGA gains to 1V/V (PGA gain registers 3, 4, and 5 =1)
• Set the Pixel Rate Offset Adder Source to internal (register 9,
bit 0=1)
• Set the Pixel Rate Multiplier Source to internal (register 9, bit
1=1)
• Set the Internal Pixel Rate Offset Adder value to 0 (register
6=0)
• Set the Internal Pixel Rate Multiplier value for a gain of 1
(registers 7 and 8 = 0)
Using the values shown before and a clamp capacitor value of
0.01µF, this works out to be:
1500 0.01µF
10V
lines =  ------------- ------------------ ln  ------------ = 10.2 lines
18 375ns
0.1V
Equation 12: Line Settling Example
At a 2MHz conversion rate, this is about 14ms.
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• Set the Multiplier Gain Range to 1:3 (register 9, bits 2 and 3 =
00)
Target Code
WhiteMAX
ADC
Output
Code
4.2 Setting the Static Offset DACs
018
014
ADC 010
Output 00C
Code 008
004
000
BlackMIN
Data Pixels
Figure 10: Finding WhiteMAX
gain too high
Target Code
Data Pixels
gain correct
Figure 8: Finding BlackMIN
gain too low
• Scan one line of a pure black test pattern, or scan one line with
the light source turned off. (Caution: turning the light source on
and off may cause thermal drift in light intensity as the light
source warms up and cools down.) Scanning multiple black
lines and averaging each pixel from each line will reduce noise
and increase the accuracy of this step.
• Find the minimum pixel value of the scanned black image
(BlackMIN) for each color (Figure 8).
• Reduce the Offset DAC value for each color so that the
minimum black pixel is close to 0, but still greater than 0
(Figure 9). One offset DAC code = ~4.2 ADC LSBs, so change
the DAC code to (31 - BlackMIN/4.2).
018
014
ADC 010
Output 00C
Code 008
004
000
ADC
Output
Code
Data Pixels
Figure 11: CCD Input Signal In Range
gain equation (Equation 1), the PGA code required is:
Target Code
32
PGA code = Integer   --------------------------------- – 0.94 ---------------
  White
 2.137
MAX
Equation 13: PGA Code Calculation
If the Blue channel requires a gain greater than 3 (Target
Code/WhiteMAX is >3), then set register 2, bit 7=1 and use
Equation 14:
BlackMIN = 13:
too high
32
Target Code
PGA code = Integer   --------------------------------- – 2.82 ---------------
6.411
White MAX
Equation 14: Blue PGA Code Calculation, x3 Bit Set
• Program the calculated PGA values for each color into
configuration registers 3, 4, and 5.
• Because the above equations are based on typical LM9812
performance, the new PGA settings should be verified. Scan
another white line(s) with the new PGA values and recalculate
WhiteMAX and WhiteMIN (the minimum ADC output code for the
white image) for each color. Verify that WhiteMAX is near but
still below the Target Code. If WhiteMAX is greater than or
equal to the target code, decrement that PGA value by 1.
•
BlackMIN = 6:
correct
Data Pixels
BlackMIN = 0:
too low
Figure 9: Setting the Static Offset DACs
• Because the above equation is based on typical LM9812
performance, the new DAC settings should be verified. Scan
another black line(s) with the new DAC values and verify that
all the pixels are still above 0. If any pixels are equal to 0,
increment the DAC value by 1. If the minimum pixel is above 8,
consider decrementing the DAC value by 1. Repeat this step
until the minimum pixel value of the scanned black image
(BlackMIN) for each color is greater than 0 but less than 9.
BlackMIN values greater than 9 are acceptable (they will be
removed by the Pixel Rate Offset Subtractor), but will reduce
the dynamic range of the system.
4.4 Determining the Multiplier Correction Range Setting
• For best performance, repeat Steps 4.2 and 4.3 before
proceeding. This will maximize the available dynamic range of
the ADC and ensure that all the pixels are in range.
• Digitize another white line (or multiple lines) and calculate the
minimum and maximum pixels from that line (WhiteMIN and
WhiteMAX). Verify that WhiteMAX is less than the Target Code.
4.3 Setting the Static PGAs
• Decide on the Target Code for your scanner. This is the
maximum output code from the ADC for a pure white image.
This code may be as large as 1023, but this value could cause
clipping if the light source drifts and becomes brighter after
calibration. A value of 1000 allows for moderate light source
drift between calibration and image scan.
• Scan one line of a pure white test pattern. Scanning multiple
white lines and averaging each pixel from each line will reduce
noise and increase the accuracy of this step.
• Find the maximum white pixel value of the image data
(WhiteMAX) for each color (Figure 10).
• Program the PGA value for each color so that the maximum
white pixel is close to, but still less than the Target Code
(Figure 11). The PGA gain required to meet this condition is
equal to the Target Code divided by WhiteMAX. Using the PGA
Target Code
WhiteMAX
WhiteMIN
ADC
Output
Code
Data Pixels
Figure 12: Determining Correction Range Setting
• The correction range required (Range) = WhiteMAX/WhiteMIN
• If Range < 1.5, then set the Multiplier Range bits (register 9,
bits 3 and 2) to 10 (33%).
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• If 1.5 < Range < 2.0, then set the Multiplier Range bits (register
9, bits 3 and 2) to 01 (50%).
• If 2.0 < Range < 3.0, then set the Multiplier Range bits (register
9, bits 3 and 2) to 00 (66%).
• If Range > 3.0, then set the range is too large and the system
can not be calibrated.
channel of the LM9812. The constant C (typically 2, given in the
Electrical Characteristics table) represents the total gain error
from Vin through DOUT with G = 1V/V (PGA register setting = 1).
To further simplify the model, the signal is always assumed to be
0V for black and increasing in the positive direction as pixel
brightness increases. In reality, black may be offset from ground,
and white may be negative (CCD) or positive (CIS) with respect to
black, but this is all taken care of by the CDS function and the correct setting of the Signal Polarity bit (Register 24, bit 7).
4.5 Calculating the Pixel Rate Offset Coefficients
• Scan one line of a pure black test pattern, or scan one line with
the light source turned off. (Caution: turning the light source on
and off may cause thermal drift in light intensity as the light
source warms up and cools down.) Scanning multiple black
lines and averaging each pixel from each line will reduce noise
and increase the accuracy of this step.
• The value of each pixel is the offset error for that pixel. Store
each pixel value into that pixel's offset correction RAM
location.
• Set the Pixel Rate Offset Adder Source to external (register 9,
bit 0 = 0)
VREF IN
C
VIN
+
Σ
+
VOS1
10 Bit
ADC
+
Σ +Σ
+
+
VOS2
VOD
G
DOUT
Offset
DAC
Figure 13: Simplified Model of One Channel of the Analog Front End
The analog front end’s transfer function is shown in Equation 18.
4.6 Calculating the Pixel Rate Multiplier Coefficients
• Scan one line of a pure white test pattern. Scanning multiple
white lines and averaging each pixel from each line will reduce
noise and increase the accuracy of this step.
• The equation for the multiplier gain is:
D
(V + V
)G + V
+V
OS 2
OD
IN
OS 1
= 1024 C ---------------------------------------------------------------------------------------V
REFIN
Equation 18: AFE Transfer Equation
OUT
The typical values of C (2) and VREFIN (2V) cancel each other
out. It is also useful to convert all the voltages to ADC codes,
since that is the domain in which they will be seen by the calibration software. VIN (in ADC codes) = VIN (in V)*1024. Calibration
can be more easily accomplished using the simplified model of
Equation 19.
x
Multiplier Gain = 1 + ---N
Equation 15: Multiplier Gain Equation
where:
x is the 10 bit multiplier gain coefficient (0 to 1023),
N = 2048 (Multiplier range = 1:1.5),
N = 1024 (Multiplier range = 1:2),
N = 512 (Multiplier range = 1:3).
• Determine the multiplier gain for each pixel n so the result is
the Target Code:
D
OUT
= (V
IN
+V
OS 1
)G + V
OS 2
+V
OD
Equation 19: AFE Transfer Equation (units of ADC LSBs)
Measurement of the two offset voltages (VOS1 and VOS2) is done
by measuring the ADC output, with a black image on the sensor
(if a black reference image is not available, it may be created simply by turning off the scanner’s illumination). In this example, VIN
is considered to be 0V, and any offsets from the sensor are
lumped in with the LM9812’s VOS1. If the ADC output is measured
with a PGA gain of 1V/V and 3V/V, then the offset errors (VOS1
and VOS2) can be determined from the following two equations:
Target Code
Gain(n) = --------------------------------pixel datan
Equation 16: Gain Calculation for Each Pixel
• The multiplier coefficient required is therefore:
Multiplier Coefficent (n) = Integer(N(Gain(n) - 1))
Target Code
= Integer  N  --------------------------------- – 1 
pixel datan
Equation 17: Multiplier Coefficient Calculation for Each Pixel
VADC1 = 1VOS1 + VOS2 + VDAC2 (PGA gain = 1V/V)
VADC2 = 3VOS1 + VOS2 + VDAC2 (PGA gain = 3V/V)
• Store the Multiplier Gain Coefficients for each pixel into that
pixel's offset correction RAM location.
• Set the Pixel Rate Multiplier Source to external (register 9, bit
1=0)
Solving for VOS1 and VOS2:
VOS1 = (VADC2 - VADC1)/2
VOS2 = (3VADC1 - VADC2)/2
CALIBRATION COMPLETE
5.0 POWER SUPPLY CONSIDERATIONS
4.7 Additional Calibration Information
5.1 General
The procedure detailed in sections 4.1 through 4.6 is only one of
many approaches to scanner calibration. In some approaches it
may be useful to use a model for the analog front end and actually measure VOS1 and VOS2.
The LM9812 should be powered by a single +5V source (unless
3V-compatible digital I/O is required-see Section 5.2). The analog
supplies (VA) and the digital supplies (VD and VDI/O) are brought
out individually to allow separate bypassing for each supply input.
They should not be powered by two or more different supplies.
Figure 13 is a mathematical model of the analog front end of one
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STATED. If the voltage on the input pin is at the threshold, large
amounts of current can be drawn from the digital I/O supply
because the N and the P channel of the input buffer are simultaneously on. These latches are very weak (sourcing and sinking
about 50µA typically) and can be easily overdriven.
In systems with separate analog and digital +5V supplies, all the
supply pins of the LM9812 should be powered by the analog +5V
supply. Each supply input should be bypassed to its respective
ground with a 0.1µF capacitor located as close as possible to the
supply input pin. A single 10µF tantalum capacitor should be
placed near the VA supply pin to provide low frequency bypassing.
From
Multiplier
To minimize noise, keep the LM9812 and all analog components
as far as possible from noise generators, such as switching power
supplies and high frequency digital busses. If possible, isolate all
the analog components and signals (OS, reference inputs and
outputs, VA, AGND) on an analog ground plane, separate from
the digital ground plane. The two ground planes should be tied
together at a single point, preferably the point where the power
supply enters the PCB.
10
D0-D9
From
Config
Register
To
Config
Register
5.2 3V Compatible Digital I/O
If 3V digital I/O operation is desired, the VDI/O pin may be powered by a separate 3V±10% or 3.3V±10% supply. In this case all
the digital I/O pins (CD0-CD9, D0-D9, MCLK, SYNC, RUN/STOP,
CS, RD, WR, EOC, GLCK, OCLK, and RD PIXELI) will be 3V
compatible. The CCD clock signals (Ø1, Ø2, RS, TR1 and TR2)
remain 5V outputs, powered by VD. In this case, the VDI/O input
should be bypassed to DGNDI/O with a parallel combination of a
0.1µF capacitor and a 10µF tantalum capacitor.
Figure 14: Weak Latches On Databus
6.3 Don’t Decrement the Reference Sample Position Register by 1
A write to the Reference Sample Position Register (Configuration
Register 22) containing a value that is 1 less than the current
value stored in the Reference Sample Position Register will
sometimes make one of the LM9812’s internal state machines to
fail, causing erratic and improper operation of the LM9812. For
example, if the value currently stored in the Reference Sample
Position Register is 12, then writing an 11 can cause this problem.
5.3 Power Down Mode
Setting the Power Down bit to a “1” puts the device in a low power
standby mode. The CCD outputs (Ø1, Ø2, RS, TR1 and TR2) are
pulled low and the analog sections are turned off to conserve
power. The digital logic will continue to operate if MCLK continues
and SYNC is held high, so for minimum power dissipation MCLK
should be stopped when the LM9812 enters the Power Down
mode. Recovery from Power Down typically takes 50µs (the time
required for the reference voltages to settle to 0.5 LSB accuracy).
To avoid this condition, never decrement the existing value stored
in the Reference Sample Position Register by 1. Incrementing by
any amount or decrementing by 2 or greater or writing the same
number over again will not cause any problems.
6.0 RULES, HINTS, AND COMMON DESIGN PROBLEMS
To get out of this mode, write a new number to the Reference
Sample Position Register that is greater than the original number.
6.1 Ignore MCLK When Designing a System
While the MCLK input is the master clock for all the LM9812 timing, it should not be used to predict when other clocks or events
will occur. To get the highest possible timing resolution, the
LM9812 uses double-edged flip flops for many functions. CCD
clock output signals, coefficient clocks, and internal clocks may
change state on the rising or falling edge of MCLK, depending on
the state of MCLK and some internal free running state machines
when the RUN/STOP or SYNC input goes high. Normal process
variations from part to part result in different delays between an
MCLK edge and other events in the LM9812.
Since incrementing and decrementing this register should only be
done during the development phase of the system until an ideal
value for this register is chosen. This issue should cause absolutely no problems in production, since the value of this register
will be fixed, so the firmware should never write more than the
final ideal value to this register.
6.4 Taking RD Low With CS High Will Drive the Databus
In many digital systems, the RD signal is ignored when CS is held
high. This is not the case with the The LM9812. Taking RD low
with CS high will take the D0-D9 databus out of tristate and put
random data on the databus. Do not assume that RD is ignored
when CS is high.
For a reliable design, synchronize your system to EOC, GCLK,
and OCLK. These signals are repeatable from device to device.
Do not synchronize your system to MCLK: treat it only as a frequency that sets the pixel rate of the system. If you need to generate additional CCD timing signals, synchronize them to the
LM9812’s TR and RS outputs.
6.2 Weak Latches On Databus
The D0-D9 databus has weak latches on its output pins to keep
the databus from drifting through the input’s trip point when TRI-
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Physical Dimensions inches (millimeters)
52-Pin Plastic Leaded Chip Carrier (PLCC)
Order Number LM9812CCV
NS Package Number V52A
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