NSC LM9831CCVJD

N
LM9831 42-Bit Color, 1200dpi USB Image Scanner
General Description
• Stepper motor control tightly coupled with image data buffer
management to maximize data transfer efficiency.
• PWM stepper motor current control allows microstepping for
the price of fullstepping.
• USB interface for Plug and Play operation on USB-equipped
computers.
• Serial EEPROM option for custom Vendor and Product IDs.
• Support for USB bus-powered operation.
• Pixel depths of 1, 2, or 4 bits are packed into bytes for faster
scans of line art and low pixel depth images.
• Supports 3 channel CCDs and 1 channel CIS sensors.
• 3 (R, G, and B) 12-bit, user-programmable gamma correction
tables.
• Compatible with a wide range of color linear CCDs and
Contact Image Sensors (CIS).
• Operates with 48MHz external crystal.
• Internal bandgap voltage reference.
• 100 pin TQFP package
The LM9831 is a complete USB image scanner system on a single IC. The LM9831 provides all the functions (image sensor
control, illumination control, analog front end, pixel processing
function image data buffer/DRAM controller, microstepping
motor controller, and USB interface) necessary to create a high
performance color scanner. The LM9831 scans images in 42 bit
color/14 bit gray, and has output data formats for 24 bit color/8
bit gray. The LM9831 supports sensors with pixel counts of up to
16384 pixels x 3 colors (1200 dpi x 13.6 inches).
The LM9831’s low operating and suspend mode supply currents
allow design of USB bus-powered scanners. The only additional
active components required are an external 4Mbit or 16Mbit
DRAM for data buffering and power transistors for the stepper
motor.
Applications
•
•
Color Flatbed Document Scanners
Color Sheetfed Document Scanners
Key Specifications
•
•
•
•
•
•
Features
• 14 bit ADC digitizes at up to 6Mpixels/s (2M RGB pixels/sec).
• Digital Pixel Processing provides 1200, 800, 600, 400, 300,
200, 150, and 100dpi horizontal resolution from a 1200dpi
sensor and 600, 400, 300, 200, 150, 100, 75, and 50dpi
horizontal resolution from a 600dpi sensor.
• Provides 50-2400dpi vertical resolution in 1 dpi increments.
• Pixel rate error correction for gain (shading) and offset errors.
• Supports 4 or 16Mbit external DRAMs.
• Multiple CCD clocking rates allows matching of CCD clock to
scan resolution and pixel depth for maximum scan speed.
•
Analog to Digital Converter Resolution
Maximum Pixel Conversion Rate
A4 Color 150dpi scan time
A4 Color 300dpi scan time
A4 Color 600dpi scan time
Supply Voltage
- LM9831
- LM9831 DRAM I/O
Typical Operating Current Consumption
14 Bits
6MHz
<10 seconds
<40 seconds
<160 seconds
+4.75V to +5.25V
+2.85 to +5.25V
134mA
LM9831 Scanner System Block Diagram
+24V
USB
Port
Optional Serial
EEPROM
2
Stepper
Motor
2
8
CCD/CIS
1-3
2-6
MISC
I/O
Power
Transistors
LM9831CCVJD
Illumination
30
1-3
DRAM
48MHz Crystal
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
©1999 National Semiconductor Corporation
1
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LM9831 42-Bit Color 1200dpi USB Image Scanner
October 1999
Absolute Maximum Ratings (Notes 1 & 2)
Operating Ratings
+
(Notes 1 & 2)
Operating Temperature Range
TMIN≤TA≤TMAX
LM9831VJD
0°C≤TA≤+70°C
+4.75V to +5.25V
VA Supply Voltage
VD Supply Voltage
+4.75V to +5.25V
+2.85V ≤ VDRAM ≤ VD+100mV
VDRAM Supply Voltage
|VA-VD|
≤ 100mV
Input Voltage Range
-0.05V to V+ + 0.05V
Positive Supply Voltage (V =VA=VD=VDRAM)
With Respect to GND=AGND=DGND
6.5V
Voltage On Any Input or Output Pin
-0.3V to V++0.3V
Input Current at any pin (Note 3)
±25mA
Package Input Current (Note 3)
±50mA
Package Dissipation at TA = 25°C
(Note 4)
ESD Susceptibility (Note 5)
Human Body Model
2000 V
Machine Model
250 V
Soldering Information
Infrared, 10 seconds (Note 6)
235°C
Storage Temperature
-65°C to +150°
Electrical Characteristics
The following specifications apply for AGND=DGND=0V, VA=VD=VDRAM=+5.0VDC,
f CRYSTAL IN= 48MHz. Boldface limits apply for TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. (Notes 8, 9, & 10)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 10)
Units
(Limits)
14
12
bits (min)
Full Channel Characteristics (in units of 12 bit LSBs unless otherwise noted)
Resolution with No Missing Codes
DNL
Differential Non-Linearity
VDRAM=3.3V
-0.47
+0.95
-1
+2.4
LSB (min)
LSB (max)
INL
Integral Non-Linearity Error (Note 11)
VDRAM=3.3V
-3.2
+2.6
-12.6
+7.3
LSB (min)
LSB (max)
Analog Channel Gain Constant
(ADC Codes/V), referred to 14 bits.
Includes voltage reference
variation, gain setting = 1
8192
7412
9300
LSB (min)
LSB (max)
C
VOS1
Pre-Boost Analog Channel Offset Error
26
-34
+76
mV (min)
mV (max)
VOS2
Pre-PGA Analog Channel Offset Error
-30
-80
+31
mV (min)
mV (max)
VOS3
Post-PGA Analog Channel Offset Error
-26
-75
+26
mV (min)
mV (max)
5
bits (min)
V/V (min)
V/V (max)
Coarse Color Balance PGA Characteristics (Configuration Registers 3B, 3C, and 3D)
Monotonicity
G0 (Minimum PGA Gain)
PGA Setting = 0
0.93
0.90
0.96
G31 (Maximum PGA Gain)
PGA Setting = 31
3.00
2.95
3.05
V/V (min)
V/V (max)
x3 Boost Gain
x3 Boost Setting On
(bit B5 of Gain Register is set)
2.94
2.85
3.04
V/V (min)
V/V (max)
0.3
-0.6
+0.9
% (min)
% (max)
6
bits (min)
Gain Error at any gain (Note 13)
Static Offset DAC Characteristics (Configuration Registers 38, 39, and 3A)
Monotonicity
Offset DAC LSB size
PGA gain = 1
9
6
12
mV (min)
mV (max)
Offset DAC Adjustment Range
PGA gain = 1
±278
±256
mV (min)
2
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Electrical Characteristics (Continued)
The following specifications apply for AGND=DGND=0V, VA=VD=VDRAM=+5.0VDC,
f CRYSTAL IN= 48MHz. Boldface limits apply for TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. (Notes 8, 9, & 10)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 10)
Units
(Limits)
CCD/CIS Source Requirements for Full Specified Accuracy and Dynamic Range (Note 12)
VCCDPEAK
Sensor’s Maximum Output Signal
Amplitude before LM9831 Analog Front
End Saturation
Gain = 0.933
Gain = 3.0
Gain = 9.0
1.9
0.6
0.19
V
V
V
nA
Analog Input Characteristics
Average OSR, OSG, OSB Input Current
CDS Enabled, OS = 3.5VDC
±3
OSR, OSG, OSB Input Current
CDS Disabled, OS = 3.5VDC
±26
µA (max)
±30
Internal Voltage Reference Characteristics
VBANDGAP
Voltage Reference Output Voltage
1.23
V
VREF MID-1.0
V
VREF LO
Negative Reference Output Voltage
VREF MID
Midpoint Reference Output Voltage
VA/2.0
V
VREF HI
Positive Reference Output Voltage
VREF MID+1.0
V
3.4
V
VREGULA-
USB I/O Voltage Regulator
TOR
DC and Logic Electrical Characteristics
The following specifications apply for AGND=DGND=0V, VA=VD=VDRAM=+5.0VDC unless otherwise noted,
fCRYSTAL IN= 48MHz. Boldface limits apply for TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. (Notes 8, 9, & 10)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 10)
Units
(Limits)
Digital Input Characteristics for D0-D15 (DRAM Interface)
VIN(1)
Logical “1” Input Voltage
VDRAM=5.25V
VDRAM=3.6V
2.0
2.0
V (min)
V (min)
VIN(0)
Logical “0” Input Voltage
VDRAM=4.75V
VDRAM=2.85V
0.8
0.8
V (max)
V (max)
IIN
Input Leakage Current
C IN
Input Capacitance
±0.1
µA
5
pF
Digital Input Characteristics for PAPER SENSE 1-2, MISC I/O 1-6, SDA, BUS POWER, CRYSTAL/EXT CLOCK, 24/48, RESET,
CMODE
VIN(1)
Logical “1” Input Voltage
VD=5.25V
2.0
V (min)
VIN(0)
Logical “0” Input Voltage
VD=4.75V
0.8
V (max)
IIN
Input Leakage Current
C IN
Input Capacitance
±0.1
µA
5
pF
Digital Input Characteristics for D+, DVIN(1)
Logical “1” Input Voltage
VD=5.25V
VIN(0)
Logical “0” Input Voltage
VD=4.75V
IIN
Input Leakage Current
C IN
Input Capacitance
3
2.0
V (min)
0.8
V (max)
±0.1
µA
5
pF
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DC and Logic Electrical Characteristics (Continued)
The following specifications apply for AGND=DGND=0V, VA=VD=VDRAM=+5.0VDC unless otherwise noted,
fCRYSTAL IN= 48MHz. Boldface limits apply for TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. (Notes 8, 9, & 10)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 10)
Units
(Limits)
Digital Output Characteristics for D0-D15, A0-A9, RD, WR, RAS, CAS (DRAM Interface)
VOUT(1)
Logical “1” Output Voltage
VDRAM=4.75V, I OUT=-4mA
VDRAM=2.85V, I OUT=-4mA
2.4
2.4
V (min)
V (min)
VOUT(0)
Logical “0” Output Voltage
VDRAM=4.75V, I OUT=4mA
VDRAM=2.85V, I OUT=4mA
0.4
0.4
V (max)
V (max)
Digital Output Characteristics for A, B, A, B
VOUT(1)
Logical “1” Output Voltage
VDRAM=4.75V, I OUT=-10mA
VDRAM=2.85V, I OUT=-10mA
2.4
2.4
V (min)
V (min)
VOUT(0)
Logical “0” Output Voltage
VDRAM=4.75V, I OUT=4mA
VDRAM=2.85V, I OUT=4mA
0.4
0.4
V (max)
V (max)
Digital Output Characteristics for MISC I/O 1-6, TR1, TR2, ø1, ø2, RS, CP1, CP2, LAMPR, LAMPG, LAMPB
VOUT(1)
Logical “1” Output Voltage
VD=4.75V, IOUT=-4mA
2.4
V (min)
VOUT(0)
Logical “0” Output Voltage
VD=4.75V, IOUT=4mA
0.4
V (max)
Digital Output Characteristics for D+, DVOUT(1)
Logical “1” Output Voltage
VD=4.75V, IOUT=-1mA
2.4
V (min)
VOUT(0)
Logical “0” Output Voltage
VD=4.75V, IOUT=3mA
0.4
V (max)
CRYSTAL IN, CRYSTAL OUT Characteristics
XTALOUT DC
CRYSTAL OUT Bias Level (Offset)
XTAL OUT AC
CRYSTAL OUT Amplitude
0.8
V
fCRYSTAL = 48MHz
0.8
VP-P
Power Supply Characteristics
IA
Analog Supply Current
(VA pins)
Operating
Suspend
87
1
137
mA (max)
µA (max)
ID
Digital Supply Current
(VD pins)
Operating
Suspend (including IDRAM)
37
14
50
mA (max)
µA (max)
IDRAM
DRAM Supply Current
(VDRAM pins)
Operating, VDRAM = 5V
Operating, VDRAM = 3V
Suspend
10
5
14
21
14
mA (max)
mA (max)
µA (max)
4
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AC Electrical Characteristics
The following specifications apply for AGND=DGND=0V, VA=VD=VDRAM=+5.0VDC unless otherwise noted,
fCRYSTAL IN= 48MHz, MCLK DIVIDER = 1.0 (unless otherwise noted), fMCLK = fCRYSTAL IN/MCLK DIVIDER, fADC CLK = fMCLK/8,
CL (databus loading) = 20pF/pin. Boldface limits apply for TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. (Notes 8, 9, & 10)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 10)
Units
(Limits)
26
35
ns (min)
ns (min)
DRAM Timing (Figure 1)
t RD SETUP
Data valid to RD rising edge
VDRAM=5.0V
VDRAM=3.3V
t RD HOLD
Data valid after RD rising edge
0
ns (min)
tWR SETUP
Data valid before WR falling edge
5
ns (min)
tWR HOLD
Data valid after WR rising edge
10
ns (min)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional,
but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply
only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND=AGND=DGND=0V, unless otherwise specified.
Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (V IN<GND or V IN>VA or V D), the current at that pin should be limited to 25mA. The 50mA
maximum package input current rating limits the number of pins that can simultaneously safely exceed the power supplies with an input current of 25mA to two.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, Θ JA and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJmax - TA) / Θ JA . T Jmax = 150°C for this device. The typical thermal resistance (Θ JA ) of this part when board mounted
is 53°C/W.
Note 5: Human body model, 100pF capacitor discharged through a 1.5kΩ resistor. Machine model, 200pF capacitor discharged through a 0Ω resistor.
Note 6: See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any National Semiconductor Linear
Data Book for other methods of soldering surface mount devices.
Note 7: Two diodes clamp the OS analog inputs to AGND and VA as shown below. This input protection, in combination with the external clamp capacitor and the output
impedance of the sensor, prevents damage to the LM9831 from transients during power-up.
VA
To Internal
Circuitry
OS Input
AGND
Note 8: For best performance, it is required that all supply pins be powered from the same power supply with separate bypass capacitors at each supply pin.
Note 9: Typicals are at TJ =TA=25°C, fCRYSTAL IN = 48MHz, and represent most likely parametric norm.
Note 10: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 11: Integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that best fits the actual transfer function of the ADC.
Note 12: VREF is defined as the CCD OS voltage for the reference period following the reset feedthrough pulse. V WHITE is defined as the peak CCD pixel output voltage for
a white (full scale) image with respect to the reference level, V REF . V RFT is defined as the peak positive deviation above V REF of the reset feedthrough pulse. The maximum
correctable range of pixel-to-pixel V WHITE variation is defined as the maximum variation in VWHITE (due to PRNU, light source intensity variation, optics, etc.) that the
LM9831 can correct for using its internal PGA.
CCD Output Signal
V RFT
V WHITE
V REF
Note 13:
Gain
PGA Gain Error is the maximum difference between the measured gain for any PGA code and the ideal gain calculated by using the formula
PGA code
32
V
---- = G + X --------------------------- where X = ( G – G ) ------ .
31
0 31
0
PGA  V
32
5
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Timing Diagrams
0
1
2
3
4
5
6
0
48MHz Internal Clock
(tPERIOD = 20.83ns)
A0-A9
Row Addressn
Column Addressn
Row Addressn+1
RAS
CAS
RD
tRD HOLD
tRD SETUP
D0-D15
Data
Read Operation
WR
tWR HOLD
tWR SETUP
D0-D15
Data
Write Operation
Figure 1: DRAM Read and Write
0
1
2
3
4
5
6
0
48MHz Internal Clock
(tPERIOD = 20.83ns)
RAS
CAS
Figure 2: DRAM Refresh (CAS before RAS)
6
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ø2
RS
CP1
CP2
ACTIVE/SUSPENDED
DGND
VREGULATOR
D-
D+
BUS POWR
VD
DGND
NC
NC
RESET
CMODE
SENSEB
NC
SENSEA
SENSEGND
TEST
VD
DGND
VA
AGND
Connection Diagram
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
VBANDGAP
1
75
ø1
VREF LO
2
74
TR2
OSR
3
73
TR1
VREF MID
4
72
MISC I/O 6
OSG
5
71
MISC I/O 5
VREF HI
6
70
MISC I/O 4
OSB
7
69
DGND
AGND
8
68
VD
VA
9
67
MISC I/O 3
A
10
66
MISC I/O 2
A
11
65
MISC I/O 1
B
12
64
PAPER SENSE 1
B
13
63
PAPER SENSE 2
D0
14
62
VD
D15
15
61
DGND
VDRAM
16
60
LAMPB
DGND
17
59
LAMPG
D1
18
58
LAMPR
D14
19
57
DGND
D2
20
56
VD
D13
21
55
24/48
D3
22
54
D12
23
53
CRYSTAL/EXT CLK
CRYSTAL IN
D4
24
52
CRYSTAL OUT
D11
25
51
SCL
LM9831VJD
SDA
A4
A3
A5
A2
A6
DGND
VDRAM
A1
A7
A0
A8
A9
RD
WR
RAS
CAS
D8
D7
DGND
VDRAM
D9
D6
D5
D10
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Ordering Information
Commercial (0°C ≤ TA ≤ +70°C)
Package
LM9831CCVJD
VJD100A 100 Pin Thin Quad Flatpac
LM9831CCVJDX
VJD100A 100 Pin Thin Quad Flatpac, Tape and Reel
7
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Pin Descriptions
Scanner Support I/O
USB Interface
D+, D-
Digital I/O. USB Interface signals
BUS POWER
Digital Input. Tie low for bus powered systems, tie high for external power.
ACTIVE/
Digital Output. Low in Suspend mode. High in
operational mode. Used to control external
regulators, other components.
SUSPENDED
SDA
Digital I/O. Serial Data to/from external
EEPROM.
SCL
Digital Output. Serial Clock Output to external
EEPROM.
OSR,
OSB
VREF LO
Analog Inputs. These inputs (for Red, Green,
and Blue) should be tied to the sensor’s output signal through DC blocking capacitors. If
unused, tie to ground through DC blocking
capacitors.
Analog Output/Input. Bypass to AGND with a
0.047µF monolithic capacitor. Do not put a
DC load on this pin.
VREF HI
Analog Output/Input. Bypass to AGND with a
0.047µF monolithic capacitor. Do not put a
DC load on this pin.
VBANDGAP
Analog Output. Bypass to AGND with a
0.047µF monolithic capacitor. Do not put a
DC load on this pin.
VREGULATOR
Analog Output. Bypass to AGND with a
0.047µF monolithic capacitor. Used as terminal voltage for 1.5k D+ pullup resistor.
Digital Inputs/Outputs. Programmable, used
for front panel switches, status LEDs, etc. At
power-on and in Suspend Mode, MISC I/Os
1-3 are inputs and MISC I/Os 4-6 are outputs.
A, B, A, B
Digital Outputs. Pulses to stepper motor drive
circuitry.
SENSEA,
SENSEB
Analog Inputs. Current sensing for stepper
motor’s PWM current control.
SENSEGND
Analog Input. Ground sense input for stepper
motor’s PWM current control.
ø1
Digital Output. CCD/CIS clock signal phase 1.
ø2
Digital Output. CCD/CIS clock signal phase 2.
RS
Digital Output. Reset pulse for the CCD/CIS.
CP1
Digital Output. Clamp pulse for the CCD/CIS.
CP2
Digital Output. Clamp pulse for the CCD/CIS.
TR1, TR2
Digital Outputs. Transfer pulses for the
CCD/CIS.
LAMPR,
Digital Outputs. Used to control R, G, and B
LEDs of single output CIS, as well as brightness of CCFL. The CDS signal can be seen
on LAMPB in a test mode (see register 5E, bit
7).
LAMPG,
LAMPB
Master Clock Generation
DRAM
D0 (LSB) -D15
(MSB)
MISC I/O 1-6
Sensor Control
Analog Output/Input. Bypass to AGND with a
0.047µF monolithic capacitor. Do not put a
DC load on this pin.
VREF MID
Digital Inputs. Programmable, used for sensing home position, paper, front panel
switches, etc.
Stepper Motor
Analog
OSG,
PAPER
SENSE 1-2
Digital Inputs/Outputs. This is the 16 bit data
path between the external DRAM and the
LM9831.
CRYSTAL IN
Digital Input. Used with CRYSTAL OUT and
an external 48MHz crystal to form a crystal
oscillator.
CRYSTAL
OUT
Digital Output. Used with CRYSTAL IN and an
external 48MHz crystal to form a crystal oscillator.
CRYSTAL/
Digital Input. Tie to DGND for operation with
an external crystal. Pull up to VD to drive
CRYSTAL OUT with an external TTL or
CMOS clock source.
EXT CLOCK
RD
Digital Output. Read signal to external DRAM.
WR
Digital Output. Write signal to external DRAM.
A0-A9
Digital Outputs. Address pins for up to 1M x
16 external DRAM.
RAS
Digital Output. Row Address Strobe signal.
CAS
Digital Output. Column Address Strobe signal.
24/48
8
Digital Input. Tie to DGND for operation with a
48MHz crystal or external clock. Pull up to VD
for operation with a 24MHz crystal or external
clock. NOTE: Operation at 24MHz is not guaranteed - always use a 48MHz crystal.
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Miscellaneous
RESET
Digital input. Take high to force device into
Power On Reset state, low to exit reset state.
TEST
Analog Output.
CMODE
Digital Input. Test mode, always tie high.
Analog Power Supplies (4 pins)
VA (2)
This is the positive supply pin for the analog
supply. It should be connected to a voltage
source of +5V and bypassed to AGND with a
0.1µF monolithic capacitor in parallel with a
10µF tantalum capacitor.
AGND (2)
This is the ground return for the analog supply.
Digital Power Supplies (17 pins)
VD (5)
This is the positive supply pin for the digital
supply. It should be connected to a voltage
source of +5V and bypassed to DGND with a
0.1µF monolithic capacitor.
VDRAM(3)
This is the positive supply pin for the digital
supply for the LM9831’s external DRAM I/O. It
also powers the A, B, A, and B stepper motor
outputs. It should be connected to a 3 or 5V
supply and bypassed to the closest DGND pin
with a 0.1µF monolithic capacitor.
DGND (9)
This is the ground return for VD and VDRAM.
9
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LM9831 Register Listing
Registers in bold boxes are reset to that value on power-up. All register addresses are in hexadecimal. All other numbers are
decimal unless otherwise noted.
Address
Function
D D D D D D D D
7 6 5 4 3 2 1 0
Value
IMAGE BUFFER (READ ONLY)
00
Pixel (Image) Data
n n n n n n n n One byte of image data.
STATUS REGISTERS (READ ONLY)
01
Image Data Available In Buffer
02
PAPER SENSE 1 State
read clears bit if edge sensitive input.
PAPER SENSE 2 State
read clears bit if edge sensitive input.
MISC I/O 1 State
read clears bit if edge sensitive input.
MISC I/O 2 State
read clears bit if edge sensitive input.
MISC I/O 3 State
read clears bit if edge sensitive input.
MISC I/O 4 State
read clears bit if edge sensitive input.
MISC I/O 5 State
read clears bit if edge sensitive input.
MISC I/O 6 State
read clears bit if edge sensitive input.
n*2 (256k x 16 DRAM) or n*8 (1M x 16 DRAM)
kilobytes of image data is available
0 False
1 True
0
False
1
True
0
False
1
True
0
False
1
True
0
False
1
True
0
False
1
True
0
False
1
True
0
False
1
True
n n n n n n n n
DATAPORT REGISTERS
0
0
1
1
DataPort Target
0
0
1
1
DataPort Target Color
03
Pause (Read Only)
This bit indicates whether or not the scanner
is currently paused due to a buffer full
condition.
DRAM Test
04
DataPort Address - MSB
05
DataPort Address - LSB
06
DataPort
0
1
0
1
0
1
0
1
Offset Coefficient Data
Gain Coefficient Data
Gamma Lookup Table
N/A
Red
Green
Blue
N/A
0
Normal State
1
The scanner is currently in the pause/reverse cycle.
0
Normal Operation
1
DRAM Test mode
R
Address of location to be read/written to.
/ a a a a a a a = 0 to 4095 for gamma tables,
W
0 to 16383 for Offset and Gain Coefficient Data
Addresses greater than these are illegal.
a a a a a a a a Bit D6 of register 4 indicates whether next operation
will be a Read (D6=1) or a Write (D6=0).
Data to be read from or written to the address of the
currently selected Dataport Target. The DataPort
n n n n n n n n Address is automatically incremented whenever one
(gamma data) or two (Gain/Offset Data) bytes are
read from or written to this register.
10
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Address
Function
D D D D D D D D
7 6 5 4 3 2 1 0
Value
COMMAND REGISTER
Idle - Stops motor (A, B, A, B = 0),
0 0 0 completes current line of data (if scanning).
Note: CCD/CIS clocks continue clocking.
High Speed Forward - Moves motor forward at a
0 0 1 speed determined by the Fast Feed Step Size
(registers 48 and 49).
High Speed Reverse - Moves motor backward at a
0 1 0 speed determined by the Fast Feed Step Size
(registers 48 and 49).
Start Scan - Resets the LM9831’s data pointers and
0 1 1
starts an image scan.
Programmed High Speed Forward - Moves motor
forward at a speed determined by the Fast Feed Step
1 0 1
Size (registers 48 and 49) for the number of lines
programmed in registers 4A and 4B.
Programmed High Speed Reverse - Moves motor
backward at a speed determined by the Fast Feed
1 1 0
Step Size (registers 48 and 49) for the number of lines
programmed in registers 4A and 4B.
Command Register
This register is used to start and end a scan.
It is also used to home the sensor in a
flatbed scanner or eject the image in a
sheetfed scanner. Note: Always make sure
the Command Register is in the idle state
(=0) before issuing a new command.
07
Standby
When this bit is set the entire chip enters a
low power state.
Warning: A Standby command will stop
DRAM refresh.
Reset
Write a 1 then a 0 to reset the LM9831’s
state machines.
Warning: A Reset will stop DRAM refresh.
0
Normal Operation
1
Low Power Standby Mode
0
Normal Operation
1
Resets the LM9831
MASTER CLOCK DIVIDER
08
MCLK Divider
This register sets the master clock frequency
for the entire scanner.
fMCLK = 48MHz/MCLK_Divider
fADC = fMCLK/8
0
0
0
a
1
1
0
0
0
a
1
1
0
0
0
a
1
1
11
0
0
1
a
1
1
0
0
1
a
1
1
0
1
0
a
0
1
÷1.0
÷1.5
÷4
÷ ((aaaaaa/2)+1)
÷32.0
÷32.5
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Address
Function
D D D D D D D D
7 6 5 4 3 2 1 0
Value
HORIZONTAL RESOLUTION AND DATAMODE SETTINGS
0
0
0
0
1
1
1
1
Horizontal DPI Divider
This register determines the horizontal
resolution of the scan.
Scan resolution = Optical resolution divided
by the Horizontal_DPI_Divider.
09
Pixel Packing
This register determines how many bits in
each byte of data are transmitted to the host
when DataMode = 0
DataMode
When DataMode = 0, the pixel data is fully
processed, going through the Offset,
Shading, Horizontal DPI Adjust, Gamma,
and Pixel Packing blocks.
When DataMode = 1, 14 bit data is extracted
following the Shading Multiplier stage.
Gamma and any other post processing must
be done by the host.
0
0
1
1
0
1
0
1
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷1
÷1.5
÷2
÷3
÷4
÷6
÷8
÷12
1 bit/pixel (1 bit grayscale/3 bit color)
2 bits/pixel (2 bit grayscale/6 bit color)
4 bits/pixel (4 bit grayscale/12 bit color)
8 bits/pixel (8 bit grayscale/24 bit color)
1, 2, 4, or 8 bit image data,
as determined by the Pixel Size setting.
14 bit image data - sent in 2 bytes, MSB first:
First Byte: 13 12 11 10 09 08 07 06
Second Byte: 05 04 03 02 01 00 XX XX
(XX: bits set to 0)
1
RESERVED
0A
Reserved
0 0 0 0 0 0 0 0 Write 00 to this register
SENSOR CONFIGURATION
Input Signal Polarity
CDS On/Off
Standard/Even-Odd Sensor
0B
CIS TR1 Timing Mode
Fake Optical Black Pixels
(for Dyna-type CIS sensors)
0 Negative (Most CCD Sensors and Toshiba CIS)
1 Positive (Most CIS Sensors)
0
CDS Off
1
CDS On
0
Standard (1 pixels per Ø period)
1
Even/Odd (2 pixels per Ø period)
0 0
Off - use standard CCD Timing
CIS TR1 Timing Mode 1:
0 1
TR1 pulse = exactly one Ø clock,
starting at rising edge of Ø1
CIS TR1 Timing Mode 2:
1 0
TR1 pulse = exactly one Ø clock,
TR1 centered around Ø1 high.
1 1
N/A
0
Off: Normal operation
1
On: RS pulse held high for entire Optical Black period
12
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Address
Function
D D D D D D D D
7 6 5 4 3 2 1 0
Value
SENSOR CONTROL SETTINGS
Ø1 Polarity
0
1
Ø2 Polarity
0
1
RS Polarity
0C
0
1
CP1 Polarity
0
1
CP2 Polarity
0
1
TR1 Polarity
0
1
TR2 Polarity
Ø1 Active/Off
0
1
Ø2 Active/Off
0
1
RS Active/Off
0
1
CP1 Active/Off
0D
0
1
CP2 Active/Off
0
1
TR1 Active/Off
0
1
TR2 Active/Off
Number of TR Pulses
0E
0F
10
11
12
13
14
15
16
17
18
TR Pulse Duration
TR-Ø1 Guardband Duration
Optical Black Clamp Start
Optical Black Clamp End
Reset Pulse Start
Reset Pulse Stop
CP1 Pulse Start
CP1 Pulse Stop
CP2 Pulse Start
CP2 Pulse Stop
Reference Sample Position
Signal Sample Position
0
1
n n n
n n n n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
0 Positive
1 Negative
Positive
Negative
Positive
Negative
Positive
Negative
Positive
Negative
Positive
Negative
Positive
Negative
0 Off
1 Active
Off
Active
Off
Active
Off
Active
Off
Active
Off
Active
Off
Active
1 TR Pulse
2 TR Pulses
n n+1 pixel periods (1-16)
n pixel periods (0-15)
n pixel rate: n=0-23, line rate: n=0-7 MCLKs from Ø1 edge
n pixel rate: n=0-23, line rate: n=0-7 MCLKs from Ø1 edge
n pixel rate: n=0-23, line rate: n=0-7 MCLKs from Ø1 edge
n pixel rate: n=0-23, line rate: n=0-7 MCLKs from Ø1 edge
n pixel rate: n=0-23, line rate: n=0-7 MCLKs from Ø1 edge
n pixel rate: n=0-23, line rate: n=0-7 MCLKs from Ø1 edge
n pixel rate: n=0-23, line rate: n=0-7 MCLKs from Ø1 edge
n pixel rate: n=0-23, line rate: n=0-7 MCLKs from Ø1 edge
n pixel rate: n=0-23, line rate: n=0-7 MCLKs from Ø1 edge
n pixel rate: n=0-23, line rate: n=0-7 MCLKs from Ø1 edge
INTEGRATION TIME ADJUST
19
Integration Time Adjustment Function
n n n n n n n tREADOUT = n*tINT, n = 1 to 127. n=0 turns off function.
STEPPER PHASE CORRECTION
1A
TR to Stepper Phase Correction - MSB
1B
TR to Stepper Phase Correction - LSB
First step of scan occurs n pixels (1 - 16383) after first
n n n n n n TR pulse. This register can be used to set the phase
between the TR pulses and the stepper motor pulses.
NOTE: a setting of n = 0 creates the maximum delay
n n n n n n n n (16384) pixels, which will increase scan time. If this
function is not used, this register should be set to 1.
13
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Address
Function
D D D D D D D D
7 6 5 4 3 2 1 0
Value
SENSOR PIXEL CONFIGURATION
1C
1D
Optical Black Pixels Start
Optical Black Pixels End
n n n n n n n n n pixels (0 - 255)
n n n n n n n n n pixels (0 - 255)
1E
Active Pixels Start - MSB
1F
Active Pixels Start - LSB
20
Line End - MSB
21
Line End - LSB
n n n n n n n pixels (0 - 16383)
Set to the same value as register Data Pixels Start.
n n n n n n n n
n pixels (0 - 16383)
n n n n n n
This selects the pixel count at which the current line is
ended and the next line begins. This determines the
n n n n n n n n
integration time of one line.
PIXEL DATA RANGE TO PROCESS
22
Data Pixels Start - MSB
23
Data Pixels Start - LSB
24
Data Pixels End - MSB
25
Data Pixels End - LSB
n pixels (Active Pixels Start - 16383)
This selects the start of the range of pixels transmitted
to the PC and determines the pixel location where
n n n n n n n n offset and shading correction begins (pixel 0 in the
DataPort). This value must be >= Active Pixels Start
n n n n n n n pixels (Data Pixels Start - [Line End - 20])
This selects the end of the range of pixels transmitted
n n n n n n n n
to the PC. This value must be <= [Line End - 20]
n n n n n n
COLOR MODE SETTINGS
0
0
1
1
AFE Operation
3 Channel or 1 Channel
26
0
0
1
1
1 Channel Grayscale Input Source
(1 Channel Color always uses the
Blue Channel as the input)
TRRED (=TR1) position
(3 Channel Line Rate Mode only)
TRGREEN (=TR2) position
(3 Channel Line Rate Mode only)
TRBLUE (=CP2) position
(3 Channel Line Rate Mode only)
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
3 Channel Line Rate TR GREEN drop
(3 Channel Line Rate Mode only)
0
0
1
1
3 Channel Line Rate TR BLUE drop
(3 Channel Line Rate Mode only)
Triple TR output
0
1
0
1
0
1
0
1
3 Channel Line Rate TR RED drop
(3 Channel Line Rate Mode only)
27
0
0
0
0
0
1
0
1
0
1
0
1
0
1
3 Channel Pixel Rate Color
3 Channel Line Rate Color
1 Channel Grayscale
1 Channel Color
Red Channel
Green Channel
Blue Channel
N/A
1st TR pulse position (inside Ø1 high)
2nd TR pulse position (inside Ø1 low)
1st TR pulse position (inside Ø1 high)
2nd TR pulse position (inside Ø1 low)
1st TR pulse position (inside Ø1 high)
2nd TR pulse position (inside Ø1 low)
Do not drop any TRRED pulses
Drop 1 TR RED pulse (double integration time)
Drop 2 TR RED pulses (triple integration time)
N/A
Do not drop any TRGREEN pulses
Drop 1 TR GREEN pulse (double integration time)
Drop 2 TR GREEN pulses (triple integration time)
N/A
Do not drop any TRBLUE pulses
Drop 1 TR BLUE pulse (double integration time)
Drop 2 TR BLUE pulses (triple integration time)
N/A
Normal operation
Outputs single TR pulse on TR1, TR2, and CP2 pins
RESERVED
28
Reserved
0 0 0 0 0 0 0 0 Write 00 to this register
14
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Address
Function
D D D D D D D D
7 6 5 4 3 2 1 0
Value
ILLUMINATION SETTINGS
Illumination Mode
Controls the function of the 3 LAMP outputs:
LAMPR, LAMPG, and LAMPB
0 0
Mode 0 is the Off/Reset state.
0 1
Mode 1 is typically used for CCFL lamps.
29
Mode 2 is for color scanning with tri-color
LEDs.
1 0
1 1
2A
2B
2C
Mode 3 is for grayscale scanning with tricolor LEDs.
LAMPG PWM - MSB (Illumination Mode 1)
LAMPG PWM - LSB (Illumination Mode 1)
LAMPR On - MSB
n n n n
n n n n n n n n
n n n n n n
2D
LAMPR On - LSB
n n n n n n n n
2E
LAMPR Off - MSB
n n n n n n
2F
LAMPR Off - LSB
n n n n n n n n
30
LAMPG On - MSB
n n n n n n
31
LAMPG On - LSB
n n n n n n n n
32
LAMPG Off - MSB
n n n n n n
33
LAMPG Off - LSB
n n n n n n n n
34
LAMPB On - MSB
n n n n n n
n n n n n n n n
35
LAMPB On - LSB
36
LAMPB Off - MSB
n n n n n n
37
LAMPB Off - LSB
n n n n n n n n
LAMPR = LAMPG = LAMPB = 0V
(Power-On/Reset Default)
Illumination Mode 1 - LAMPR and LAMPB turn on
every line, with their on and off points controlled by
the Pixel Counter settings. LAMPG Output is
continuous PWM pulse stream. (Figure 20)
LAMPR and/or LAMPB may be set to stay on or off at
all times by setting the LAMP Off or LAMP On settings
(registers 2C-37) greater than the Line End value
(registers 20 and 21).
Illumination Mode 2 - LAMPR, LAMPG, LAMPB turn on
sequentially at the line rate, with their on and off
points controlled by Pixel Counter settings. (Figure
21)
Illumination Mode 3 - LAMPR, LAMPG, LAMPB turn on
every line, with their on and off points controlled by
the Pixel Counter settings. (Figures 22 and 23)
LAMPG output is a PWM pulse stream. Duty cycle is
n/4095. Frequency = 48Mhz/4096 = 11.7kHz
n pixels (1 - 16384)
This selects the pixel count at which the LAMPR
output goes high (if programmed)
n pixels (1 - 16384)
This selects the pixel count at which the LAMPR
output goes low (if programmed)
n pixels (1 - 16384)
This selects the pixel count at which the LAMPG
output goes high (if programmed)
n pixels (1 - 16384)
This selects the pixel count at which the LAMPG
output goes low (if programmed)
n pixels (1 - 16384)
This selects the pixel count at which the LAMPB
output goes high (if programmed)
n pixels (1 - 16384)
This selects the pixel count at which the LAMPB
output goes low (if programmed)
STATIC OFFSET AND GAIN SETTINGS FOR ANALOG FRONT END
38
Static Offset (Red)
39
Static Offset (Green)
3A
Static Offset (Blue)
3B
Static Gain (Red)
3C
Static Gain (Green)
3D
Static Gain (Blue)
0
1
0
1
0
1
0
1
0
1
0
1
n
n
n
n
n
n
n
n
n
n
n
n
15
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
Offset = +n*9.3mV, n = 0 to 31
Offset = -n*9.3mV, n = 0 to 31
Offset = +n*9.3mV, n = 0 to 31
Offset = -n*9.3mV, n = 0 to 31
Offset = +n*9.3mV, n = 0 to 31
Offset = -n*9.3mV, n = 0 to 31
Gain = 0.93 + 0.067*n (V/V), n = 0 to 31
Gain = 3(0.93 + 0.067*n) (V/V), n = 0 to 31
Gain = 0.93 + 0.067*n (V/V), n = 0 to 31
Gain = 3(0.93 + 0.067*n) (V/V), n = 0 to 31
Gain = 0.93 + 0.067*n (V/V), n = 0 to 31
Gain = 3(0.93 + 0.067*n) (V/V), n = 0 to 31
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Address
Function
D D D D D D D D
7 6 5 4 3 2 1 0
Value
DIGITAL PIXEL RATE OFFSET AND GAIN SETTINGS
3E
3F
40
41
Fixed Offset Coefficient - MSB
Fixed Offset Coefficient - LSB
Fixed Multiplier Coefficient - MSB
Fixed Multiplier Coefficient - LSB
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
0
n
n
n
Fixed Offset to use for calibration
0
n
Fixed Gain to use for calibration
n
DIGITAL PIXEL RATE OFFSET AND GAIN/DRAM SETTINGS
Shading Multiplier
Multiplier Coefficient Source
42
Offset Coefficient Source
1 0
Reserved
DRAM Size
0
1
16
0 Gain = [Multiplier Coefficent]/16384
1 Bypass Multiplier
0
Configuration Register 40 and 41 (Fixed)
1
External DRAM
0
Configuration Register 3E and 3F (Fixed)
1
External DRAM
Set to 10
256k x 16
1M x 16
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Address
Function
D D D D D D D D
7 6 5 4 3 2 1 0
Value
STEPPER MOTOR CONTROL SETTINGS
43
44
n lines saved in DRAM for every m lines (register 44)
scanned, function bypassed if register value = 0.
n (Line Skipping)
Part of the “n out of m” function, consisting of t t t t t t t t n (lines saved per m lines scanned) = 256 - t
registers 43, 44, and 54 (bits 3-7).
t = 256 - n
If t = 0 then function is bypassed.
n lines (register 43) saved in DRAM for every m lines
m (Line Skipping)
Part of the “n out of m” function, consisting of m m m m m m m m scanned. m = 1 to 255.
registers 43, 44, and 54 (bits 3-7).
If m = 0 then function is bypassed.
0 Full Step Mode
Full/Microstepping
1 Microstepping Mode
1 Phase - No microstepping, just kickstart/stop
Current Sensing Phases
0
= 0 for fullstepping
functions
= 1 for microstepping
1
2 Phases - necessary for microstepping
0
Positive (A/B/A/B Output high = winding energized)
Stepper Motor Phase A Polarity
Negative (A/B/A/B output low = winding energized)
WARNING: When idle, this setting leaves the motor
energized for unipolar motors, and will destroy bipolar
motor drivers. Keep this bit set to a 0.
1
45
0
Stepper Motor Phase B Polarity
1
A, B, A, and B stepper motor status
46
47
48
49
4A
4B
Positive (A/B/A/B Output high = winding energized)
0
1
n
n
n
n
n
n
Scanning Step Size - MSB
Scanning Step Size - LSB
Fast Feed Step Size - MSB
Fast Feed Step Size - LSB
Fullsteps to Skip at Start of Scan - MSB
Fullsteps to Skip at Start of Scan - LSB
Fullsteps to Scan after PAPER SENSE 2
trips -MSB
Fullsteps to Scan after PAPER SENSE 2
trips -LSB
n n n
n n n
n
n n n
n n
n n n
Pause scanning, stop/reverse motor
n n n n n n n n
4F
Resume scanning, start motor
n n n n n n n n
50
Full steps to reverse when buffer is full
Acceleration Profile (stopped)
Acceleration Profile (25%)
Acceleration Profile (50%)
Default Phase Difference - High Byte
Default Phase Difference - Mid Byte
Default Phase Difference - Low Byte
Lines to Process After Pause/
Lines to Discard after Resume
Line Skipping Phase
Part of the “n out of m” function, consisting of
registers 43, 44, and 54 (bits 3-7).
Line Skipping Color Phase Delay
Part of the “n out of m” function, consisting of
registers 43, 44, and 54 (bits 3-7).
Kickstart steps (fullstepping mode)
Hold Current Timeout
4C
4D
4E
51
52
53
54
55
56
Stepper Motor PWM Frequency
57
Stepper Motor PWM Set Duty Cycle
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
Negative (A/B/A/B output low = winding energized)
WARNING: When idle, this setting leaves the motor
energized for unipolar motors, and will destroy bipolar
motor drivers. Keep this bit set to a 0.
A, B, A, and B output pins in Tri-State
A, B, A, and B output pins active
The step size of one microstep while scanning, in
units of pixel periods (minimum 2)
The step size of one microstep while fast feeding, in
units of pixel periods (minimum 2)
When scan starts, paper is fed forward n full steps (0 32767) at highest speed. For “zooming” in flatbeds
n n n n Adds a delay of n (0-4095) full steps between when
PAPER SENSE 2 trips and when the scanning bit is
n n n n n n n n reset, terminating the scan/motor movement
0
Pause scan when buffer is n*2 (16 x 256k) or
n*8 (16x1M) kbytes full
Resume scan when buffer is n*2 (16 x 256k) or
n*8 (16x1M) kbytes full
n (0-63) full steps (0 = do not reverse)
n (0-3) full step time units pause while stopped
n (0-3) full steps at 25% speed
n (0-3) full steps at 50% speed
18 bit word used to calculate when motor resumes
after reversing and stopping. 1 < n < 262143. 2 bits in
register 51 are the most significant bits of 18 bit word.
n (0-7) lines. This only applies if the motor doesn’t
reverse (reverse steps = 0)
Red sensor data arrives before Green sensor
1
Blue sensor data arrives before Green sensor
n n n n n n
n n
n n
n n
n n
n n n n n n n n
n n n n n n n n
n n n
n n n n
n lines, n = 0-15
n n n Motor gets maximum current for first n (0-7) full steps
Full step time units (1-31) (do not set to 0)
=CRYSTAL OUT/(256*n) (0 < n < 256)
n n n n n n n n
=CRYSTAL OUT/(256*256) (n = 0)
n n n n n n = minimum of n/64 (default = 0)
n n n n n
17
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Address
Function
D D D D D D D D
7 6 5 4 3 2 1 0
Value
PAPER SENSE SETTINGS
PAPER SENSE 1: Polarity
PAPER SENSE 1: Level/Edge sensitive
PAPER SENSE 1: Stop Scan
58
PAPER SENSE 2: Polarity
PAPER SENSE 2: Level/Edge sensitive
PAPER SENSE 2: Stop Scan
0 A low input on PAPER SENSE 1 is True
1 A high input on PAPER SENSE 1 is True
Level sensitive: PAPER SENSE 1 State bit (in Status
0
Register) is set to a 1 if PAPER SENSE 1 is currently
True.
Edge sensitive: PAPER SENSE 1 State bit (in Status
1
Register) is set to a 1 if PAPER SENSE 1 has been
True since the last time the Status Register was read.
Transitions on PAPER SENSE 1 will not clear the
0
scanning bit.
A False - to - True transition on PAPER SENSE 1 will
1
clear the Command Register and stop the scan.
0
A low input on PAPER SENSE 2 is True
1
A high input on PAPER SENSE 2 is True
Level sensitive: PAPER SENSE 2 State bit (in Status
0
Register) is set to a 1 if PAPER SENSE 2 is currently
True.
Edge sensitive: PAPER SENSE 2 State bit (in Status
1
Register) is set to a 1 if PAPER SENSE 2 has been
True since the last time the Status Register was read.
Transitions on PAPER SENSE 2 will not clear the
0
scanning bit.
A False - to - True transition on PAPER SENSE 2 will
clear the Command Register and stop the scan (after
1
the number of lines specified in the Lines to Scan
after PAPER SENSE 2 trips register).
MISC I/O PIN SETTINGS
MISC I/O 1: Input or Output
MISC I/O 1: Polarity
(if configured as an input)
MISC I/O 1: Level/Edge sensitive
(if configured as an input)
MISC I/O 1: Output State
(if configured as an output)
Power On/USB Suspend Default: Input
59
MISC I/O 2: Input or Output
MISC I/O 2: Polarity
(if configured as an input)
MISC I/O 2: Level/Edge sensitive
(if configured as an input)
MISC I/O 2: Output State
(if configured as an output)
Power On/USB Suspend Default: Input
0 The MISC I/O 1 pin is configured as an input.
1 The MISC I/O 1 pin is configured as an output.
0
A low input on MISC I/O 1 is True
1
A high input on MISC I/O 1 is True
Level sensitive: MISC I/O 1 State bit (in Status
0
Register) is set to a 1 if MISC I/O 1 is currently True.
Edge sensitive: MISC I/O 1 State bit (in Status
1
Register) is set to a 1 if MISC I/O 1 has been True
since the last time the Status Register was read.
The output of the MISC I/O 1 pin will be a logic low
0
(0V).
The output of the MISC I/O 1 pin will be a logic high
1
(5V).
0
The MISC I/O 2 pin is configured as an input.
1
The MISC I/O 2 pin is configured as an output.
0
A low input on MISC I/O 2 is True
1
A high input on MISC I/O 2 is True
Level sensitive: MISC I/O 2 State bit (in Status
0
Register) is set to a 1 if MISC I/O 2 is currently True.
Edge sensitive: MISC I/O 2 State bit (in Status
1
Register) is set to a 1 if MISC I/O 2 has been True
since the last time the Status Register was read.
The output of the MISC I/O 2 pin will be a logic low
0
(0V).
The output of the MISC I/O 2 pin will be a logic high
1
(5V).
18
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Address
Function
D D D D D D D D
7 6 5 4 3 2 1 0
MISC I/O 3: Input or Output
MISC I/O 3: Polarity
(if configured as an input)
0
1
0
MISC I/O 3: Level/Edge sensitive
(if configured as an input)
5A
(NEW)
1
MISC I/O 3: Output State
(if configured as an output)
Power On/USB Suspend Default: Input
0
1
0
1
MISC I/O 4: Input or Output
MISC I/O 4: Polarity
(if configured as an input)
0
1
0
MISC I/O 4: Level/Edge sensitive
(if configured as an input)
1
MISC I/O 4: Output State
0
(if configured as an output)
Power On/USB Suspend Default: Output,
1
Logic High
MISC I/O 5: Input or Output
MISC I/O 5: Polarity
(if configured as an input)
0
1
0
MISC I/O 5: Level/Edge sensitive
(if configured as an input)
5B
(NEW)
1
MISC I/O 5: Output State
(if configured as an output)
Power On/USB Suspend Default: Output,
Logic High
0
1
0
1
MISC I/O 6: Input or Output
MISC I/O 6: Polarity
(if configured as an input)
0
1
0
MISC I/O 6: Level/Edge sensitive
(if configured as an input)
1
MISC I/O 6: Output State
0
(if configured as an output)
Power On/USB Suspend Default: Output,
1
Logic Low
19
Value
0 The MISC I/O 3 pin is configured as an input.
1 The MISC I/O 3 pin is configured as an output.
A low input on MISC I/O 3 is True
A high input on MISC I/O 3 is True
Level sensitive: MISC I/O 3 State bit (in Status
Register) is set to a 1 if MISC I/O 3 is currently True.
Edge sensitive: MISC I/O 3 State bit (in Status
Register) is set to a 1 if MISC I/O 3 has been True
since the last time the Status Register was read.
The output of the MISC I/O 3 pin will be a logic low
(0V).
The output of the MISC I/O 3 pin will be a logic high
(5V).
The MISC I/O 4 pin is configured as an input.
The MISC I/O 4 pin is configured as an output.
A low input on MISC I/O 4 is True
A high input on MISC I/O 4 is True
Level sensitive: MISC I/O 4 State bit (in Status
Register) is set to a 1 if MISC I/O 4 is currently True.
Edge sensitive: MISC I/O 4 State bit (in Status
Register) is set to a 1 if MISC I/O 4 has been True
since the last time the Status Register was read.
The output of the MISC I/O 4 pin will be a logic low
(0V).
The output of the MISC I/O 4 pin will be a logic high
(5V).
0 The MISC I/O 5 pin is configured as an input.
1 The MISC I/O 5 pin is configured as an output.
A low input on MISC I/O 5 is True
A high input on MISC I/O 5 is True
Level sensitive: MISC I/O 5 State bit (in Status
Register) is set to a 1 if MISC I/O 5 is currently True.
Edge sensitive: MISC I/O 5 State bit (in Status
Register) is set to a 1 if MISC I/O 5 has been True
since the last time the Status Register was read.
The output of the MISC I/O 5 pin will be a logic low
(0V).
The output of the MISC I/O 5 pin will be a logic high
(5V).
The MISC I/O 6 pin is configured as an input.
The MISC I/O 6 pin is configured as an output.
A low input on MISC I/O 6 is True
A high input on MISC I/O 6 is True
Level sensitive: MISC I/O 6 State bit (in Status
Register) is set to a 1 if MISC I/O 6 is currently True.
Edge sensitive: MISC I/O 6 State bit (in Status
Register) is set to a 1 if MISC I/O 6 has been True
since the last time the Status Register was read.
The output of the MISC I/O 6 pin will be a logic low
(0V).
The output of the MISC I/O 6 pin will be a logic high
(5V).
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Address
Function
D D D D D D D D
7 6 5 4 3 2 1 0
Value
TEST MODE SETTINGS
5C
5D
ADC Output Code - MSB
ADC Output Code - LSB
ADC Test Mode
Pixel Processing Input Select
5E
16 bit Counter Increment Select
(16 bit counter starts at 0, increments every
datapixel)
MCLK edge for AFE (Set this bit to 0)
CDS Signal
5F-7F
Reserved
n n n n n n n
n n n n n n n
0
0
Used to force the input to the HDPI Divider to a known
value for digital tests
Normal Operation
Bypass AFE, Normal ADC Operation
Bypass AFE, bypass ADC digital correction,
1 0
output uncorrected ADC MSB
Bypass AFE, bypass ADC digital correction,
1 1
output uncorrected ADC LSB
0 0
Normal Operation - ADC Output
0 1
Registers 5C and 5D
1 0
16 bit counter, reset at the start of every scan
1 1
16 bit counter, reset at the start of every line
0 0
Increments by 1
0 1
Increments by 4
1 0
Increments by 16
1 1
N/A
0
Rising
1
Falling
0
Normal Operation
1
CDS signal is output on LAMPB pin
0 0 0 0 0 0 0 0 Write 00 to these registers
20
n
n
0
1
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Applications Information
The number of pixels coming out of the Pixel Processing block is
equal to the integer portion of the number of pixels going in to the
Pixel Processing block divided by the “Divide By” setting, from the
table shown in Figure 4.
1.0 OVERVIEW
The LM9831 is a USB, 1200dpi, 14 bit (42 bit color) scanner-ona-chip.
Pixels
OUT
PixelsIN
= INT  -------------------------
 Divide By
2.0 ANALOG SIGNAL PROCESSING
This equation also applies to the divide by 1.5 function.
One channel of the LM9831’s analog front end is shown in Figure
3. The gain through each channel can be set between 0.93V/V
and 9.0V/V using registers 3B, 3C, and 3D. The offset DAC provides up to ±278mV of offset correction using registers 38, 39,
and 3A. The offset DAC and gain stages should be adjusted during coarse calibration so that the input signal is a maximum of
1.9Vp-p at the ADC input.
Divide
By
DPI
(1200
DPI
system)
DPI
(800
DPI
system)
DPI
(600
DPI
system)
DPI
(300
DPI
system)
1
1.5
2
3
4
6
8
12
1200
800
600
400
300
200
150
100
800
533
400
267
200
133
100
67
600
400
300
200
150
100
75
50
300
200
150
100
75
50
37.5
25
3.0 DIGITAL SIGNAL PROCESSING
3.1 ADC
The digital pixel data comes from a 6MHz 14 bit pipelined ADC.
The output data is formatted as a 16 bit word. The pixel data is in
the upper 14 bits, and the lower two bits are set to 0.
Figure 4: Decreasing Horizontal Resolution
3.2 Pixel Processing Block
The Pixel Processing stage is used to digitally reduce the optical
resolution of the sensor. The optical resolution can be reduced by
a factor of 1, 1.5, 2, 3, 4, 6, 8, or 12. For a 1200 dpi (optical) system, this would produce resolutions of 1200, 800, 600, 400, 300,
200, 150, and 100. A 600 dpi (optical) system would be capable
of 600, 400, 300, 200, 150, 100, 75, and 50 dpi. (Resolution in the
vertical direction is controlled by the stepper motor speed.)
If there are not enough pixels at the end of a line to form a complete pixel, the last pixel will be eliminated. For example, if a line
is 35 pixels wide and the Horizontal DPI setting is set to divide by
6, then the output of the Pixel Processing block will be 5 pixels
(the integer portion of 35/6). The last 5 pixels will be discarded,
since 6 pixels would be required to form a new pixel in this mode.
Horizontal resolution reduction is accomplished by averaging
adjacent pixels. Averaging produces better image quality and
reduces aliasing versus the traditional technique of simply discarding pixels to reduce resolution. For example, to get 100 dpi
from a 300dpi optical sensor, you would average 3 300dpi pixels:
The output of this stage is sent to the Pixel Rate Offset Correction
Block.
3.3 Pixel Rate Offset Correction Block
Offset correction words for every pixel of the CCD are stored in
the external DRAM and accessed at the pixel rate. A digital subtractor subtracts the 16 bit offset word (corresponding to that
pixel’s offset error) from each pixel.
p
+p
+p
n-2
n-1
n
pixel
= -------------------------------------------100dpi
3
PGA
0.93V/V to
3V/V
Gain Boost
1V/V or
3V/V
VIN
+
Σ
+
VOS1
GB
+
Σ
+
VOS2
+
Σ
+
GPGA
VDAC
+
Σ
+
VOS3
14 Bit
ADC
DOUT
Offset
DAC
DOUT = (((VIN + VOS1)GB + VDAC + VOS2)GPGA + VOS3)C
simplified, with all offsets = 0, this is:
DOUT = (VINGB + VDAC)GPGAC
C is a constant that combines the gain error through the AFE, reference voltage variance, and analog voltage
to digital code conversion into one constant. Ideally, C = 8192 codes/V (16384codes/1.9V).
Manufacturing tolerances widen the range of C. See Electrical Specifications.
Figure 3: Analog Front End (AFE) Model
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The subtractor saturates at 0, i.e. if the coefficient to be subtracted is greater than the ADC output code, the result is an output of 0.
3.6 Pixel Packing/Thresholding Block
Some scans require only one bit per pixel (“line art” mode), others
may need only 2 or 4 bits/pixel. To increase scanning speed for
lower pixel depths, the LM9831 packs the desired MSBs of multiple pixels together into 1 16 bit word, increasing the transmission
speed to the host by a factor of 2, 4, 8, or 16. Figure 6 shows how
the pixels are packed together for 8, 4, 2, and 1 bit pixel depths.
In Figure 6, “b” indicates the bit position (b7 = the most significant
and b0 = the least significant bit) of the original 8 bit pixel data,
and pn indicates the original pixel sequence, i.e p0, p1, p2, p3...
The offset words stored in DRAM are typically calculated by
scanning a black calibration strip at 14 bits, and storing the
results in the DRAM using the DataPort.
The offset subtractor only uses the upper 14 bits of the 16 bit
word. When scanning in 14 bit mode, a pixel is transmitted as a
16 bit word, with the upper 14 bits containing the image data. The
2 LSBs of the image data and the offset correction word should
be 00.
If there are not enough unpacked pixels at the end of a line to
complete the packed word for transmission, that final word is not
sent. For example, doing an 8 bit pixel rate scan with a HDPI
divider of 1 and an odd number of pixels will truncate the blue
component of the last pixel.
The offset correction equation is:
Pixel
OUT
= Pixel
IN
– coefficient
3.4 Pixel Rate Gain Correction Block
This is a digital multiplier that multiplies the output word from the
subtractor by a 16 bit digital correction coefficient corresponding
to that pixel’s gain error. The coefficients are stored in the external RAM and accessed at the pixel rate.
The multiplier saturates at 16383, i.e. if the result of the multiplication is greater than 16383, the multiplier output is 16383.
Pixel
Depth
bit
15
8
4
2
1
b7 p0
b7 p0
b7 p0
b7 p0
bit
7
The gain equation is:
PixelOUT = PixelIN
8
4
2
1
coefficient
⋅ -------------------------16384
Note that a coefficient of 0 represents a gain of 0. On the LM9830
and previous parts, a coefficient of 0 represented a gain of 1. To
achieve a gain of 1, the coefficient should be set to 16384.
b7 p1
b7 p2
b7 p4
b7 p8
bit
14
b6
b6
b6
b7
p0
p0
p0
p1
bit
6
b6
b6
b6
b7
p1
p2
p4
p9
bit
13
bit
12
b5 p0
b5 p0
b7 p1
b7 p2
b4 p0
b4 p0
b6 p1
b7 p3
bit
5
bit
4
bit
11
b3
b7
b7
b7
p0
p1
p2
p4
bit
3
bit
10
bit
9
b2 p0
b6 p1
b6 p2
b7 p5
b1 p0
b5 p1
b7 p3
b7 p6
bit
2
bit
1
bit
8
b0
b4
b6
b7
p0
p1
p3
p7
bit
0
b5 p1 b4 p1 b3 p1 b2 p1 b1 p1 b0 p1
b5 p2 b4 p2 b7 p3 b6 p3 b5 p3 b4 p3
b7 p5 b6 p5 b7 p6 b6 p6 b7 p7 b6 p7
b7 p10b7 p11 b7 p12b7 p13b7 p14b7 p15
Figure 6: Packing Multiple Pixels Into One Word
The gamma table in 3.5 Gamma Correction Tables allows the
user to set the threshold of each transition for various line art or
reduced pixel depth modes.
3.5 Gamma Correction Tables
There are 3 gamma lookup tables for R, G, and B. The input to
the table is the 12 MSBs (most significant bits) of the 14 bit pixel
data coming from the previous stage (3.4 Pixel Rate Gain Correction Block). The output is the 8 bit gamma corrected pixel
data. The tables consume 12k words (4K bytes x 16 bits, only the
8 LSBs of each word is used) of the external DRAM. Each
gamma table (red, green, and blue) can be loaded with any arbitrary user-defined transfer curve.
3.7 14 Bit Output Mode
For calibration purposes, it is useful to get the 14 bit data from the
ADC. This mode is set through register 9, bit 5. In the 14 bit output mode, the gamma and pixel packing stages are bypassed,
and the 14 bit data from the ADC is stored in DRAM, formatted as
shown in Figure 7.
255
8 Bit Pixel Out
MSB
LSB
15
14
13
12
11
10
9
8
b13
b12
b11
b10
b9
b8
b7
b6
7
6
5
4
3
2
1
0
b5
b4
b3
b2
b1
b0
0
0
Figure 7: 14 Bit Output Mode Data Format
The 14 bit data is stored as a 16 bit word, with the 2 least significant bits of the 16 bit word set to 0.
0
0
12MSBs of 14 bit Output
4095
Figure 5: Gamma Table
3.8 Line Buffer
The line buffer uses the external DRAM as a FIFO line buffer to
store the pixel data (which is generated at a fixed rate, synchronous to the CCD clocks) and send it back to the PC at an asynchronous, unpredictable, and non-constant rate.
The gamma tables are loaded through the dataport (see 6.1 The
DataPort: Reading and Writing to Gamma, Offset, and Gain
Memory). The DataPort selects which color (Red, Green or Blue)
gamma table will be read from or written to.
The LM9831 supports 2 sizes of DRAM, 256k x 16bit and 1M x
16bit. 216kbytes (108kwords) of the capacity of the DRAM is consumed by the offset and shading coefficients and the gamma
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of the image sensor, determines the effective vertical resolution
(Lines Per Inch, or LPI).
tables. That leaves 296kbytes of memory available for line buffer
when using a 256k x 16 bit DRAM, or 1832kbytes of memory
when using a 1M x 16 bit DRAM.
The stepper motor is moved forwards and backwards by two signals, A and B, 90° out of phase with each other. The phase for
the forward direction is set in Configuration Register 45.
The line buffer is tightly coupled to the stepper motor (4.0 Stepper Motor Controller), and is responsible for stopping the motor
before the buffer overflows and starting the motor again as the
buffer nears empty.
The A and B signals are either squarewaves (in Full Step Mode,
Figure 8), or a staircase approximation of a sine wave (in
Microstep mode, Figures 10 and 11).
If the scanner is generating pixel data faster than the PC can
acquire it, the line buffer will start to fill up. As the buffer nears
100% of its capacity, the scan must be paused before it starts
acquiring a line which will overflow the buffer. This Pause Threshold limit (register 4E) is programmable in 2 kbyte (256k x 16 bit
DRAM) or 8kbyte (1M x 16 bit DRAM) increments between 0 and
255.
A
A
1 full step = 4
microsteps
To maximize scanner performance and minimize pausing due to
buffer full conditions, the pause threshold should be set using this
formula:
B
Pause Threshold (kB) = Available_Memory - (Line_Length + 1)
B
where Available_Memory = 296kbytes (256k x 16b DRAM) or
1832kbytes (1M x 16 bit DRAM),
Figure 8: Stepper Motor Waveform - Full Stepping
Line_Length = (Bytes/Line)/1024
The LM9831 always counts stepper motor steps in units of
microsteps. A full step is equal to four microsteps. Even when the
LM9831 is in Full Step Mode, it is counting in microsteps, and will
increment the stepper motor (generating a full step) every four
microsteps.
Data Pixels 
 INT  ----------------------------------- ⋅ C ⋅ B
 HDPI_Divider


Bytes/Line = 2 ⋅ INT  ------------------------------------------------------------------------
16




The microstep Step Size is defined in units of time. These units of
time are pixel periods, as defined in the horizontal pixel counter.
In the 3 Channel Pixel Rate input mode, the pixel period is the
fADC/3 (= f MCLK/24). In the 3 Channel Line Rate and 1 channel
modes, the pixel period is equal to fADC (= fMCLK/8). The Step
Size is stored in the Scanning Step Size configuration register
as a 14 bit value. During normal operation, the stepper motor is
advanced 1 microstep every Step Size pixel periods. The LPI can
be calculated as follows:
StepSize
LPI = 4FSPI -----------------------------------pixels/line ⋅ X
Where C = 1 for “1 Channel Grayscale”, 3 for all other modes,
Data_Pixels = Data Pixels End (registers 24, 25) - Data Pixels
Start (registers 22, 23)
HDPI_Divider = Horizontal DPI divider = 1, 1.5, 2, 3, 4, 6, 8, or 12
B = Bits per Pixel = 16 (14 bit mode), 8, 4, 2, or 1
Register 4E value = Pause Threshold (kB)/2 (256k x 16 DRAM)
or Pause Threshold (kB)/8 (1M x 16 DRAM)
When the Pause Threshold is reached the buffer sends a command to the stepper motor controller to stop scanning. The
remainder of the line being processed will continue being processed and be sent to the buffer. If the Lines To Process After
Pause Scan Signal register (register 54) is greater than 0, then
room for these additional lines needs to be added into the Pause
Threshold value calculation.
Where FSPI = the number of full steps required to move the
image one inch, pixels/line is the number of pixel periods it takes
to scan one horizontal line (equivalent to the value stored in the
Line End registers), StepSize is the number of pixel periods/microstep, and X = 3 for line rate and 1 for pixel rate modes.
Note that the scanner software on the host PC must set a Pause
Threshold value low enough to ensure that any data that comes
after a pause request (the rest of the current line and any subsequent lines if register 54 bits 0-2 are greater than 0) will fit into the
DRAM buffer. If the Pause Threshold is set too high, the Line
Buffer may overflow, creating discontinuities in the scanned
image.
Whenever the stepper motor has been moving and then comes to
a stop, the LM9831 waits for the time specified in the Hold Current Timeout register and then de-asserts the A, B, A, and B outputs to cut power to the motor. When the stepper motor is not
scanning or fast-feeding (Command = 00), A, B, A, and B are deasserted in all stepper modes.
After a pause, the buffer will continue to transmit data to the PC
until it hits the Resume Threshold limit (register 4F), which is also
programmable in 2 kbyte (256k x 16 bit DRAM) or 8kbyte (1M x
16 bit DRAM) increments between 0 and 255. When the Resume
Threshold is reached, the Line Buffer sends the motor controller a
command to resume.
There are two modes of stepper motor operation: fullstepping and
microstepping.
4.1 Full Step Mode
In Full Step Mode the output is a pulse stream, as shown in Figure 8. The amplitude of the pulses is controlled by the output of
4.0 Stepper Motor Controller
The stepper motor controller sends a series of pulses to the stepper motor to move the paper past the sensor (sheetfed) or the
sensor past the paper (flatbed). The speed at which the paper
moves relative to the sensor, combined with the integration time
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noise generated by the driver transistor turning on.
the 2 bit DAC, shown in Figure 9.
Scan Mode
Starting from
a dead stop
Scanning
Stopped
DAC Voltage
DAC
0.465V for number of steps specified
in Kickstart Steps register (0-7). If
register is 0 there is no Kickstart
current-movement begins at 0.325V.
0.325V
0.110V for number of steps specified
in Hold Current Timeout register (1 31), 0V after time out.
A
A
DAC
Figure 9: Full Step Current Control
B
4.2 Microstep Mode
B
Microstepping is a technique of driving the stepper motor with a
staircase approximation of a sine wave, as shown in Figure 10.
This technique maximizes the torque of a given motor, resulting in
a higher maximum speed. In addition, it increases the resolution
of the stepper motor. If a stepper motor moves 3.6° per full step,
microstepping can create positions inside the 3.6°: 1.8°, 0.9°, or
0.45°, for example. This increases the maximum vertical resolution of the scanner. Microstepping also results in quieter motor
movement.
Figure 11: Stepper Motor Waveform - LM9831 Signals
Figure 12 shows the LM9831’s DAC voltages. The peak current
through the stepper motor winding will be 0.465V/RSENSE. The
table index is incremented every microstep (StepSize pixel periods).
A
A
1 microstep
B
Table
Index
A (B)
A (B)
0
1
2
3
4
-0
-1
-2
-3
-4
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
DAC
Voltage
N/A
0.175V
0.325V
0.425V
0.465V
N/A
0.175V
0.325V
0.425V
0.465V
Figure 12: Microstepping Current Control
4.3 Pause Behavior - Non-Reversing Mode
B
When the Full Steps to Reverse When Buffer is Full register is
0, the stepper motor simply stops moving when the Pause signal
is received, as shown in Figure 13. The line of data currently
being processed (section “a” in Figure 13) will continue to be processed and stored in DRAM. Additional lines may be digitized
and stored as well, depending on the number programmed in the
Lines to Process After Pause Scan Signal register (Figure 14).
This value is different for different scanner designs and should be
empirically set to the value that minimizes the spatial distortion
created by the motor slowing down and stopping.
Figure 10: Bipolar Microstepping Waveform
The amplitude of the microstepped sine wave is controlled by the
output of the stepper motor DAC (Figure 11). The current in the
stepper motor winding is measured as a voltage across the sense
resistor, and the transistor drive signals are pulse width modulated (PWM) to force the average current through the winding
equal to VDAC/RSENSE. Register 56 controls the frequency of the
PWM, and Register 57 controls the minimum time the driver is on
every period. Register 57 should be set as short as possible, the
driver only needs to be on long enough to mask any transient
a
b
c
d
TR
Microstep
Pulse
Pause
Scanning
Signal
Figure 13: Stepper Motor Stopping
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Value
0
1
2
...
7
a
Additional Lines to Store in DRAM
0(a only)
1 (a and b)
2 (a, b and c)
...
7
Microstep Pulse
(if motor had not
paused)
When the Resume Scan signal is received, the stepper motor
controller waits the appropriate number of pixel periods after the
next TR pulse and then starts stepping again at the normal rate.
The first new line transmitted is determined by the Lines to Discard After Resume Scan Signal register. The discard value
must be the same as the value in the Lines to Process After
Pause Scan Signal register.
b
c
d
Resume
Scanning
Signal
Value
e
Pause
Scanning
Signal
Stopping, reversing, and resuming forward motion all follow the
curve programmed in the Acceleration Profile configuration register. There are 3 segments (Stopped, 25%, and 50%), and the
number in each register indicates the number of full steps to stay
at that acceleration. A value of 0 indicates that that segment is to
be skipped. For example, a value of 0 in all three registers would
mean that the motor would instantly reverse when the buffer is
full, then instantly stop after going back the specified number of
lines.
Speed
Register
Figure 16: Stepper Motor Resuming
0
1
2
...
7
d
Figure 17: Reversing - The Goal
TR
Microstep
Pulse
c
Microstep
Pulse
Figure 14: Lines to Process after Pause Scan Signal Register
a
b
TR
Stopped
(x = 0 to 3)
First Line to Transmit After Pause
25%
(y = 0 to 3)
b
c
d
...
i
50%
(z = 0 to 3)
Figure 15: Lines to Discard After Resume Scan Signal
Register
DAC output
x = number of full step clocks to wait
before reversing motor.
y = number of full steps at 25% of final
speed. Full step period = 4 full step
clocks.
z = number of full steps at 50% of final
speed. Full step period = 2 full step
clocks.
Figure 18: Acceleration Profile Settings
4.4 Pause Behavior - Reversing Mode
This acceleration profile is used any time the motor is started,
stopped, or reversed.
If the Full Steps to Reverse When Buffer is Full register is >0,
then the Reversing Mode is enabled.
The acceleration profile for stopping, reversing, stopping, and
going forward again is this:
The Reversing Mode eliminates spatial distortion due to the
pausing of a scan. When the Pause Scan signal is received, the
line currently being processed is completed and stored in RAM
(line “b” in Figure 17). When the scan resumes, ideally the
LM9831 would send out lines “c” and after under the exact same
speed and positional conditions the scanner was in before the
scan paused (as indicated by the dotted line in Figure 17).
• Full speed forward (1 microstep = #pixels in Scanning Step
Size register) until the Pause Scanning signal is received.
• 50% speed forward for z full steps (1 microstep = 2* #pixels in
Scanning Step Size register)
• 25% speed forward for y full steps (1 microstep = 4*#pixels in
Scanning Step Size register)
• Stopped for x full steps (1 microstep = #pixels in Scanning
Step Size register).
When the Pause Scan signal is received, the LM9831 processes
the remainder of the line currently being read from the CCD (line
b), and stores the offset (in pixel periods) between the last TR
pulse and the last step. It then stops, reverses, stops, and waits
for the Resume Scan signal. Once Resume Scan is asserted, the
motor controller waits for the previously stored number of pixels
periods, then starts moving forward again, maintaining the same
phase relationship between the TR pulse and the stepper motor
control signals. The result is as if the stepper motor had never
paused.
• 25% speed backward for y full steps (1 microstep = 4*#pixels in
Scanning Step Size register)
• 50% speed backward for z full steps (1 microstep = 2* #pixels in
Scanning Step Size register)
• Full speed backward (1 microstep = #pixels in Scanning Step
Size register) for number of microsteps in the Steps to
Reverse register
• 50% speed backward for z full steps (1 microstep = 2* #pixels in
Scanning Step Size register)
• 25% speed backward for y full steps (1 microstep = 4*#pixels in
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light to the image being scanned. This source may be white (typically a fluorescent lamp), or red, green, and/or blue LEDs. There
are four illumination modes in the LM9831:
Scanning Step Size register)
• Paused until a Resume Scan signal is received, whichever
event happens first. During the hold current timeout period, the
DAC output is held at 0.110V (the hold current) for FullStep
mode, or the DAC outputs are held as they were prior to stopping for the microstep mode. After the hold current timeout
period, output drivers A, B, A, and B will be deasserted.
Illumination
Mode
0
• Wait for Resume Scan signal
• Wait for correct number of pixel periods to resynchronize stepper motor with sensor timing.
1
• 25% speed forward for y full steps (1 microstep = 4*#pixels in
Scanning Step Size register)
• 50% speed forward for z full steps (1 microstep = 2* #pixels in
Scanning Step Size register).
2
• Full speed forward (1 microstep = #pixels in Scanning Step
Size register), with TR pulses synchronized to same the position on image that they would have been had scanner not
stopped.
3
The Lines to Process After Pause Scan Signal/Lines to Discard After Resume Scan Signal register is not used in reversing
mode.
Description
LAMPR, LAMPG, LAMPB outputs = 0.
This is the power-on default.
Scanning with white light:
LAMPR and LAMPB controlled by
LAMP On/Off pointers in horizontal
pixel counter (as in Mode 3),
LAMPG is a PWM pulse stream
Scanning with 3 LEDs in color:
LAMPR turns on for Red lines
LAMPG turns on for Green lines
LAMPB turns on for Blue lines
Scanning with 3 LEDs in gray:
LAMPR turns on for all lines
LAMPG turns on for all lines
LAMPB turns on for all lines
Figure 19: Illumination Modes
In Illumination Mode 1, the lamp connected to the LAMPR pin is
controlled by the LAMPR On/Off settings in the configuration register. The LAMPB output (if used) is controlled the same way. If
the lamp is supposed to be on all the time, then the On setting
should be set to a number between 0 and the value in the Line
End register, and the Off register should be set to a number
greater than the value in the Line End register. Conversely, if the
lamp is supposed to be off all the time, then the On setting should
be set to a number greater than the value in the Line End register,
and the Off register should be set to a number between 0 and the
value in the Line End register. The LAMPG output is a PulseWidth-Modulated pulse stream whose duty cycle is controlled by
the value in the PWM register (0-4095). The duty cycle is therefore equal to the register value/4096. The PWM counter is
clocked with the 48MHz clock so the output frequency is
48MHz/4096 = 11.7kHz. This PWM output can be used to control
the brightness of a fluorescent lamp.
4.5 Fast Feed Step Size Register
When the motor is being moved quickly (Paper Feed to
End/Paper Feed to Beginning command or Steps to Skip at
Start of Scan register), the microstep period comes from this
register.
For all other motor movement, the microstep size is given in the
Scanning Step Size register.
4.6 Stepper Motor Current Control Using PWM
There is an option to use Pulse Width Modulation of the current in
the stepper motor to increase high speed torque, optimize efficiency, and allow use of a lower current, less expensive motor.
Precisely controlling the current in the motor provides several
benefits. In Full Step Mode, the motor can start moving faster and
overcome inertia by increasing the current to the motor to 100%
when it is starting from a dead stop. After a programmable number of steps, the inertia is overcome and the current can be
reduced to 70% to reduce heat in the stepper motor (allowing a
less expensive motor to be used). When stopping the stepper
motor, the current is increased to 100% for a short time to overcome the forward momentum, then the motor is held in position
with a low-level standby current of 25%. If the motor is motionless
for more than the Hold Current Timeout period, the current goes
to 0%.
TR
LAMPR (LAMPR On < Line End, LAMPR Off > Line End
LAMPG
LAMPB (LAMPB On > Line End, LAMPB Off < Line End
In microstepping mode, the PWM is used to approximate a sine
wave as shown in Figure 10.
Figure 20: Illumination Mode 1
The current control is accomplished by measuring the average
motor winding current through a sense resistor to ground, comparing it to a reference voltage, and PWMing the motor driver
transistor(s) to force the current to be equal to the reference current. See the Stepper Motor Current Controller Block Diagram
at the end of this document.
In Illumination Mode 2 (which is typically used in conjunction with
1 Channel Color), the LAMPR, LAMPG, and LAMPB outputs are
cycled through sequentially, one line at a time. An internal color
counter keeps track of the color of the line to be integrated, and
takes that color’s LAMP output high when the pixel counter
reaches the value stored in that color’s LAMP On register (Configuration Registers 2C-37). If the On value is greater than the
value in the Line End register, then that lamp never turns on. That
color’s LAMP output goes low when the pixel counter reaches
that color’s Off value. If the Off value is greater than the value in
the Line End register, then the pixel counter will never reach the
5.0 Scanner Support Functions
5.1 Illumination Control Block
Scanner systems require an illumination source to supply the
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18 for more details on the timing of specific signals. The LM9831
features:
Off value and the lamp will always stay on. Illumination Mode 2
timing is shown in Figure 21, and in slightly more detail in Figure
33.
• Independent control over the polarity (inverting or noninverting)
of the input stage to accommodate CIS or CDS signals.
TR
• Full timing control of the CIS and CDS sample points. Reference and signal sample points can be independently adjusted.
Note that the absolute time between reference sample and signal sample must be 2 MCLKs or greater, whether CDS is on or
off.
LAMPR
LAMPG
• Ability to turn off CDS. When CDS is on, traditional CDS is performed. When CDS is off, the signal is sampled at the Sample
Signal point, but the internal reference is used for the Sample
Reference voltage (not a point on the input signal itself).
LAMPB
Figure 21: Illumination Mode 2
• The CP1 output supplies the CP pulse needed on some popular Toshiba CCDs. This looks and acts just like another, independent RS pulse.
Illumination Mode 3 is similar to Illumination Mode 2, except that
the LAMP outputs for all three colors are turned on and off every
line. Illumination Mode 3 timing is shown in Figures 22 and 23.
The Lamp On and Lamp Off settings work the same as in Mode 2
to control the on and off points for the different lamp signals. In
systems with a limited power budget, care should be taken to prevent turning multiple lamps on at the same time. This can also be
important for CIS sensors that limit the maximum combined current of the three lamps.
• A CP2 output is another independent pixel rate pulse that (if
needed) can be programmed to supply an additional clock.
• CCD clock signals RS, CP1, CP2 are reset when Line Ends
• The internal Clamp signal is reset with Optical Black Pixels
End.
TR
• TR1 and TR2 pulse widths are always the same width, as
determined by Register 0E.
LAMPR
• The TR-Ø1 guardband may be equal to 0, causing TR and Ø1
to go high simultaneously and low simultaneously (Figure 24).
This is a requirement of some Canon CIS sensors.
TR
LAMPG
ø1
LAMPB
TR Pulse same as first clock pulse
Figure 22: Illumination Mode 3 (grayscale)
Figure 24: TR-Ø1Guardband Can Be Equal To 0
• CIS TR1 Timing Mode 1. In this mode the TR1 pulse is exactly
one Ø clock long, occurring on the rising edge of Ø1. The TR1
pulse width and guardband settings are ignored. For Dyna CIS.
TR
TR1
LAMPR (LAMPR On > Line End, LAMPR Off < Line End
Ø1
LAMPG
RS
LAMPB (LAMPB On > Line End, LAMPB Off < Line End
Previous
Line
Figure 23: Illumination Mode 3 (green only)
Transfer
Phase
Dummy
Pixels
Figure 25: CIS TR1 Timing Mode 1
These modes are in operation whenever the chip is powered on
and not in standby mode. For example, the LAMP outputs in Figures 21 and 22 keep pulsing whether the LM9831 is in the Idle,
Paper Feed, or Scanning states. This eliminates light amplitude
variations due to the lamp/LEDs warm-up characteristics. Since
the LAMP pulses are synchronized to the TR pulse, which is
determined by the horizontal pixel counter, this means that the
pixel counter is constantly running, and any new scans can only
be started by waiting for the next new line (the next Red line in
the case of Illumination Mode 2).
• CIS TR1 Timing Mode 2. In this mode the TR pulse is again
equal to 1 Ø period, but now it is centered around Ø1. The TR
pulse width and guardband settings are ignored. For Canon
CIS.
tø1 /4
TR1
tø1/4
tø1/4
ø1
tø1
ø1 inside TR1 pulse
5.2 CCD/CIS Control Block
Figure 26: CIS TR1 Timing Mode 2
This function generates the clock signals necessary to control a
CCD or CIS sensor. Refer to the descriptions for registers 0B to
• To prevent sensor saturation, the LM9831 is always clocking
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the CCD/CIS, except when it is in Reset or Standby (Register 7
bit 2 or 3 = 1).
Line-Rate
Multiplexing
Red Channel
• There is a bit for Fake Optical Black Pixels (register 19, bit 2).
This is used with Dyna CIS sensors. In this mode, the RS output pulses once inside the TR1 pulse, then is held high until the
end of the optical black pixels. The TR1 pulse is extended until
the trailing edge of the first RS pulse. This mode works for TR1
only, under all TR1 settings (normal and CIS TR1 Timing
modes 1 and 2).
C
C
D
Green Channel
ADC
Blue Channel
ADC Out LIne 1: RRRRRRRRRRRRRRR...
ADC Out LIne 2: GGGGGGGGGGGGGG...
ADC Out LIne 3: BBBBBBBBBBBBBBBBB...
ADC Out LIne 4: RRRRRRRRRRRRRRR...
TR1
Figure 29: 3 Channel Line Rate Mode
RS
Trailing edge of
first RS pulse
tINT (RED)
End of Optical
Black Pixels
TR RED
Figure 27: Fake Optical Black Pixels
tINT (GREEN)
TR GREEN
5.3 AFE Operation
The LM9831 supports the following operation modes, controlled
by registers 26 and 27:
tINT (BLUE)
• 3 Channel Pixel Rate Mode. In this mode all three channels are
converted with the multiplexer in front of the ADC switching at
the ADC conversion rate, producing interleaved RGB data that
is transferred to RAM. The ADC runs at MCLK/8, each channel’s pixel rate is MCLK/24. Each color has its own offset and
gain coefficients. This mode typically uses Illumination Mode 1.
Red Channel
C
C
D
Green Channel
TR BLUE
Multiplexer
Channel
Green
Blue
Red
Green
Figure 30: 3 Channel Line Rate TR Pulse Timing
In the 3 Channel Line Rate Mode three TR pulses are generated.
TRRED is the TR1 output, TRGREEN is the TR2 output, and
TRBLUE is the CP2 output. In this mode TR pulses for a particular
color can be “skipped”, increasing the integration time for that
color. In the example shown in Figure 30, the red channel sees 2
times the integration time of the green channel, and the blue
channel sees 3 times the integration time of the green channel.
Each channel can be independently programmed to drop 0, 1, or
2 TR pulses.
Pixel-Rate
Multiplexing
ADC
Blue Channel
ADC Out LIne 1:
ADC Out LIne 2:
ADC Out LIne 3:
ADC Out LIne 4:
Red
RGBRGBRGBRGBRGB...
RGBRGBRGBRGBRGB...
RGBRGBRGBRGBRGB...
RGBRGBRGBRGBRGB...
1
Figure 28: 3 Channel Pixel Rate Mode
2
1
2
Ø1
• 3 Channel Line Rate Mode. In this mode all three channels are
converted with the multiplexer in front of the ADC switching at
the line rate, producing a line of Red data, followed by a line of
Green data, followed by a line of Blue data, etc. that is transferred to RAM. The selected channel and the ADC both run at
MCLK/8. Each color has its own offset and gain coefficients.
This mode typically uses Illumination Mode 1.
TR RED
TR GREEN
TR BLUE
Figure 31: 3 Channel Line Rate Mode with 2 TR
Pulse Positions
Each color’s TR pulse can be programmed to occur in position 1
(inside Ø1 high) or position 2 (inside Ø1 low), as shown in Figure
31.
• 1 Channel Grayscale: Uses the selected channel’s offset and
gain coefficients for all lines. 1 Channel Grayscale is used to
scan a grayscale images. This mode typically uses Illumination
Mode 1 when used with a 3 Channel Color sensor, or Illumination Mode 3 when used with a 1 Channel sensor.
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Alliance: AS4C1M16E5-50 (5V), AS4LC1M16E5-50 (3V)
TR
Micron: MT4LC1M16E5DJ-5, MT4LC1M16E5TG-5 (3V)
There are 2 scan modes: 8 bit and 16 bit. The 8 bit mode is used
for normal scanning to application software to generate 8 bit gray
or 24 bit color images. The 16 bit mode is used for calibration.
R LED
1
G LED
2
3
4
5
6
48MHz
7
B LED
COEF.
DATA
SC
SC
SC
SC = selected channel (=green in this example)
Figure 32: 1 Channel Grayscale
RO
RS
RG
WP8
RP
RF
16 bit
RO
RS
RP
WP16
RP
RF
875ns
• 1 Channel Color: This mode uses a sensor tied to the Blue OS
input only. Illumination is switched in RGBRGB pattern at the
line rate. Each color has own digital offset and gain coefficients
as well as static Gain and Offset data. Note that there is a one
line delay between when a line is exposed to a color and when
pixels of that color are clocked out of the sensor. For example,
the Green LEDs should be on while you are clocking out Red
pixels. This mode uses Illumination Mode 2.
RO: Offset Coefficient read
RS: Shading (Gain) Coefficient read
RG: Gamma Table read
WP8: 8 bit pixel write (write 2 pixels as 16 bits
every other cycle)
WP16: 16 bit pixel write
RP: read pixel
RF: refresh
Figure 34: DRAM Timing per Pixel
TR
The ADC always converts at 1/8 of the MCLK frequency (fADC =
fMCLK/8). The datarate to the DRAM is the ADC rate divided by
the HDPI divider setting (fDRAM = f ADC/HDPI_DIVIDER. The offset correction data and the gain correction coefficient data are
provided at the DRAM datarate.
R LED
G LED
The DRAM timing is shown in Figure 34. All the read and write
operations shown in Figure 34 must be done for every pixel written to DRAM. That limits the pixel datarate to the DRAM to
1/875ns = 1.14MHz. The following equation must be adhered to
in order to limit the DRAM datarate to 1MHz or slower:
B LED
COEF.
DATA
8 bit
SC
B
R
G
B
(MCLK div)(HDPI divider)(Int Time Adj) >= 6
Int Time Adj refers to the value in register 19, and will be discussed in a later section. If register 19 = 0, then the value of Int
Time Adj = 1 (for the purpose of this equation).
Figure 33: 1 Channel Color
5.4 External DRAM Interface
The LM9831 supports two external DRAM sizes: 256k x 16 and
1M x 16. The DRAM is used for line buffering, gain (shading)
coefficient data, offset coefficient data, and gamma correction.
48kwords (16k pixels * 3 colors) are used for gain coefficients,
and another 48kwords (16k pixels * 3 colors) for the offset coefficients. Gamma correction consumes 12kwords (4k x 3 colors).
The remaining RAM (148kwords = 296kB for 256k DRAM, or
916kwords = 1,832kB for 1M DRAM) is used for the circular
image data buffer. The 1M size does not necessarily provide a
performance advantage (except perhaps when the USB bus is
heavily loaded and I/O is very slow) - the option is there to provide an alternative to the 256k in case of a supply shortage of
256k DRAMs.
16kwords Red Offset
16kwords Green Offset
16kwords Blue Offset
16kwords Red Shading
16kwords Green Shading
16kwords Blue Shading
4kwords Red Gamma
4kwords Green Gamma
4kwords Blue Gamma
Pixel Data
148
kwords (256k and 1M)
768
Pixel Data (1M)
kwords
8 bit Datamode
16kwords
16kwords
16kwords
16kwords
16kwords
16kwords
Red Offset
Green Offset
Blue Offset
Red Shading
Green Shading
Blue Shading
Pixel Data
160
kwords (256k and 1M)
768
Pixel Data (1M)
kwords
16 bit Datamode
Figure 35: Memory Map of External DRAM
Because the LM9831 does not use any EDO or Fast Page Mode
features, it can work with either EDO or Fast Page Mode DRAM.
The LM9831 should work with most 50-60ns 256k x 16 or 1Mx16
DRAM. Examples:
5.5 PAPER SENSE and MISC I/O
These 8 pins are used for home and paper sensing, LED displays, user start buttons, etc.
Samsung: KM416C1000C/C-L-5, KM416C1200C/C-L-5,
KM416C1004C/C-L-5, KM416C1204C/C-L-5 (5V)
Two pins are dedicated inputs: PAPER SENSE 1 and PAPER
SENSE 2. The other six pins, MISC I/O 1-6, can be configured as
inputs or outputs.
KM416V1000C/C-L-5, KM416V1200C/C-L-5, KM416V1004C/CL-5, KM416V1204C/C-L-5 (3V)
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multiplexed into only 3 MISC I/O lines. Figure 37 shows how to
decode the data in register 2 to determine which button was
pressed. This multiplexing technique can easily be scaled to
allow for more or less buttons with the minimum number of MISC
I/O lines.
.
The state of each pin, True or False (1 or 0), is reflected in the
Status Register.
These are the configurable aspects of these I/O pins:
• Input or Output function. If this bit is set to a 0, the pin is configured as an input. If this bit is set to a 1 the pin is configured as
an output.
+5V
• The polarity of the input. If this bit is set to a 1 (Active High), a
high level on that input pin will produce a True reading (1) in the
Status Register. If this bit is set to a 0 (Active Low), a low level
on that input pin will produce a True reading (1) in the Status
Register.
22k 22k 22k
MISC I/O 1
MISC I/O 2
MISC I/O 3
• Level or Edge Sensitive. If this bit is set to 0 (Level Sensitive),
the Status Register will reflect the current state at that sensor
input pin. If this bit is set to 1 (Edge Sensitive), the Status Register for that input will be True (1) if there were any False to
True transitions at that sensor input pin since the last time the
Status Register was read. Reading the status register clears
the state of all the edge sensitive inputs to False (0).
A
B
C
D
E
F
G
Figure 36: Remote Wakeup With Up To 7 Switches
• PAPER SENSE 1 can be programmed to stop the scan (by
clearing the Scanning bit) when its state (as reflected in the Status Register) changes from False to True. This is useful in flatbeds to prevent the motor from trying to step past the limits of
travel of the system. In sheetfed systems, PAPER SENSE 1
can be used to detect whether or not the user has inserted a
document to be scanned.
• PAPER SENSE 2 can be programmed to stop the scan (by
clearing the Scanning bit) and set its bit in the Status Register
to True a programmable number of lines after its input pin
changes state from False to True. In sheetfed scanners this is
useful if the PAPER SENSE is located before the scanner array,
where the sensor will change states before all of the paper has
been scanned. For flatbed scanners this sensor can be used to
detect the home position.
Switch
MISC I/O 1
MISC I/O 2
MISC I/O 3
A
B
C
D
E
F
G
0
0
0
1
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1
1
0
Figure 37: Truth Table for Remote Wakeup With Up To
7 Switches
• If they are configured as outputs, the MISC I/O 1-6 pins can
have their outputs set to +5V or 0V by writing a 1 or a 0 to the
appropriate bit.
5.6 The Brains
This is the master control section that keeps track of the position
of the CCD pixel going through the analog front end, the color of
that line of CCDs (for single output CCD illumination control), the
stepper motor, and all other system coordination.
The default state of the MISC I/O pins is described in detail in the
Register Listing section. The Misc I/O pins revert to their default
states on power-on, after entering USB Suspend, or when the
RESET pin is pulsed high. A soft reset (register 07) does not
reset the MISC I/O pins. The default states of the MISC I/O pins
are:
6.0 Communicating with the LM9831
Everything on the LM9831 (configuration settings, image data,
coefficient data, and gamma tables) is accessed through the
Configuration Register. Configuration Register I/O is done
through two steps. The first step is to write the address (0 through
7F) of the configuration register to be read from or written to. The
second access is the data operation (a read or a write) for that
address. The address only needs to be written once. After an
address is written, any number of reads and/or writes may be
made to that address.
• MISC I/O 1: Input, edge sensitive, high-to-low transition sets bit
2 of register 2.
• MISC I/O 2: Input, edge sensitive, high-to-low transition sets bit
3 of register 2.
• MISC I/O 3: Input, edge sensitive, high-to-low transition sets bit
4 of register 2.
• MISC I/O 4: Output, voltage on MISC I/O 4 pin = VD.
Registers 0, 1, and 2 are read-only registers. Writing to these
addresses may affect various counters inside the LM9831 and
should therefore be avoided. Bits 4 of register 3 is also read only,
however it is OK to write to register 3. All of the remaining configuration registers can be read from and written to using this protocol.
• MISC I/O 5: Output, voltage on MISC I/O 5 pin = VD.
• MISC I/O 6: Output, voltage on MISC I/O 6 pin = 0V.
5.5.1 Adding Function Buttons
Many scanners today feature multiple buttons to select scan,
copy, fax, email, etc. functions. The LM9831’s MISC I/O pins can
be used for these functions. To free up MISC I/O inputs for other
functions, or if more than 6 buttons are required, you can multiplex the buttons together. Figure 36 shows how 7 buttons can be
6.1 The DataPort: Reading and Writing to Gamma, Offset,
and Gain Memory
Because the gamma table and the shading and offset correction
blocks of RAM are very large, the LM9831 uses an indexed
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method of reading and writing them, called the DataPort. Four
addresses in the Configuration Register are used to implement
this feature, as shown in Figure 38.
Configuration
Register
Address
Name
DataPort
Target/
Color
DataPort
Address
(MSB)
DataPort
Address
(LSB)
DataPort
3
4
5
6
6.1.2 DataPort Address
This 14 bit register (at Configuration Register addresses 4 and 5)
determines what the starting address is for the read/write operation. This address is automatically incremented after every 2 byte
word read/write operation to the actual DataPort. For the gamma
table the range is 0 to 4093. For the Gain and Offset Coefficients
this range is 0 (corresponding the first valid pixel as programmed
in the Valid Pixels Start register) to 16383 (the maximum number
of image pixels). If reads or writes continue past 4093 or 16383,
the DataPort address counter wraps back around to 0 and continues counting.
Bits
b3- b0
b13 - b8
6.1.3 DataPort
The DataPort is the 8 bit register (Configuration Register address
06) where the data is sequentially read from or written to. The formats for Offset, Gain, and Gamma data are shown in Figures 41,
42, and 43.
b7 - b0
b7 - b0
Figure 38: DataPort
7
The DataPort allows the user to select a memory block (gamma,
gain coefficient, or offset coefficient) and color (red, green, or
blue) to be read from or written to, by writing to Configuration
Register Address 3.
6
5
4
b13 b12 b11 b10
b5 b4 b3 b2
3
2
1
0
Type
b9
b1
b8
b0
b7
0
b6
0
First Byte
Second Byte
Figure 41: DataPort Offset Format
The starting address of that block (usually 0) is written into the
DataPort Address register (at Configuration Register Addresses
4 and 5). Bit D6 of register 4 should also be set to a 0 or a 1 to
indicate whether the DataPort will be read from (D6 = 1) or written
to (D6 = 0) in subsequent operations. This is required so the
LM9831 can prefetch the data for faster access. The DataPort
Address is automatically incremented after every word (2 bytes)
of Offset, Shading, or Gamma data is read/written.
7
6
5
4
3
2
b15 b14 b13 b12 b11 b10
b7 b6 b5 b4 b3 b2
1
0
Type
b9
b1
b8
b0
First Byte
Second Byte
Figure 42: DataPort Gain Format
Once the memory block, color, and starting address are written, a
series of reads or writes to the DataPort will read from or write to
the selected memory block at maximum speed.
Registers 4 and 5 should always be written to after Register 3 has
been changed.
Reading and writing the DataPort should only be done when the
LM9831 is not scanning (Register 07 = 0).
7
6
5
4
0
b7
0
b6
0
b5
0
b4
3
2
b11 b10
b3 b2
1
0
Type
b9
b1
b8
b0
First Byte
Second Byte
Figure 43: DataPort Gamma Format
6.1.1 DataPort Type and Color
7.0 The USB Interface
These 3 bits determine which memory block (gamma, gain, or offset coefficients, Figure 39) and which color of that memory block
(red, green, or blue, Figure 40) is to be read from or written to.
The LM9831 uses the USB (Universal Serial Bus) interface.
Refer to the LM9831 software package for details on USB communication.
7
6
5
4
3
2
1
0
Type
-
-
-
-
-
-
0
0
1
1
0
1
0
1
Offset
Gain
Gamma
Undefined
7.1 The USB Pins
Data is received and transmitted through the D+ and D- pins.
These are 3V differential signals. Figure 44 shows the recommended circuitry between the LM9831’s D+ and D- pins and the
scanner’s USB connector.
Figure 39: DataPort Target Pointer
7
6
5
4
3
2
1
0
Color
-
-
-
-
0
0
1
1
0
1
0
1
-
-
Red
Green
Blue
Undefined
Figure 40: DataPort Color Pointer
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with the Red data representing line m+x, the Green data representing line m, and the Blue data representing line m-x. “x” is the
separation between lines, which depends on the physical distance between the R, G, and B sensors and the rate at which the
sensor is moving over the image.
LM9831 VREGULATOR
(pin82)
∗Optional - forces LM9831 into
suspend mode if USB cable is
1.5k
not attached to scanner.
22Ω
LM9831 D+
D+ USB
(pin 84)
Connector
22Ω
LM9831 DD- USB
(pin 83)
Connector
10pF 10pF
The length of a line of image data sent to the PC depends on several factors:
• The range of pixels to be scanned (Data Pixels): Data Pixels =
(Data Pixels End - Data Pixels Start),
• The horizontal resolution set in the configuration register
(HDPI_Divider)
1MΩ∗
• The number of bits per pixel (1, 2, 4, or 8, called B), and
• The color mode: pixel rate (C=3) or line rate (C=1).
Figure 44: Recommended USB Component Values
Data Pixels 
 INT  ----------------------------------
 HDPI_Divider ⋅ C ⋅ B

Bytes/Line = 2 ⋅ INT  ------------------------------------------------------------------------
16




8.0 Scanning
8.1 Start Scanning - Initiating an Image Scan
The scanner software on the host must strip the 2 byte status
word from the end of each line before reconstructing the image.
An image scan is initiated by writing a Scan command to Register
07. The LM9831 will move the sensor forward the number of fullsteps specified in registers 4A/4B and begin scanning. Scanning
ends when the host writes a new command to the command register (Idle, Paper Feed to Start or Paper Feed to End) or when
PAPER SENSE 1 or PAPER SENSE 2 changes state (if programmed to do so).
8.2.1 Reconstructing 14 bit Image Data Received By the PC
In the 14 bit Data Mode the Gamma Correction and Pixel Packing
stages are bypassed. Each pixel comes out as 2 bytes instead of
1, doubling the amount of memory needed to store one line. The
data format is shown in Figure 45. This mode is otherwise identical to the 8 bit mode. The number of bytes per line in 14 bit mode
is given in this equation:
The line buffer is reset when the Scanning bit is SET, not when it
is cleared. The host can continue to read stored data out of the
line buffer after a scan has stopped.
Data Pixels
Bytes/Line = 2 ⋅ INT ( ------------------------------------ ) ⋅ C
HDPI_Divider
Pixel data is read from configuration register address 00. Registers at other addresses can be read during a scan (to read the
LM9831’s status registers, abort the scan, etc.).
The 14 bit mode is used to acquire 14 bit data for accurate gain
and offset calibration.
If for some reason you want to pause the scan for some length of
time and resume later, do NOT stop the scan (return to Idle). Simply stop reading pixel data. When the buffer fills up, the LM9831
will automatically stop scanning and turn off power to the stepper
motor (when the delay goes beyond the time specified in the Hold
Current Timeout register).
7
6
5
4
b13 b12 b11 b10
b5 b4 b3 b2
3
2
1
0
Type
b9
b1
b8
b0
b7
0
b6
0
First Byte
Second Byte
Figure 45: 14 bit Data Format
The last 2 bytes of every line is a status word indicating how
much data is in the image buffer at the time the status word was
written. This information is in the 8 LSBs of the status word, and
has the same format as Register 01.
8.3 High Speed Forward
When register 07 is set to a 1, the LM9831 moves the motor forward at maximum speed (determined by the fast feed stepsize,
registers 48 and 49) until a 0 is written to register 07 or either one
of the PAPER SENSE inputs becomes True (if that sensor has
been properly programmed to interrupt scanner movement).
PAPER SENSE 2 can be used to cause a delayed stop. If the
FullSteps to Scan after PAPER SENSE 2 trips register is
greater than 0, motor movement will continue for the programmed number of full steps. This can be used to eject paper in
sheetfed scanners.
8.2 Reconstructing 8 bit Image Data Received By the PC
When reconstructing an image from the stream of data received
from the LM9831, it is useful to know the format of the data. The
LM9831 does not perform deinterleaving on the pixel data, it
comes out exactly as the sensor sends it. Deinterleaving must be
performed on the host PC.
For a single output CCD/CIS that outputs one line of data with
colors alternating at the line rate, the output format is:
The LM9831 also features a Programmed High Speed Forward
command. This is identical to the High Speed Forward function,
except that it will automatically stop moving once the motor has
moved the number of lines specified in registers 4A and 4B.
R1, R 2, R 3, R4,..., Rn-2, Rn-1, Rn (line m)
G1, G2, G3, G4,..., Gn-2, Gn-1 , Gn (line m + 1)
B1, B2, B3, B4,..., Bn-2, Bn-1, Bn (line m + 2)
For a triple output CCD/CIS that outputs 3 lines of data (each x
pixels apart in the vertical direction) with colors alternating at the
pixel rate, the output would be:
8.4 High Speed Reverse
When register 07 is set to a 2, the LM9831 moves the motor
backwards at maximum speed (determined by the fast feed stepsize, registers 48 and 49) until a 0 is written to register 07 or
R1, G1, B1, R2, G2, B2,..., Rn-1, Gn-1, Bn-1, Rn, Gn, Bn
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MCLK is used to clock the vast majority of the LM9831’s circuits.
CRYSTAL OUT is directly used in the USB I/O section, DRAM
timing, and a few subsections where the highest possible clock
speed is required (such as the PWM pulse generator for the light
source and the stepper motors).
either one of the PAPER SENSE inputs becomes True (if that
sensor has been properly programmed to interrupt scanner
movement). The FullSteps to Scan after PAPER SENSE 2 trips
register is not used in the High Speed Reverse mode. This function is generally used to home the sensor in flatbed scanning
applications.
To use the LM9831’s crystal oscillator feature, tie the CRYSTAL/EXT CLK pin to DGND. Figure 46 shows the recommended
loading circuit and values for a 48MHz oscillator. These component values assume 10pF of stray capacitance between CRYSTAL IN and ground, and 10pF between CRYSTAL OUT and
ground, for a total CRYSTAL IN and CRYSTAL OUT loading of
15pF and 25pF.
The LM9831 also features a Programmed High Speed Reverse
command. This is identical to the High Speed Reverse function,
except that it will automatically stop moving once the motor has
moved the number of lines specified in registers 4A and 4B.
8.5 Short Example of a Scan
When laying out the crystal oscillator components, always keep
the traces as short as possible, to minimize stray capacitance
and inductive noise coupling, particularly on the CRYSTAL IN pin.
• PC configures the LM9831 by writing to the configuration registers.
• PC has the LM9831 scan a calibration image, then calculates
the calibration coefficients for the scanner.
Operation at 24MHz (24/48 = VD) is not reliable and should not
be used.
• PC transmits the calibration information to the LM9831.
To drive the LM9831 with an external 48MHz clock, tie CRYSTAL/EXT CLK (pin 54) to VD, tie CRYSTAL_IN to DGND, and
drive the TTL or CMOS-level clock signal into CRYSTAL_OUT
(pin 52).
• If a sheetfed, the PC now polls the LM9831 status registers to
see if there is any paper inserted. If a flatbed, it moves the scan
head to the home position.
• PC sets the Scanning bit in the Configuration Register.
• PC calculates the size of the image to be scanned in bytes,
then reads bulk data from register 00 of the LM9831 until it has
read the entire image. If for some reason the scan needs to be
aborted, the PC writes a 0 to register 07.
10.0 INITIALIZATION
10.1 Power On Reset (POR)
POR is generated by the ramp of the VA supply pins from 0V to
+5V. A low to high to low signal on the external RESET pin will
also generate a POR. A POR event:
• Resets the USB transceiver. All enumeration and configuration
data will be reset to its default setting.
• The oscillator will start (or continue) oscillating.
• Forces all configuration registers that have defaults (shown as
black boxes in the configuration register tables) to their default
settings (including the Reset and Standby bits). See the Reset
and Standby mode descriptions for more information.
• MISC I/O 1-3 will be configured as inputs and could generate
remote wakeup signals (after the device is initialized).
• MISC I/O 4-6 are configured as outputs.
• After all image data is read, PC writes a 0 to register 07 to stop
scan.
• If this is a flatbed scanner, the PC should now send a High
Speed Reverse command to send the sensor back to the home
position. For a sheetfeeder, it can send a High Speed Forward
command to eject the remainder of the image.
• The scanner is now in the idle state.
9.0 Master Clock Source
The timing for the entire chip comes from the CRYSTAL OUT pin.
Typically this pin is used (with the CRYSTAL IN pin) as a crystal
oscillator. The clock frequency should be 48MHz. This 48MHz
clock is divided by the MCLK divider (register 08), and the divided
output is MCLK (Master CLocK). The MCLK divider range is from
1.0 to 32.5 in steps of 0.5. A configuration register code of 0
divides the clock by 1.0, while a code of 63 divides the clock by
32.5. AT 48MHz, this provides an MCLK range of 1.48MHz to
48MHz and a corresponding ADC conversion rate of 184kHz to
6.00MHz. This divider can be used to closely match the output
data rate to the PC’s input data rate, minimizing scan time.
48MHz Third
Overtone Crystal
Ecliptek
EC-T-48.000M
10.2 Soft Reset
A Soft Reset is generated by setting bit 5 of register 07. A Soft
Reset:
• Stops most of the internal clocks inside the system to save
power.
• Does NOT stop 48MHz oscillator.
• Resets internal state machines for correct operation after
register changes.
• Stops DRAM refresh. This will corrupt all the gamma, offset,
gain values, as well as any image data, stored in the external
DRAM.
• Does NOT prevent configuration register read/writes.
10Ω
CRYSTAL OUT
CRYSTAL IN
5pF
15pF
C1
C2
10.3 Standby
The LM9831 enters the Standby mode by setting bit 4 of register
07. Standby Mode:
• Powers down the analog section to conserve power.
• Tristates the stepper motor outputs (regardless of the state of
register 45, bit4).
• Does NOT prevent configuration register read/writes.
1.2µH
300pF 24/48 = DGND
Figure 46: 48 MHz Crystal Oscillator Circuit
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When using the ITA function (ITA > 0), use this version of the
equation:
10.4 Suspend Mode: Entering
Suspend Mode is entered when the USB bus has had no activity
for 3ms. The Suspend state forces the LM9831 into a low current
idle state. Suspend Mode:
• Stops the oscillator.
• Forces all black-box highlighted configuration registers to their
default settings (including the Reset and Standby bits). See
the Reset and Standby mode descriptions for more
information.
• MISC I/O 1-3 will be configured as inputs and can be used as
remote wakeup signals.
mclk_divider ⋅ HDPI_divider ⋅ ITA ≥ 6
Use this equation to calculate the stepsize for a scan:
line_length ⋅ vertical_resolution
scan_stepsize = ----------------------------------------------------------------------------------FSPI ⋅ 4
where vertical_resolution = the desired vertical resolution of the
scan, and FSPI = the number of full steps required to move the
sensor one inch.
When using the ITA function (ITA > 0), use this version of the
equation to compensate for the ITA function:
line_length ⋅ vert_res ( ITA + 1 )
scan_stepsize = -------------------------------------------------------- ⋅ -----------------------ITA
FSPI ⋅ 4
10.5 Suspend Mode: Exiting
When the LM9831 exits Suspend Mode:
• The oscillator is restarted.
• The Reset and Standby bits are still set. The driver software is
responsible for clearing them and setting the configuration
registers again to resume operation. All configuration registers
and DRAM data should be re-written after a Suspend
sequence.
12.0 QUESTIONS AND ANSWERS
Q Where is calibration done?
A Calibration is done on the host computer.
11.0 USEFUL EQUATIONS
Q Does the LM9831 support 800dpi sensors? 400dpi? XXXdpi?
A Yes. The LM9831 will support any sensor up to a maximum of
16383 pixels x 3 colors. Available horizontal resolutions are
calculated by the optical resolution of the scanner divided by
the HDPI_divider.
The integration time (t INT) for 1 line is always:
t
INT
= pixel_period ⋅ line_length
where pixel_period is the time it takes to clock one pixel out of the
sensor (C = 3 for Pixel Rate Color, and 1 for all other modes):
13.0 GENERAL NOTES AND TROUBLESHOOTING TIPS
(mclk_divider)(HDPI_divider)(ITA) must be greater than or equal
to 6. If this condition is not met, the LM9831 will not work.
mclk_div ⋅ C ⋅ 8
pixel_period = ---------------------------------------48MHz
Make sure the gamma tables are programmed with a valid
gamma curve.
and line_length is the length of an entire line, measured in units of
pixels. Note that this includes the transfer portion of the line:
line_length = line_end
Make sure the multiplier gain coefficients are loaded and correct.
(Remember, a gain coefficient of 0 means a GAIN of x0, not x1. If
the gain coefficient = 0 the output code will always be 0.)
+ TR_time
Remember that when the LM9831 is reset (reg08 = 0x20) or in
suspend for longer than a few milliseconds (consult your DRAM
datasheet), DRAM refresh will stop and the Gamma and Coefficient data may be corrupted.
These equations apply for any ITA (Integration Time Adjust, Register 19) setting.
To maximize scanner throughput, it is desirable to generate data
at the same rate as the digital I/O to the host PC. Under some
conditions (slow digital I/O, or very high resolution scans), the
time to generate one line may be greater than the maximum integration time. In this case, the integration time may be set to an
acceptable value using the previous equations, and the time to
process a line extended using Register 19 (the ITA function).
Some of the CCD signals (RS, CP1, and CP2) can have a small
pulse when line_end occurs. Line_end resets these signals and
depending on how they are programmed to go on and off,
line_end can chop off the signal before its programmed off time.
This is not a problem because the truncation occurs at the end of
every line, after all the image data for that line has been digitized.
Registers 4 and 5 only autowrap to 0 from their highest possible
legal address. If an address higher than the highest legal address
is written, it will continue to increment from the illegal address, not
wrap to 0, and unknown operation may occur. This can not happen unless the host writes an illegal address to the dataport.
Using the ITA function, the time to process 1 line can be extended
to match the digital I/O rate required:
t
LINE
= ( 1+ ITA )t
INT
The absolute distance between reference sample and signal
sample must be 2 MCLKs or greater, whether CDS is on or off.
The maximum DRAM write pixel rate allowed is 1MHz. If you configure the LM9831 to generate data any faster then 1Mpixel/s, the
LM9831 will not function correctly. To ensure that the LM9831 is
programmed to a legal datarate, ensure that this constraint is
met:
mclk_divider ⋅ HDPI_divider
≥6
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same location and perform the same function as they did in the
LM9830, many other registers have changed. Sometimes the
address of a register changed, sometimes the location of the bits
inside a register were moved, some register settings were combined or deleted, and the size of some registers was changed.
Please compare the register listings for the LM9830 and LM9831
carefully. This is a list of registers that have changed:
The range of values for the Optical Black (registers 0F and 10),
Reset Pulse (11 and 12), CP1 pulse (13 and 14), CP2 pulse (15
and 16), Reference Sample (17), and Signal Sample (18) settings
depend on the rate of the pixel data coming from the sensor.
Mode
Pixel Rate
Registers 0F to 18
Range
Pixel Rate Modes
MCLK/24
0 - 23
Line Rate Modes
MCLK/8
0-7
Registers 1, 2, 3, 4, 7, 9, B, 19, 1A, 1B, 3E-41, 42, 43-44, 4E-4F,
51-53, 54, 5A, 5B, 5E.
14.1.2 Choosing the MCLK Divider (Register 0x08)
Always make sure line length (data pixels end - data pixels start)
is >= the horizontal divider. For example, if you are dividing by 12,
the line length must be >=12.
The datarate coming out of the Horizontal DPI Divider must be
1.1MHz or less. If it is faster than this, the LM9831 will not operate correctly. Since the maximum USB datarate is about 1MHz,
this does not impact the performance of the scanner in any way.
The Line End (registers 20 and 21) setting must be programmed
as follows relative to the Data Pixels End (registers 24 and 25)
setting:
This is the Clock Divider Rule:
Line End must be >= Data Pixels End + 20
(MCLK_divider)(HDPI_divider)(ITA) >= 6.
The Data Pixels Start (registers 22 and 23) setting must be >=the
Active Pixels Start (registers 1E and 1F) setting.
The ITA (Integration Time Adjust) refers to register 19, and will be
discussed in a later section. If register 19 = 0, then the value of
ITA = 1 for the purposes of this formula.
The correct Default Phase Difference (registers 52 and 53) must
be set for a scan to restart properly following a pause in the scanning. See the LM9831 software for information on setting the
DPD register.
If register 19 = 0, this formula means that if the HDPI_divider = 1,
the MCLK_divider must be set to divide-by-6 (reg 08 = 10 [decimal]) or higher. If the HDPI_divider = 4, the MCLK_divider must
be set to divide-by-2 (reg 08 = 2) or higher. If the HDPI_divider is
6 or larger, then the MCLK_divider can be set to divide-by-1
(reg08 = 0).
The number of fullsteps skipped at the start of a scan may be one
less than the Fullsteps to Skip at Start of Scan (registers 4A and
4B) setting.
The Scanning Step Size (registers 46 and 47) and Fast Feed
Step Size (registers 48 and 49) settings must be > 2.
See 14.2.2 Integration Time Adjustment Function for additional information.
When reverse is enabled, the LM9831 always stops on Red (line
rate color). When reverse is disabled, it will stop on any color.
The contents of register 01 is not reset by the start of a new scan,
but it is updated to the correct value after the first line has been
scanned. To reset this counter prior to starting a scan, the chip
can be briefly reset (register 7 = 0x20). Since resetting the chip
may have undesired consequences (turning the lamp off briefly,
interrupting DRAM refresh), it is also acceptable to simply wait
until register 01 starts incrementing. At that point the register 01
data will be correct.
14.1.3 Calibration
In the LM9830, calibration was always performed at the optical
resolution of the scanner. For example, if the optical resolution of
the scanner was 600dpi, then calibration was performed at
600dpi even if the scan was going to be at 300dpi or 150dpi.
To keep the speed of the LM9831 high while using slower DRAM
(instead of SRAM), the architecture of the LM9831 was changed
so that the Horizontal DPI adjust function is performed before the
pixel rate offset and shading correction, instead of after (as in the
LM9830).
Gamma and gain/offset coefficient data should be written with
reg07=0 (idle). Do not attempt to write gamma or gain/offset coefficient data when scanning (reg07=03).
14.0 PORTING SOFTWARE FOR LM9830 TO LM9831
This means that the calibration routine needs to be changed so
that register 9 is set to the desired scan resolution before calibration.
The LM9831 is similar in architecture to the LM9830. Porting a
TWAIN driver from the LM9830 to the LM9831 is relatively
straightforward if consideration is given to the following issues.
The LM9831 includes almost all the features of the LM9830, plus
several new ones. The first step is to change the LM9830 Twain
driver so that it works with the LM9831. The second step is to
take advantage of the new features of the LM9831 that will allow
you to obtain even better, faster scans than you obtained with the
LM9830.
14.1.4 Pixel Rate Offset Correction
The LM9831 now uses 14 bits for the offset correction of each
pixel. The offset correction data is shifted up to fit into the 16 bit
DRAM. For example, offset correction codes of 3, 31 and 4096
would be transmitted to the dataport as:
0003: 0000 0000 0000 1100
0031: 0000 0000 0111 1100
4096: 0100 0000 0000 0000
14.1 Porting Step 1
14.1.1 Adjust for Register Changes
While more than 50% of the registers in the LM9831 are in the
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bits in register 3. This has been fixed in the LM9831. Register 3
controls the gamma table color.
14.1.5 Pixel Rate Shading Multiplier
The shading multiplier uses all 16 bits of data.
Make sure your software takes all of these changes into account.
There is an important difference between the pixel rate shading
multiplier of the LM9830 and the LM9831. In the LM9830, if the
value for the shading multiplier was 0, the gain through the multiplier was 1V/V. The LM9830 also had 3 multiplier gain ranges: 1
to 1.5, 1 to 2.0, and 1 to 3.0 V/V.
14.2 Porting Step 2
Once your TWAIN driver is operating with the LM9831, you can
start taking advantage of the LM9831’s additional features.
The LM9831 has a simpler multiplier with only one gain range: 0
to 4 V/V. The gain of the multiplier is
14.2.1 1200 DPI
Gain = (gain code)/16384 V/V
The LM9831 can support line widths up to 16384 pixels x 3 colors. This allows 1200dpi scanners with a maximum width of 13.6”
(B-size).
Note that if the gain code = 0, then the pixel is multiplied by 0! In
other words, if the gain coefficient is set to 0, the output of the
multiplier will be all 0s. A gain code of 0 was not unusual for the
LM9830, but will not work with the LM9831. To maintain a minimum gain of 1V/V, make sure the gain code is 16384 or higher.
14.2.2 Integration Time Adjustment Function
Due to DRAM speed limitations, the maximum speed at which the
LM9831 can store pixels is 1MHz. The ADC can run at speeds up
to 6MHz, but only when the HDPI divider is set to divide-by-6 or
greater, which results in a pixel rate of 1MHz or less.
If desired, gains between 0 and 1 V/V can be used, but they will
usually result in less dynamic range and noisier images.
This can be a challenge when scanning at high resolutions. For
example, a 600dpi 8.5” wide color CCD scanner digitizes 15,300
pixels/line. At a 1MHz rate, the resulting integration time
is15.3ms. Integration times above 10ms may be problematic in
some designs.
14.1.6 The Gamma Table
The LM9831’s 3 gamma tables are 12 bits wide, instead of 10 bits
(LM9830). This means each gamma curve has 4 times the number of datapoints and you can now get 4 times the accuracy available with the LM9830.
To allow shorter integration times without violating the 1MHz max
pixel rate, the LM9831 has an Integration Time Adjust (ITA) function (Figure 47). ITA generates 2 alternating timebases for the
CCD timing, a high frequency timebase, and a lower frequency
timebase. During the high frequency timebase, the integration
time (t INT1) is short, as short as the total number of pixels in a line
divided by 6MHz. (Using the previous example, that would be
2.5ms). During tINT1, data is clocked out of the CCD but it is not
digitized by the AFE. The CCD output signal (representing line “n1”) is discarded.
Since most consumer CCDs have a true SNR of less than 12 bits,
the LM9831 does not support a 14 bit gamma table, freeing up an
additional 36kwords of DRAM memory.
14.1.7 General DataPort Information
There have been several important changes to the dataport.
The read-only Pause bit is now in register 3. You can write this bit
in order to write to the other bits in the register, but anything you
write to the Pause bit will be ignored.
After the short integration time, the clock is slowed for the next
integration time (tINT2). Integration for line “n+1” is done during
this period. Since t INT2 is longer, there is more time to read out
pixel data for line “n”. As long as tINT2 corresponds to a pixel rate
of 1MHz or slower, the line can be digitized and written to the
DRAM.
There are now 2 bits to select between Offset Coefficients, Gain
Coefficients, and Gamma data.
In the LM9830, Offset and Gain coefficients were combined to
make one 16 bit word, written to register 6 as 2 bytes.
TR
In the LM9831, Offset is a 16 bit word, and Gain is a 16 bit word.
Offset and Gain data each have a separate dataport address.
Register 5 will auto increment after 2 bytes are written to register
6 in Offset mode or Gain mode (reg03b1 = 0).
Pixel
Data
line n-1
line n-2
tINT1
tINT2
line n
line n+1
discard
line n
Gamma data is 8 bits wide, as in the LM9830. Register 5 will auto
increment after 1 gamma byte is written to register 6 in Gamma
mode (reg03b1 = 1).
Figure 47: Integration Time Adjust Function
The bit locations for selecting color (R, G, or B), have been
shifted left by 1 bit.
tINT 1 is determined by the traditional calculations, primarily the
MCLK divider and line end settings. tINT2 = ITA * tINT1 .
tINT2 = ITA * tINT1
There are two more considerations when using the ITA. The first
is CCD image lag. Image lag is a sensor phenomenon in which a
percentage of the pixel voltage from the previous line appears in
the pixel voltage for the current line. In the example above, some
of the signal from line n-1 will leak into line n. Since the integra-
The DataPort address width is now 14 bits wide. This caused the
R/W bit to be shifted left by 1 bit.
When using 1 Channel Grayscale, the LM9830 ignored the color
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I/O 1, MISC I/O 2, or MISC I/O 3 inputs was supposed to generate a USB Remote Wakeup. While the LM9831 passes the Chapter 9 test for Remote Wakeup, we have not been able to get this
function to work with a PC that is in Suspend Mode. At the time of
release we are still trying to verify functionality of this feature.
tion time for line n-1 (tINT2) is 2 to 6 times longer than tINT1, the
leakage may be as much as 2 to 6 times the sensor specified
image lag. This is usually not a problem. If it is, use a sensor with
a low image lag specification, or reduce the brightness of the
CCFL light source.
The second consideration is the stepsize calculation. Using the
ITA’s dual timebases affects the stepsize required to produce an
image with the correct vertical resolution. The solution is to calculate the stepsize using the traditional formula, then multiply it by
the factor (ITA+1)/ITA:
stepsize_ITA = stepsize
ITA+1
⋅ ----------ITA
15.0 KNOWN ISSUES AND SOLUTIONS
15.1 14-Bit Data Mode
The 14 Bit Data Mode (register 09, bit 5) has two uses. The first is
for calibration, where very accurate pixel data must be acquired
to allow calculation of the offset and shading coefficients. The
second is for scanning images where the pixel data transmitted to
the PC is greater than 8 bits/channel.
The current silicon has two problems in 14 bit mode:
1) When attempting to read more image data than the DRAM
buffer has available (underflowing the DRAM), the LM9831 may
insert an extra, random byte of data. This is not predictable or
detectable. The fix is simple: poll register 01 before reading register 00, and only read the amount of data register 01 says is available.
For 1M x 16 DRAMs, read (<reg 01> - 1) * 8kbytes of data.
For 256k x 16 DRAMs, read (<reg 01> - 1) * 2kbytes of data.
Note: The information in register 01 (number of bytes of image
data in DRAM buffer) is not valid until the first line of image data
has been digitized. The solution is to poll register 01 until it starts
incrementing. When register 01 has incremented, the data it contains is valid.
2) When the DRAM buffer’s address counter “wraps around”, it
may or may not insert 2 extra bytes of bad data. There is no way
to predict when or if this will happen. This limits the size of a continuous scan to the size of the DRAM line buffer (148k pixels or
916k pixels). This means that it is impossible to scan large
images with more than 8 bits/channel being transmitted to the
PC. Calibration can be done at 14 bits (since calibration is only a
few lines of data), but you can not reliably transmit 10, 12, or 14
bit images to the PC.
15.2 USB Interrupts
When configured to do so, changes on the Paper Sense and
MISC I/O pins were supposed to generate USB Interrupts. This
functionality is not working at the time of this datasheet’s publication. The solution (as demonstrated in our Twain Driver software)
is to poll register 02 every 200 to 500ms. This uses very little
additional bandwidth compared to the USB interrupt solution.
15.3 USB Remote Wakeup
When configured to do so, a high-to-low transition on the MISC
37
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LM9831 Digital Block Diagram
48MHz
CRYSTAL/ EXT
CLOCK
24/48
CRYSTAL
OUT
CRYSTAL
IN
EXTERNAL
EEPROM
SCL SDA
Test
CMODE
External EEPROM
2
System Clock
Generation
Internal ROM
Configuration
Registers
Test
Modes
8
USB
Interface
D+, DActive/Suspend
Bus Power
16
16
CCD
or
CIS
Image
Sensor
Analog
Front
End
14
Pixel
Processing
(Horizontal
DPI adjust)
Pixel-Rate
Offset
Subtraction
16
16
16
16 x 16
Pixel-Rate
Multiplier
(Shading)
16
14 Bit
Pixel Data
Gamma
Table
Address
16
Pixel
Processing
(Packing) 16
RD
12
Sensor (Offset and Shading)
Address Counter
17
Buffer In Address Counter
20
WR
DRAM
Address
Multiplexer
and
Controller
RAS
CAS
10
Buffer Out Address Counter
20
Pause Scanning
Line Buffer Controller
Resume Scanning
Stepper
Motor
Controller
The Brains
RESET
System Synchronization and Control
Pixel Counter, Stepper Counter,
Lamp Counter, Command Interpreter
Power
Transistors
3
Current
Feedback
3
Lamp
Control
PAPER
SENSORS 1,2
6
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A0-A9
DRAM
Address Bus
4
2
38
D0-D15
DRAM
Data Bus
MISC I/O 1-6
Analog Front End Block Diagram
RED OS
from sensor
OSR
Gain
Boost
Static
Offset
DACs
x1or x3
+
1
CDS
+
-1
OSG
GREEN OS
from sensor
BLUE OS OSB
from sensor
x0.93
to x3
Offset
DACR
1
CDS
x1or x3
-1
+²
+
x0.93
to x3
Offset
DACG
1
CDS
-1
Coarse Color
Balance PGAs
x1or x3
+²
+
14 Bit
ADC
14
x0.93
to x3
Offset
DACB
VREF LO
VREF MID
ø1
1.5V (CDS)
3.5V (CCD)
ø2
Sensor
Clock
Generation
VREF HI
VBANDGAP
VREGULATOR
Bandgap
Reference
RS
CP1
CP2
TR1
TR2
3V (USB I/O)
Regulator
39
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Stepper Motor Current Controller Block Diagram
Phase A
Invert
A
A
DAC code for
phase A
DAC A:
0.110V,
0.175V,
0.325V,
0.425V,
0.465V
3
–
Set-Dominant
S/R Flipflop
Reset
+
A
+Vmotor
Q
Set
A
8
Comparators need no hysteresis. SR flipflops are set periodically by pulse from PWM Generator. Flipflops can only be reset
after SR goes low when Reset (comparator output) is high
(VSENSE > VDAC).
÷1 to 256
1Ω
HIGH CURRENT
GND SENSE
Reset is level sensitive, not edge sensitive.
CR
6
Stepper
Phase A
SENSE1
12MHz
CR
Stepper
Phase A
÷64
PWM
Generator
0/64 to
63/64
high time
1Ω
SENSE2
B
Set-Dominant
S/R Flipflop
Stepper
Phase B
Stepper
Phase B
Set
DAC code for
phase B
3
DAC B:
0.110V,
0.175V,
0.325V,
0.425V,
0.465V
Q
+
Reset
+Vmotor
–
B
B
B
Phase B
Invert
TriState Stepper
Motor Outputs
LM9831
40
External Components
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LM9831 42-Bit Color 1200dpi USB Image Scanner
Physical Dimensions (millimeters)
100-Pin Thin Plastic Quad FlatPac (JEDEC) (TQFP)
NS Package Number VJD100A
Order Number LM9831VJD
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