MM54HC74A/MM74HC74A Dual D Flip-Flop with Preset and Clear General Description The MM54HC74A/MM74HC74A utilizes advanced silicongate CMOS technology to achieve operating speeds similar to the equivalent LS-TTL part. It possesses the high noise immunity and low power consumption of standard CMOS integrated circuits, along with the ability to drive 10 LS-TTL loads. This flip-flop has independent data, preset, clear, and clock inputs and Q and Q outputs. The logic level present at the data input is transferred to the output during the positive-going transition of the clock pulse. Preset and clear are independent of the clock and accomplished by a low level at the appropriate input. Connection and Logic Diagrams The 54HC/74HC logic family is functionally and pinout compatible with the standard 54LS/74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. Features Y Y Y Y Y Typical propagation delay: 20 ns Wide power supply range: 2 – 6V Low quiescent current: 40 mA maximum (74HC Series) Low input current: 1 mA maximum Fanout of 10 LS-TTL loads Truth Table Dual-In-Line Package Inputs Outputs PR CLR CLK D Q Q L H L H H H H L L H H H X X X X X X H L X H L H* H L Q0 L H H* L H Q0 u u L Note: Q0 e the level of Q before the indicated input conditions were established. * This configuration is nonstable; that is, it will not persist when preset and clear inputs return to their inactive (high) level. TL/F/5106 – 1 Order Number MM54HC74A or MM74HC74A TL/F/5106 – 2 C1995 National Semiconductor Corporation TL/F/5106 RRD-B30M105/Printed in U. S. A. MM54HC74A/MM74HC74A Dual D Flip-Flop with Preset and Clear January 1988 Absolute Maximum Ratings (Notes 1 & 2) Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) DC Input or Output Voltage (VIN, OUT) b 0.5 to a 7.0V Supply Voltage (VCC) b 1.5 to VCC a 1.5V DC Input Voltage (VIN) b 0.5 to VCC a 0.5V DC Output Voltage (VOUT) g 20 mA Clamp Diode Current (IIK, IOK) g 25 mA DC Output Current, per pin (IOUT) g 50 mA DC VCC or GND Current, per pin (ICC) b 65§ C to a 150§ C Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) 600 mW S.O. Package only 500 mW Lead Temp. (TL) (Soldering 10 seconds) 260§ C Operating Temp. Range (TA) MM74HC MM54HC Min 2 Max 6 0 VCC Units V V b 40 b 55 a 85 a 125 §C §C 1000 500 400 ns ns ns Input Rise or Fall Times VCC e 2.0V (tr, tf) VCC e 4.5V VCC e 6.0V DC Electrical Characteristics (Note 4) Symbol Parameter Conditions TA e 25§ C VCC 74HC TA eb40 to 85§ C Typ 54HC TA eb55 to 125§ C Units Guaranteed Limits VIH Minimum High Level Input Voltage 2.0V 4.5V 6.0V 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V V V VIL Maximum Low Level Input Voltage** 2.0V 4.5V 6.0V 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 V V V VOH Minimum High Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA 2.0V 4.5V 6.0V 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V V V 4.5V 6.0V 4.3 5.2 3.98 5.48 3.84 5.34 3.7 5.2 V V 2.0V 4.5V 6.0V 0 0 0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V V V VIN e VIH or VIL lIOUTl s4.0 mA lIOUTl s5.2 mA 4.5V 6.0V 0.2 0.2 0.26 0.26 0.33 0.33 0.4 0.4 V V VIN e VIH or VIL lIOUTl s4.0 mA lIOUTl s5.2 mA VOL Maximum Low Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA IIN Maximum Input Current VIN e VCC or GND 6.0V g 0.1 g 1.0 g 1.0 mA ICC Maximum Quiescent Supply Current VIN e VCC or GND IOUT e 0 mA 6.0V 4.0 40 80 mA Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C. Note 4: For a power supply of 5V g 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. **VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89. 2 AC Electrical Characteristics VCC e 5V, TA e 25§ C, CL e 15 pF, tr e tf e 6 ns Symbol Parameter Conditions Typ Guaranteed Limit Units fMAX Maximum Operating Frequency 72 30 MHz tPHL, tPLH Maximum Propagation Delay Clock to Q or Q 10 30 ns tPHL, tPLH Maximum Propagation Delay Preset or Clear to Q or Q 17 40 ns tREM Minimum Removal Time, Preset or Clear to Clock 6 5 ns ts Minimum Setup Time Data to Clock 10 20 ns tH Minimum Hold Time Clock to Data 0 0 ns tW Minimum Pulse Width Clock, Preset or Clear 8 16 ns AC Electrical Characteristics Symbol Parameter CL e 50 pF, tr e tf e 6 ns (unless otherwise specified) Conditions TA e 25§ C VCC Typ 74HC TA eb40 to 85§ C 54HC TA eb55 to 125§ C Units Guaranteed Limits fMAX Maximum Operating Frequency 2.0V 4.5V 6.0V 22 72 94 6 30 35 5 24 28 4 20 24 MHz MHz MHz tPHL, tPLH Maximum Propagation Delay Clock to Q or Q 2.0V 4.5V 6.0V 34 12 10 110 22 19 140 28 24 165 33 28 ns ns ns tPHL, tPLH Maximum Propagation Delay Preset or Clear To Q or Q 2.0V 4.5V 6.0V 66 20 16 150 30 26 190 38 33 225 45 38 ns ns ns tREM Minimum Removal Time Preset or Clear To Clock 2.0V 4.5V 6.0V 20 6 5 50 10 9 65 13 11 75 15 13 ns ns ns ts Minimum Setup Time Data to Clock 2.0V 4.5V 6.0V 35 10 8 80 16 14 100 20 17 120 24 20 ns ns ns tH Minimum Hold Time Clock to Data 2.0V 4.5V 6.0V 0 0 0 0 0 0 0 0 0 ns ns ns tW Minimum, Pulse Width Clock, Preset or Clear 2.0V 4.5V 6.0V 30 9 8 80 16 14 101 20 17 119 24 20 ns ns ns tTLH, tTHL Maximum Output Rise and Fall Time 2.0V 4.5V 6.0V 25 7 6 75 15 13 95 19 16 110 22 19 ns ns ns tr, tf Maximum Input Rise and Fall Time 2.0V 4.5V 6.0V 1000 500 400 1000 500 400 1000 500 400 ns ns ns CPD Power Dissipation Capacitance (Note 5) CIN Maximum Input Capacitance (per flip-flop) 80 5 pF 10 10 10 pF Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, IS e CPD VCC f a ICC. 3 MM54HC74A/MM74HC74A Dual D Flip-Flop with Preset and Clear Physical Dimensions inches (millimeters) Order Number MM54HC74J or MM74HC74J NS Package J14A Order Number MM74HC74N NS Package N14A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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