MM54C74/MM74C74 Dual D Flip-Flop General Description The MM54C74/MM74C74 dual D flip-flop is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement transistors. Each flipflop has independent data, preset, clear and clock inputs and Q and Q outputs. The logic level present at the data input is transferred to the output during the positive going transition of the clock pulse. Preset or clear is independent of the clock and accomplished by a low level at the preset or clear input. Y Features Y Y Y Y Supply voltage range Tenth power TTL compatible High noise immunity 3V to 15V Drive 2 LPT2L loads 0.45 VCC (typ.) Y Low power Medium speed operation 50 nW (typ.) 10 MHz (typ.) with 10V supply Applications Y Y Y Y Y Y Y Automotive Data terminals Instrumentation Medical electronics Alarm system Industrial electronics Remote metering Computers Logic Diagram TL/F/5885 – 1 Truth Table Connection Diagram Preset Clear Qn Qn 0 0 1 1 0 1 0 1 0 1 0 *Qn 0 0 1 *Qn Dual-In-Line Package *No change in output from previous state. Order Number MM54C74 or MM74C74 Top View TL/F/5885 – 2 Note: A logic ‘‘0’’ on clear sets Q to logic ‘‘0’’. A logic ‘‘0’’ on preset sets Q to logic ‘‘1’’. C1995 National Semiconductor Corporation TL/F/5885 RRD-B30M105/Printed in U. S. A. MM54C74/MM74C74 Dual D Flip-Flop February 1988 Absolute Maximum Ratings (Note 1) b 65§ C to a 150§ C Storage Temperature Range Power Dissipation Dual-In-Line 700 mW Small Outline 500 mW Lead Temperature (Soldering, 10 seconds) 260§ C If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Voltage at Any Pin (Note 1) b 0.3V to VCC a 0.3V Operating Temperature Range MM54C74 MM74C74 b 55§ C to a 125§ C b 40§ C to a 85§ C Operating VCC Range VCC(Max) 3V to 15V 18V DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise specified Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) VIN(0) Logical ‘‘1’’ Input Voltage Logical ‘‘0’’ Input Voltage VOUT(1) Logical ‘‘1’’ Output Voltage VOUT(0) Logical ‘‘0’’ Output Voltage VCC e 5V 3.5 VCC e 10V 80 V V VCC e 5V 1.5 VCC e 10V 2.0 VCC e 5V 4.5 VCC e 10V 9.0 V V V V VCC e 5V 0.5 VCC e 10V 1.0 V VCC e 15V 1.0 mA IIN(1) Logical ‘‘1’’ Input Current IIN(0) Logical ‘‘0’’ Input Current VCC e 15V ICC Supply Current VCC e 15V b 1.0 V mA 0.05 60 mA 0.8 V CMOS/LPTTL INTERFACE VIN(1) Logical ‘‘1’’ Input Voltage 54C, VCC e 4.5V 74C, VCC e 4.75V VIN(0) Logical ‘‘0’’ Input Voltage 54C, VCC e 4.75V 74C, VCC e 4.75V VOUT(1) Logical ‘‘1’’ Output Voltage VOUT(0) Logical ‘‘0’’ Output Voltage 54C, VCC e 4.5V, ID e b360 mA 74C, VCC e 4.75V, ID e b360 mA 54C, VCC e 4.5V, ID e 360 mA 74C, VCC e 4.75V, ID e 360 mA VCCb1.5 2.4 V 0.4 V OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) ISOURCE Output Source Current VCC e 5V, VIN(0) e 0V TA e 25§ C, VOUT e 0V b 1.75 mA ISOURCE Output Source Current VCC e 10V, VIN(0) e 0V TA e 25§ C, VOUT e 0V b 8.0 mA ISINK Output Sink Current VCC e 5V, VIN(1) e 5V TA e 25§ C, VOUT e VCC 1.75 mA ISINK Output Sink Current VCC e 10V, VIN(1) e 10V TA e 25§ C, VOUT e VCC 8.0 mA Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. 2 AC Electrical Characteristics* TA e 25§ C, CL e 50 pF, unless otherwise noted Symbol Parameter Conditions Min Typ Max Units CIN Input Capacitance Any Input (Note 2) 5.0 tpd Propagation Delay Time to a Logical ‘‘0’’ tpd0 or Logical ‘‘1’’ tpd1 from Clock to Q or Q VCC e 5V VCC e 10V 180 70 300 110 ns ns tpd Propagation Delay Time to a Logical ‘‘0’’ from Preset or Clear VCC e 5V VCC e 10V 180 70 300 110 ns ns tpd Propagation Delay Time to a Logical ‘‘1’’ from Preset or Clear VCC e 5V VCC e 10V 250 100 400 150 ns ns tS0, tS1 Time Prior to Clock Pulse that Data Must be Present tSETUP VCC e 5V VCC e 10V tH0, tH1 Time after Clock Pulse that Data Must be Held VCC e 5V VCC e 10V b 20 b 8.0 0 0 ns ns tPW1 Minimum Clock Pulse Width (tWL e tWH) VCC e 5V VCC e 10V 100 40 250 100 ns ns tPW2 Minimum Preset and Clear Pulse Width VCC e 5V VCC e 10V 100 40 160 70 ns ns tr, tf Maximum Clock Rise and Fall Time VCC e 5V VCC e 10V 15.0 5.0 fMAX Maximum Clock Frequency VCC e 5V VCC e 10V 2.0 5.0 CPD Power Dissipation Capacitance (Note 3) 100 40 pF 50 20 ns ns ms ms 3.5 8.0 MHz MHz 40 pF *AC Parameters are guaranteed by DC correlated testing. Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: Capacitance is guaranteed by periodic testing. Note 3: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics Application NoteÐAN-90. Switching Time Waveform CMOS to CMOS TL/F/5885 – 3 tr e tf e 20 ns 3 AC Test Circuit TL/F/5885 – 4 Typical Applications Ripple Counter (Divide by 2n) TL/F/5885 – 5 Shift Register TL/F/5885 – 6 Guaranteed Noise Margin as a Function of VCC 74C Compatibility TL/F/5885 – 7 TL/F/5885 – 8 4 Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54C74J or MM74C74J NS Package Number J14A 5 MM54C74/MM74C74 Dual D Flip-Flop Physical Dimensions inches (millimeters) (Continued) Ceramic Dual-In-Line Package (J) Order Number MM54C74N or MM74C74N NS Package Number N14A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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