NSC MM54HC4017

MM54HC4017/MM74HC4017
Decade Counter/Divider with 10 Decoded Outputs
General Description
The MM54HC4017/MM74HC4017 is a 5-stage Johnson
counter with 10 decoded outputs that utilizes advanced silicon-gate CMOS technology. Each of the decoded outputs is
normally low and sequentially goes high on the low to high
transition of the clock input. Each output stays high for one
clock period of the 10 clock period cycle. The CARRY output transitions low to high after OUTPUT 9 goes low, and
can be used in conjunction with the CLOCK ENABLE to
cascade several stages. The CLOCK ENABLE input disables counting when in the high state. A RESET input is
also provided which when taken high sets all the decoded
outputs low except output 0.
The MM54HC4017/MM74HC4017 is functionally and pinout
equivalent to the CD4017BM/CD4017BC. It can drive
up to 10 low power Schottky equivalent loads. All inputs are
protected from damage due to static discharge by diodes
from VCC and ground.
Features
Y
Y
Y
Y
Y
Wide power supply range: 2 – 6V
Typical operating frequency: 30 MHz
Fanout of 10 LS-TTL loads
Low quiescent current: 80 mA (74HC Series)
Low input current: 1.0 mA
Connection Diagram
Dual-In-Line and Flat Package
TL/F/5351 – 1
Order Number MM54HC4017 or MM74HC4017
C1995 National Semiconductor Corporation
TL/F/5351
RRD-B30M105/Printed in U. S. A.
MM54HC4017/MM74HC4017 Decade Counter/Divider with 10 Decoded Outputs
January 1988
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VCC)
Supply Voltage (VCC)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (IIK, IOK)
DC Output Current, per pin (IOUT)
DC VCC or GND Current, per pin (ICC)
Storage Temperature Range (TSTG)
Power Dissipation (PD)
(Note 3)
S.O. Package only
Lead Temperature (TL)
(Soldering 10 seconds)
DC Input or Output Voltage
(VIN, VOUT)
b 0.5 to a 7.0V
b 1.5 to VCC a 1.5V
Operating Temp. Range (TA)
MM74HC
MM54HC
b 0.5 to VCC a 0.5V
g 20 mA
Min
2
Max
6
0
VCC
Units
V
V
b 40
b 55
a 85
a 125
§C
§C
1000
500
400
ns
ns
ns
Input Rise or Fall Times
VCC e 2.0V
(tr, tf)
VCC e 4.5V
VCC e 6.0V
g 25 mA
g 50 mA
b 65§ C to a 150§ C
600 mW
500 mW
260§ C
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
TA e 25§ C
VCC
74HC
TA eb40 to 85§ C
Typ
54HC
TA eb55 to 125§ C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage**
2.0V
4.5V
6.0V
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
V
VOH
Minimum High Level
Output Voltage
VIN e VIH or VIL
lIOUTl s20 mA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN e VIH or VIL
lIOUTl s4.0 mA
lIOUTl s5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN e VIH or VIL
lIOUTl s4.0 mA
lIOUTl s5.2 mA
VOL
Maximum Low Level
Output Voltage
VIN e VIH or VIL
lIOUTl s20 mA
IIN
Maximum Input
Current
VIN e VCC or GND
6.0V
g 0.1
g 1.0
g 1.0
mA
ICC
Maximum Quiescent
Supply Current
VIN e VCC or GND
IOUT e 0 mA
6.0V
8.0
80
160
mA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C.
Note 4: For a power supply of 5V g 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN,
ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
**VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89.
2
AC Electrical Characteristics
Symbol
VCC e 5V, TA e 25§ C, CL e 15 pF, tr e tf e 6 ns
Parameter
Conditions
Typ
Guaranteed
Limit
Units
Measured with
respect to carry line
50
30
MHz
fMAX
Maximum Clock Frequency
tPHL, tPLH
Maximum Propagation
Delay, Enable to Carry-Out Line
26
44
ns
tPHL, tPLH
Maximum Propagation
Delay Enable Decode-Out Lines
27
44
ns
tPHL, tPLH
Maximum Propagation
Delay, Reset or Clock to Decode Out
23
40
ns
tPHL, tPLH
Maximum Propagation
Delay, Reset or Clock to Carry Out
23
40
ns
tS
Minimum Clock Inhibit to Clock
Set-Up Time
12
20
ns
tW
Minimum Clock or Reset Pulse Width
8
16
ns
tREM
Minimum Reset Removal Time
20
10
ns
AC Electrical Characteristics
Symbol
Parameter
VCC e 2.0 – 6.0V, CL e 50 pF, tr e tf e 6 ns (unless otherwise specified)
Conditions
VCC
TA e 25§ C
Typ
fMAX
Maximum Clock Frequency
Measured with
2.0V
respect to carry line 4.5V
6.0V
74HC
54HC
TA eb40 to 85§ C TA eb55 to 125§ C Units
Guaranteed Limits
6
30
35
5
24
28
4
20
24
MHz
MHz
MHz
tPHL, tPLH Maximum Propagation
Delay, Enable to Carry-Out Line
2.0V 89
4.5V 25
6.0V 20
250
50
43
312
63
54
375
75
65
ns
ns
ns
tPHL, tPLH Maximum Propagation
Delay, Enable to Decode Out Line
2.0V 90
4.5V 25
6.0V 20
250
50
43
312
63
54
375
75
65
ns
ns
ns
tPHL, tPLH Maximum Propagation
Delay, Reset or Clock to Decode Out
2.0V 82
4.5V 22
6.0V 18
230
46
39
288
58
49
345
69
59
ns
ns
ns
tPHL, tPLH Maximum Propagation
Delay, Reset or Clock to Carry Out
2.0V 82
4.5V 22
6.0V 18
230
46
39
288
58
49
345
69
59
ns
ns
ns
tW
Minimum Reset, Clock, or
Clock Enable Pulse Width
2.0V 30
4.5V 9
6.0V 8
80
16
14
100
20
18
120
24
21
ns
ns
ns
tREM
Minimum Reset Removal Time
2.0V
4.5V
6.0V
100
20
17
125
25
21
150
30
25
ns
ns
ns
tS, tH
Minimum Clock Inhibit
to Clock Set-Up or Hold Time
2.0V
4.5V
6.0V
50
10
9
63
13
11
75
15
13
ns
ns
ns
tTHL, tTLH Maximum Output Rise
and Fall Time
2.0V 30
4.5V 8
6.0V 7
75
15
13
95
19
16
110
22
19
ns
ns
ns
tr, tf
Minimum Input Rise and Fall Time
2.0V
4.5V
6.0V
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
CPD
Power Dissipation
Capacitance (Note 5)
CIN
Maximum Input Capacitance
(per package)
pF
5
10
10
10
pF
Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, IS e CPD VCC f a ICC.
3
Logic and Timing Diagrams
MM54HC4017/MM74HC4017
TL/F/5351 – 2
TL/F/5351 – 3
4
5
MM54HC4017/MM74HC4017 Decade Counter/Divider with 10 Decoded Outputs
Physical Dimensions inches (millimeters)
Dual-In-Line and Flat Package
Order Number MM54HC4017J or MM74HC4017J,N
NS Package Number J16A
Dual-In-Line and Flat Package
Order Number MM74HC4017N
NS Package Number N16E
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