HI-2130 Single Package MIL-STD-1553 / MIL-STD-1760 3.3V BC / MT / RT with Integrated Transformers January 2013 FEATURES GENERAL DESCRIPTION The HI-2130 provides a 3.3V fully integrated interface between a host processor and a MIL-STD-1553 / MIL-STD-1760 bus. It combines the functionality of Holt’s HI-6130 16-bit parallel bus interface and HI-6131 SPI devices, integrating MIL-STD-1553 protocol logic, dual transceivers and dual transformers in a single compact 15 x 15mm package. The HI-2130 die is hermetically sealed in a ceramic substrate and dual transformers are mounted onto the same package. Two package options are offered, namely BGA and PGA (see “Ordering Information” on page 6). The device includes the entire signal I/O set of HI-6130 and HI-6131, with the addition of a new input signal for selecting parallel bus or SPI host interface. Two pairs of transformer output signals connect directly to the MIL-STD-1553 Bus A and Bus B stubs. o o The part is available in Industrial -40 C to +85 C, or o o Extended, -55 C to +125 C temperature ranges. Optional burn-in is available on the extended temperature range. Refer to the HI-6130 datasheet for full functional description and operation. 64K Byte Shared RAM External Serial Flash EEPROM Interface HI-2130 Transformers BC RT RT MT MIL-STD-1553 Protocol & Memory Management DS2130 Rev. B Transceiver A Transceiver B • Combined functionality of HI-6130 and HI-6131 in a single package with integrated transformers • Smallest footprint MIL-STD-1553 solution available (includes transformers) • Extended temperature range, -55ºC to +125ºC, with optional burn-in • Hermetically sealed die improves reliability and achieves MSL 1 • Less expensive than traditional multi-chip modules • DO-254 certifiable • Concurrent multi-terminal operation (BC, MT, 1 or 2 independent RTs) • Two host interface options in one package: 16-bit parallel bus or 4-wire SPI • 64K bytes on-chip RAM with error detection/ correction option • Autonomous terminal operation requires minimal host intervention • Shared MIL-STD-1553 bus interface reduces circuit complexity and circuit board area. • Fully programmable Bus Controller with 28 op code instruction set • Simple Monitor Terminal (SMT) Mode records commands and data separately, with 16-bit or 48-bit time tagging • IRIG Monitor Terminal (IMT) Mode supports IRIG-106 Chapter 10 packet format. Complete IRIG-106 data packets including full packet headers and trailers can be generated • Independent time-tag counters for all terminals with 32-bit option for Bus Controller and 48-bit option for Monitor Terminal • 64-Word Interrupt Log Buffer queues the most recent 32 interrupts. Hardware-assisted interrupt decoding quickly identifies interrupt sources • Built-in self-test for protocol logic, digital signal paths and internal RAM • Optional self-initialization at reset uses external serial EEPROM o o • Two temperature ranges: -40 C to +85 C, or o o -55 C to +125 C HOLT INTEGRATED CIRCUITS www.holtic.com 1 01/13 HI-2130 BLOCK DIAGRAM HI-2130 HI-6130 / HI-6131 RT1A4 - 0 RT1AP IRQ MTPKRDY READY ACTIVE RT1MC8 Discrete Signal Outputs Configuration Option Logic BWID RAMEDC INTERNAL CLOCKS RE Data WE BC Message Processor Control Address WPOL Memory and Register Access Control Control BUS / SPI CE MT Message Processor SCK RT2ENA ACKIRQ RT1SSF RT2SSF Words Bus A Manchester Decoder BUSA TXINHB Bus B Manchester Encoder BUSB Bus B Manchester Decoder BUSB RT2 Message Processor Serial Peripheral Interface (SPI) to EEPROM ESCK RT1ENA Discrete Signal Inputs Data Address BCENA BCTRIG ECS MR BUSA MISO MOSI EECOPY RT1 Message Processor MTTCLK Bus A Manchester Encoder Control Reset & Initialization Logic Address & Control AUTOEN Data MISO Control Address MOSI Rx 1553 Words Data Tx 1553 Words Address D15:0 MCLK TTCLK TXINHA Host Interface A15:1 MTRUN RT1LOCK MTSTOFF 64K Static RAM and Registers BTYPE A0 BENDI RT2LOCK RT2MC8 WAIT RT2A4 - 0 RT2AP OPTIONAL SERIAL EEPROM (AUTO-CONFIG) HOLT INTEGRATED CIRCUITS 2 POWER Test Logic GND VDD TEST MODE HI-2130 PIN DIAGRAM Top View 11 10 9 8 7 6 L RAM EDC DATA 14 DATA 11 DATA 9 DATA 4 RT1 SSF K nCE DATA 12 DATA 10 AUTO EN DATA 6 VDD J MODE BC TRIG DATA 13 TX INHA H MISO DATA 15 MOSI G nWAIT SCLK 5 4 MTPKT RT1 RDY MC8 3 2 1 nIRQ B BENDI TYPE L ACK IRQ DATA 2 WPOL nBUS A K DATA 7 DATA READY TEST 5 DATA 0 DATA 1 nBUS A J TX INHB DATA 8 DATA 3 RT2 MC8 MTST OFF RT1 LOCK DNC BUS A H nRE VDD GND VDD GND VDD BC ENA DNC BUS A G ACTIVE F nWE BUS nSPI MCLK GND VDD GND VDD GND VDD DNC DNC F E RT1 A2 RT1 A0 RT1 A1 VDD GND VDD GND VDD RT2 ENA DNC BUS B E D nMR RT1 A3 RT1 A4 ADDR 8 nECS ADDR RT2 10 LOCK RT2 A0 RT2 A1 DNC BUS B D C ADDR 0 RT1 ENA ADDR 2 E MOSI GND EE COPY MT RUN RT2 A2 RT2 A3 ADDR 14 nBUS B C B ADDR ADDR ADDR ADDR 1 3 4 6 TT CLK VDD ESCK RT2 SSF ADDR ADDR 15 13 nBUS B B A ADDR 5 RT1 AP E MISO ADDR 7 MTT CLK ADDR ADDR 9 11 RT2 AP RT2 A4 ADDR 12 BWID A 11 10 9 8 7 4 3 2 1 6 5 See HI-6130 datasheet for a full Pin Description. Notes: a. DNC: Do Not Connect. b. All balls denoted VDD must be connected to 3.3V DC power. c. All balls denoted GND must be connected to circuit ground. d. BUS/nSPI (F10) selects 16-bit wide parallel bus or SPI operation (see Section “Selection of Host Interface” on page 4). e. nCE: The chip enable signal is shared between 16-bit parallel and SPI host interfaces (SPI Slave Select). HOLT INTEGRATED CIRCUITS 3 HI-2130 OPERATION Refer to the HI-6130 datasheet for detailed operation and register description. Selection of Host Interface The host interface is selected using the SPI/BUS pin. • BUS/SPI pin set to logic “1”: Selects 16-bit parallel bus host interface • BUS/SPI pin reset to logic “0”: Selects SPI host interface HOLT INTEGRATED CIRCUITS 4 HI-2130 PACKAGE DIMENSIONS Pin Grid Array (121PGA) Bottom View Top View 0.590 (14.986) 0.220 (5.59) .075 ± .008 (1.9 ± 0.2) .500 (12.7) 10X @ .050 (1.27) L 10X @ .050 (1.27) .500 (12.7) .011 (0.28) HI-2130 +.003 (0.076) –.001 (0.025) 121X 0.590 (14.986) K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 +0.0020 121X Ø.0338 –0.0019 121X @ .120 (3.048) Ø.012 M C A B Ø.006 M C Dimensions in inch (mm) inches Ball Grid Array (121BGA) Top View BottomView 0.590 (14.986) 0.220 (5.59) 10 EQ. SP. @ .050 (1.27) = 0.5 (12.7) K .050 (1.27) 0.590 (14.986) J H G HI-2130 F E D C B A 1 0.075 (1.905) Dimensions in inch (mm) HOLT INTEGRATED CIRCUITS 5 2 3 4 5 6 7 8 9 10 11 121x Ø = 0.035 (0.89) 0.045 (1.143) L HI-2130 ORDERING INFORMATION HI - 2130 Cx x F PART NUMBER Blank LEAD FINISH Tin / Lead (Sn / Pb) finish, BGA only F Pb-free, RoHS compliant PART NUMBER TEMPERATURE RANGE o o FLOW BURN IN I -40 C to +85 C I No T -55oC to +125oC T No PART NUMBER PACKAGE DESCRIPTION CP 121 PIN GRID ARRAY - PGA (121PGA), (Pb-free, RoHS compliant) CB 121 BALL GRID ARRAY - BGA (121BGA), non-collapsing solder balls HOLT INTEGRATED CIRCUITS 6 HI-2130 REVISION HISTORY Revision DS2130, Date Description of Change Rev. New 09/14/12 Initial Release. Rev. A 11/14/12 Corrected typos in pin diagram. Updated package drawings for new thickness. Updated Ordering Information table. Rev. B 01/22/13 Remove LGA package option. HOLT INTEGRATED CIRCUITS 7