HI-3588 ARINC 429 Receiver with SPI Interface July 2012 GENERAL DESCRIPTION 44 43 42 41 40 39 38 37 36 35 34 N/C RINB-40 RINB N/C N/C N/C MR SI CS N/C N/C · · 3.3V or 5.0V logic supply operation On-chip analog line receiver connects directly to ARINC 429 bus Programmable label recognition for 256 labels N/C N/C N/C GND N/C N/C N/C N/C RFLAG N/C N/C N/C N/C N/C SCK N/C GND N/C ACLK SO N/C N/C - N/C - RINA - RINA-40 - N/C - VDD - N/C - N/C - N/C - N/C - N/C - N/C 44 43 42 41 40 39 38 37 36 35 34 N/C - 1 RINB-40 - 2 RINB - 3 N/C - 4 N/C - 5 N/C - 6 MR - 7 SI - 8 CS - 9 N/C - 10 N/C - 11 HI-3588PQI HI-3588PQT 33 - N/C 32 - N/C 31 - N/C 30 - GND 29 - N/C 28 - N/C 27 - N/C 26 - N/C 25 - RFLAG 24 - N/C 23 - N/C 32 x 32 Receive Data FIFO N/C - 12 N/C - 13 N/C - 14 SCK - 15 N/C - 16 GND - 17 N/C - 18 ACLK - 19 SO - 20 N/C - 21 N/C - 22 · · · · · · ARINC specification 429 compliant - 44 - Pin Plastic 7mm x 7mm Chip-Scale Package (QFN) The HI-3588 checks received data against ARINC 429 electrical, timing and protocol requirements. ARINC 429 databus timing comes from a 1 MHz clock input, or an internal counter can derive it from higher clock frequencies having certain fixed values, possibly the external host processor clock. · · · HI-3588PCI HI-3588PCT 33 32 31 30 29 28 27 26 25 24 23 - The Serial Peripheral Interface minimizes the number of host interface signals allowing for a small footprint device which can be interfaced to a wide variety of industrystandard microcontrollers supporting SPI. Alternatively, the SPI signals may be controlled using just four general purpose I/O port pins from a microcontroller or custom FPGA. The SPI and all control signals are CMOS and TTL compatible and support 3.3V or 5V operation. FEATURES - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 12 13 14 15 16 17 18 19 20 21 22 The HI-3588 from Holt Integrated Circuits is a silicon gate CMOS device for interfacing a Serial Peripheral Interface (SPI) enabled microcontroller to an ARINC 429 serial bus. The device provides one receiver with user-programmable label recognition for any combination of 256 possible labels, a 32 by 32 Receive FIFO and an analog line receiver. Receive FIFO status can be monitored using the programmable external interrupt pin, or by polling the HI-3588 Status Register. Other features include the ability to switch the bit-signifiance of ARINC 429 labels. The ARINC input pins are available with different input resistance values to provide flexibility when adding external lightning protection circuitry. N/C RINA RINA-40 N/C VDD N/C N/C N/C N/C N/C N/C PIN CONFIGURATIONS (Top View) Programmable data rate selection High-speed, four-wire Serial Peripheral Interface Label bit-order control Parity checking may be disabled to allow 32-bit data reception Low power 44 - Pin Plastic Quad Flat Pack (PQFP) Industrial & extended temperature ranges (DS3588 Rev. G) HOLT INTEGRATED CIRCUITS www.holtic.com 07/12 HI-3588 BLOCK DIAGRAM VDD ARINC Clock Divider ACLK SCK CS SPI Interface SI SO Control Register RINA-40 RINB Label Filter Bit Map Memory ARINC 429 Line Receiver RINB-40 RINA Status Register 40 Kohm 40 Kohm ARINC 429 Valid word Checker Label Filter ARINC 429 Received Data FIFO RFLAG GND PIN DESCRIPTIONS SIGNAL FUNCTION RINB RINB-40 MR SI CS SCK GND ACLK SO RFLAG VDD RINA-40 RINA INPUT INPUT INPUT INPUT INPUT INPUT POWER INPUT OUTPUT OUTPUT POWER INPUT INPUT DESCRIPTION ARINC receiver negative input. Direct connection to ARINC 429 bus Alternate ARINC receiver negative input. Requires external 40K ohm resistor Master Reset. A positive pulse clears the Receiver data FIFO and flags SPI interface serial data input Chip select. Data is shifted into SI and out of SO when CS is low. SPI Clock. Data is shifted into or out of the SPI interface using SCK Chip 0V supply. Note BOTH GND pins MUST be connected Master timing source for the ARINC 429 receiver SPI interface serial data output Goes high when ARINC 429 receiver FIFO is empty (CR15=0), or full (CR15=1) 3.3V or 5.0V logic power Alternate ARINC receiver positive input. Requires external 40K ohm resistor ARINC receiver positive input. Direct connection to ARINC 429 bus HOLT INTEGRATED CIRCUITS 2 INTERNAL PULL UP / DOWN 10K ohm pull-down 10K ohm pull-down 10K ohm pull-up 10K ohm pull-down 10K ohm pull-down HI-3588 INSTRUCTIONS Instruction op codes are used to read, write and configure the HI3588A. When CS goes low, the next 8 clocks at the SCK pin shift an instruction op code into the decoder, starting with the first positive edge. The op code is fed into the SI pin, most significant bit first. For write instructions, the most significant bit of the data word must immediately follow the instruction op code and is clocked into its register on the next rising SCK edge. Data word length varies depending on word type written: 16-bit writes to Control Register, 32-bit ARINC word writes to transmit FIFO or 256-bit writes to the label-matching enable/disable table. Table 1 lists all instructions. Instructions that perform a reset or set are executed after the last SI bit is received while CS is still low. Example: one SPI Instruction CS SCK SI op code 07hex MSB For read instructions, the most significant bit of the requested data word appears at the SO pin after the last op code bit is clocked into the decoder, at the next falling SCK edge. As in write instructions, data field bit-length varies with read instruction type. data field 02hex LSB MSB LSB TABLE 1. DEFINED INSTRUCTION OP CODES OP CODE Hex DATA FIELD 00 None No instruction implemented 01 None After the 8th op-code bit is received, perform Master Reset (MR) 02 None After the 8th op-code bit is received, reset all label selections 03 None After the 8th op-code bit is received, set all the label selections 04 8 bits Reset label at address specified in data field 05 8 bits Set label at address specified in data field 06 256 bits 07 8 bits Programs a division of the ACLK input. If the divided ACLK frequency is 1 MHz and Control Register bit CR1 is set, the ARINC receiver operates from the divided ACLK clock. Allowable values for division rate are X1, X2, X4, X8, or XA hex. Any other programmed value results in no clock. Note: ACLK input frequency and division ratio must result in 1 MHz clock. 08 32 bits Read the next word in the Receive FIFO. If the FIFO is empty, it will read zeros 09 None No instruction implemented 0A 8 bits Read the Status Register 0B 16 bits Read the Control Register 0C 8 bits Read the ACLK divide value programmed previously using op code 07 hex 0D 256 bits 0E None No instruction implemented 0F None No instruction implemented 10 16 bits Write the Control Register DESCRIPTION Starting with label FF hex, consecutively set or reset each label in descending order For example, a Data Field pattern starting with 1011 will set labels FF, FD, and FC hex and reset label FE hex. Read the Label look-up memory table consecutively starting with address FF hex HOLT INTEGRATED CIRCUITS 3 HI-3588 FUNCTIONAL DESCRIPTION CONTROL WORD REGISTER STATUS REGISTER The HI-3588 contains a 16-bit Control Register which is used to configure the device. Control Register bits CR15 - CR0 are loaded from a 16-bit data value appended to SPI instruction 10 hex. The Control Register contents may be read using SPI instruction 0B hex. Each bit of the Control Register has the following function: The HI-3588 contains an 8-bit Status Register which can be interrogated to determine status of the ARINC Receive FIFO. The Status Register is read using SPI instruction 0A hex. Unused bits are undefined and may be read as either “1” or “0”. The following table defines the Status Register bits. Data rate = CLK/80 (ARINC 429 Low-Speed) 0 ARINC CLK = ACLK input frequency 1 ARINC CLK = ACLK divided by the value programmed with SPI Instruction 07 hex 0 Label recognition disabled 1 Label recognition enabled Not used CR3 - X CR4 Receiver Parity Check Enable 0 Receiver parity check disabled 1 Receiver odd parity check enabled Receiver Enable 0 Disable receiver. The HI-3588 ignores all ARINC 429 data bus traffic 1 Normal operation 0 Receiver decoder disabled 1 ARINC bits 10 and 9 must match CR7 and CR8 - If receiver decoder is enabled, the ARINC bit 10 must match this bit CR8 - - If receiver decoder is enabled, the ARINC bit 9 must match this bit CR9 - X Not used CR10 - X Not used 0 Label bit order reversed (SeeTable 2) 1 Label bit order same as received (See Table 2) Receiver FIFO is empty 0 Receiver FIFO holds less than 16 words 1 Receiver FIFO holds at least 16 words 0 Receiver FIFO not full. RFLAG pin reflects the state of this bit when CR15=”1” 1 Receiver FIFO full. To avoid data loss, the FIFO must be read within one ARINC word period SR1 SR2 Receive FIFO Half Full Receive FIFO Full SR3 Not used X Undefined SR4 Not used X Undefined SR5 Not used X Undefined SR6 Not used 0 Always “0” SR7 (MSB) Not used 0 Always “0” ARINC 429 DATA FORMAT CR12 - X Not used CR13 - X Not used CR14 - X Not used CR15 (MSB) RFLAG Definition 0 FLAG goes high when receive FIFO is empty 1 RFLAG goes high when receive FIFO is full Control Register bit CR11 controls how individual bits in the received ARINC word are mapped to the HI-3588 SPI data word bits during data read or write operations. The following table describes this mapping: Table 2. SPI / ARINC bit-mapping SPI Order 6 7 8 Data 31 - 11 Data CR11=0 ARINC bit 32 CR11=1 HOLT INTEGRATED CIRCUITS 4 Label (LSB) 5 10 9 8 7 6 5 4 3 2 1 Label (MSB) 4 Label 3 Label 2 Label 1 Label 9 Label 10 Label 31 - 11 Label . ARINC bit 32 Label 23 24 25 26 27 28 29 30 31 32 Label 2 - 22 Label 1 Label CR11 ARINC Label Bit Order 1 Label - Receiver FIFO contains valid data Sets to One when all data has been read. RFLAG pin reflects the state of this bit when CR15=”0” SDI CR7 Receiver Decoder 0 Label (MSB) CR6 Receive FIFO Empty SDI CR5 SR0 (LSB) DESCRIPTION Label (LSB) CR2 Enable Label Recognition Data rate = CLK/10 (ARINC 429 High-Speed) 1 STATE SDI CR1 ARINC Clock Source Select 0 FUNCTION SDI Receiver Data Rate Select SR Bit Parity CR0 (LSB) DESCRIPTION Parity CR Bit FUNCTION STATE HI-3588 FUNCTIONAL DESCRIPTION (cont.) ARINC 429 RECEIVER The HI-3588 accepts signals within these tolerances and rejects signals outside these tolerances. Receiver logic achieves this as described below: ARINC BUS INTERFACE Figure 1 shows the input circuit for the ARINC 429 line receiver. The ARINC 429 specification requires the following detection levels: STATE ONE NULL ZERO RINA-40 DIFFERENTIAL VOLTAGE +6.5 Volts to +13 Volts +2.5 Volts to -2.5 Volts -6.5 Volts to -13 Volts DIFFERENTIAL AMPLIFIERS VDD COMPARATORS ONE RINA NULL GND VDD ZERO RINB GND FIGURE 1. ARINC RECEIVER INPUT The HI-3588 guarantees recognition of these levels with a common mode voltage with respect to GND less than ±30V for the worst case condition (3.15V supply and 13V signal level). Design tolerances guarantee detection of the above levels, so the actual acceptance ranges are slightly larger. If the ARINC signal (including nulls) is outside the differential voltage ranges, the HI-3588 receiver rejects the data. Valid data bits require at least three consecutive One or Zero samples (three high bits) in the upper half of the Ones or Zeros sampling shift register, and at least three consecutive Null samples (three high bits) in the lower half of the Null sampling shift register within the data bit interval. 3. To validate the receive data bit rate, each bit must follow its preceding bit by not less than 8 samples and not more than 12 samples. With exactly 1MHz input clock frequency, the acceptable data bit rates are: DATA BIT RATE MIN DATA BIT RATE MAX RECEIVER LOGIC OPERATION Figure 2 is a block diagram showing receiver logic. BIT TIMING The ARINC 429 specification defines the following timing tolerances for received data: HIGH SPEED 100K BPS ± 1% 1.5 ± 0.5 µsec 1.5 ± 0.5 µsec 5 µsec ± 5% 2. The receiver uses three separate 10-bit sampling shift registers for Ones detection, Zeros detection and Null detection. When the input signal is within the differential voltage range for any shift register’s state (One Zero or Null) sampling clocks a high bit into that register. When the receive signal is outside the differential voltage range defined for any shift register, a low bit is clocked. Only one shift register can clock a high bit for any given sample. All three registers clock low bits if the differential input voltage is between defined state voltage bands. A word gap Null requires at least three consecutive Null samples (three high bits) in the upper half of the Null sampling shift register and at least three consecutive Null samples (three high bits) in the lower half of the Null sampling shift register. This guarantees the minimum pulse width. RINB-40 BIT RATE PULSE RISE TIME PULSE FALL TIME PULSE WIDTH 1. An accurate 1MHz clock source is required to validate the receive signal timing. Less than 1% error is recommended. HIGH SPEED LOW SPEED 83K BPS 125K BPS 10.4K BPS 15.6K BPS 4. Following the last data bit of a valid reception, the Word Gap timer samples the Null shift register every 10 input clocks (every 80 clocks for low speed). If a Null is present, the Word Gap counter is incremented. A Word Gap count of 3 enables the next reception. LOW SPEED 12K -14.5K BPS 10 ± 5 µsec 10 ± 5 µsec 34.5 to 41.7 µsec HOLT INTEGRATED CIRCUITS 5 HI-3588 FUNCTIONAL DESCRIPTION (cont.) CS 32 X 32 RFLAG FIFO LOAD CONTROL SI SPI INTERFACE FIFO SO SCK / CONTROL BITS CR2, CR6-8 LABEL / DECODE COMPARE CONTROL BITS CR0, CR1 CLOCK OPTION ACLK CLOCK 256-BIT LABEL LOOK-UP TABLE 32 BIT SHIFT REGISTER DATA PARITY CHECK 32ND BIT BIT COUNTER AND END OF SEQUENCE BIT CLOCK EOS ONES WORD GAP TIMER WORD GAP SHIFT REGISTER BIT CLOCK END NULL SHIFT REGISTER ZEROS SHIFT REGISTER START SEQUENCE CONTROL ERROR ERROR DETECTION FIGURE 2. CLOCK RECEIVER BLOCK DIAGRAM RECEIVER PARITY CR4 The Receiver Parity Check Enable bit (Control Register bit 4, CR4) controls how the 32nd bit of the received ARINC word is interpreted by the HI-3585 receiver. ARINC BUS 32nd bit FIFO 32nd bit 0 data data 1 parity bit Error Bit: When CR4 is set to a “0”, the 32nd bit is treated as data and transferred as received from the ARINC bus to the receive FIFO. When CR4 is set to a “1”, the 32nd bit is treated as a parity error bit. Odd Parity Received The receiver expects the 32nd bit of the received word to indicate odd parity. If this is the case, the parity bit is reset to indicate correct parity was received and resulting word is written to the receive FIFO. Even Parity Received If the received word is even parity, the receiver sets the 32nd bit to a “1”, indicating a parity error. The resulting word is then written to the receive FIFO. Therefore, when CR4 is set to “1”, the 32nd bit retrieved from the receiver FIFO will always be “0” when valid (odd parity) ARINC 429 words are received. HOLT INTEGRATED CIRCUITS 6 0 = odd parity 1= odd parity error (even parity) HI-3588 FUNCTIONAL DESCRIPTION (cont.) RETRIEVING DATA LABEL RECOGNITION Once 32 valid bits are recognized, the receiver logic generates an End of Sequence (EOS). Depending on the state of Control Register bits CR2, and CR6 through CR8, the received 32-bit ARINC word is then checked for correct decoding and label match before it is loaded into the 32 x 32 Receive FIFO. ARINC words that do not match required 9th and 10th ARINC bit and do not have a label match are ignored and are not loaded into the Receive FIFO. The table below describes this operation. The user loads the 256-bit label look-up table to specify which 8-bit incoming ARINC labels are captured by the receiver, and which are discarded. Setting a “1” in the look-up table enables processing of received ARINC words containing the corresponding label. A “0” in the look-up table causes discard of received ARINC words containing the label. The 256-bit look-up table is loaded using SPI op codes 02 hex, 03 hex or 06 hex, as described in Table 1. After the look-up table is initialized, set Control Register bit CR2 to enable label recognition. Once a valid ARINC word is loaded into the FIFO, the EOS signal clocks the Data Ready flip-flop to a "1" and Status Register bit 0 (SR0) to a “0”. The SR0 bit remains low until the Receive FIFO is empty. Each received ARINC word is retrieved via the SPI interface using SPI instruction 08 hex to read a single word. Up to 32 ARINC words may be held in the Receive FIFO. Status register bit 2 (SR2) goes high when the Receive FIFO is full. Failure to unload the Receive FIFO when full causes additional received valid ARINC words to overwrite Receive FIFO location 32. A FIFO half-full flag (SR1) is high when the Receive FIFO contains 16 or more ARINC words. SR1 may be interrogated by the system’s external microprocessor, allowing a 16 word data retrieval routine to be performed. CR2 ARINC word matches Enabled label CR6 ARINC word bits 10, 9 match CR7,8 FIFO 0 X 0 X Load FIFO 1 No 0 X Ignore data 1 Yes 0 X Load FIFO 0 X 1 No Ignore data 0 X 1 Yes Load FIFO 1 Yes 1 No Ignore data 1 No 1 Yes Ignore data 1 No 1 No Ignore data 1 Yes 1 Yes Load FIFO If label recognition is enabled, the receiver compares the label in each new ARINC word against the stored look-up table. If a label match is found, the received word is processed. If no match occurs, the new ARINC word is discarded and no indicators of received ARINC data are presented. READING THE LABEL LOOK-UP TABLE The contents of the Label Look-up table may be read via the SPI interface using instruction 0D hex as described in Table 1. LINE RECEIVER INPUT PINS The HI-3588 has two sets of Line Receiver input pins, RINA/B and RINA/B-40. Only one pair may be used to connect to the ARINC 429 bus. The unused pair must be left floating. The RINA/B pins may be connected directly to the ARINC 429 bus. The RINA/B-40 pins require external 40K ohm resistors in series with each ARINC input. These do not affect the ARINC receiver thresholds. By keeping excessive voltage outside the device, this option is helpful in applications where lightning protection is required. When using the RINA/B-40 pins, each side of the ARINC bus must be connected through a 40K ohm series resistor in order for the chip to detect the correct ARINC levels. The typical 10 Volt differential signal is translated and input to a window comparator and latch. The comparator levels are set so that with the external 40K ohm resistors, they are just below the standard 6.5 volt minimum ARINC data threshold and just above the standard 2.5 volt maximum ARINC null threshold. Please refer to the Holt AN-300 Application Note for additional information and recommendations on lightning protection of Holt line drivers and line receivers. MASTER RESET (MR) Assertion of Master Reset causes immediate termination of data reception. The receive FIFO, Status Register FIFO flags and the FIFO status RFLAG pin is also cleared. The Control Register is not affected by Master Reset. HOLT INTEGRATED CIRCUITS 7 HI-3588 TIMING DIAGRAMS SERIAL INPUT TIMING DIAGRAM t CPH t CYC CS tCHH t SCKF t CES t CEH SCK t DS t SCKR t DH SI MSB LSB SERIAL OUTPUT TIMING DIAGRAM t CPH t CYC CS t SCKH tSCKL SCK t CHZ t DV SO MSB Hi Impedance LSB Hi Impedance * Above diagram does not apply for op code instruction 09hex DATA RATE - EXAMPLE PATTERN TXAOUT ARINC BIT TXBOUT NULL DATA DATA DATA NULL WORD GAP BIT 32 BIT 31 BIT 30 NULL BIT 1 NEXT WORD RECEIVER OPERATION ARINC DATA BIT 31 BIT 32 RFLAG tRFLG tRXR tSPIF CS SPI INSTRUCTION 08h SI ARINC BIT 32 ARINC BIT 31 ARINC BIT 30 SO HOLT INTEGRATED CIRCUITS 8 ARINC BIT 1 HI-3588 ABSOLUTE MAXIMUM RATINGS Supply Voltages VDD ......................................... -0.3V to +7.0V Power Dissipation at 25°C Plastic Quad Flat Pack ..................1.5 W, derate 10mW/°C Voltage at pins RINA, RINB ............................... -120V to +120V DC Current Drain per pin .............................................. ±10mA Voltage at any other pin ............................... -0.3V to VDD +0.3V Storage Temperature Range ........................ -65°C to +150°C Solder temperature (Leads) .................... 280°C for 10 seconds (Package) .......................................... 260°C Operating Temperature Range (Industrial): .... -40°C to +85°C (Hi-Temp): .....-55°C to +125°C NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS VDD = 3.3V or 5.0V , GND = 0V, TA = Operating Temperature Range (unless otherwise specified). LIMITS PARAMETER ARINC INPUTS - SYMBOL CONDITIONS UNIT MIN TYP MAX 6.5 -13.0 -2.5 10.0 -10.0 0 13.0 -6.5 2.5 V V V 140 140 100 - KW KW KW 200 µA µA 20 20 20 pF pF pF 20% VDD V V Pins RINA, RINB, RINA-40 (with external 40KOhms), RINB-40 (with external 40KOhms) Differential Input Voltage: (RINA to RINB) Input Resistance: ONE ZERO NULL VIH VIL VNUL Common mode voltages less than ±30V with respect to GND Differential To GND To VDD RI RG RH - Input Sink Input Source IIH IIL -450 Differential To GND To VDD CI CG CH Input Voltage HI Input Voltage LO VIH VIL Input Sink Input Source Pull-down Current (MR, SI, SCK, ACLK pins) Pull-up Current (CS Pin) IIH IIL IPD IPU Input Current: Input Capacitance: (Guaranteed but not tested) (RINA to RINB) LOGIC INPUTS Input Voltage: Input Current: 80% VDD 1.5 -1.5 250 -600 600 -300 µA µA µA µA 10% VDD V V -1.0 mA mA LOGIC OUTPUTS Output Voltage: Output Current: (All Outputs & Bi-directional Pins) Output Capacitance: Logic "1" Output Voltage Logic "0" Output Voltage VOH VOL IOH = -100µA IOL = 1.0mA 90%VDD Output Sink Output Source IOL IOH VOUT = 0.4V VOUT = VDD - 0.4V 1.6 CO 15 pF Operating Voltage Range VDD 3.15 5.25 V 7 mA Operating Supply Current VDD IDD HOLT INTEGRATED CIRCUITS 9 2.5 HI-3588 AC ELECTRICAL CHARACTERISTICS VDD = 3.3V or 5.0V, GND = 0V, TA = Operating Temperature Range and fclk=1MHz +0.1% with 60/40 duty cycle LIMITS PARAMETER SYMBOL UNITS MIN TYP MAX SPI INTERFACE TIMING - 5.0V SCK clock period CS active after last SCK rising edge CS setup time to first SCK rising edge CS hold time after last SCK falling edge CS inactive between SPI instructions SPI SI Data set-up time to SCK rising edge SPI SI Data hold time after SCK rising edge SCK rise time SCK fall ime SO valid after SCK falling edge SO high-impedance after SCK falling edge Master Reset pulse width tCYC tCHH tCES tCEH tCPH tDS tDH tSCKR tSCKF tDV tCHZ tMR 250 10 10 40 20 25 15 10 10 125 100 150 ns ns ns ns ns ns ns ns ns ns ns ns SPI INTERFACE TIMING - 3.3V SCK clock period CS active after last SCK rising edge CS setup time to first SCK rising edge CS hold time after last SCK falling edge CS inactive between SPI instructions SPI SI Data set-up time to SCK rising edge SPI SI Data hold time after SCK rising edge SCK rise time SCK fall ime SO valid after SCK falling edge SO high-impedance after SCK falling edge Master Reset pulse width tCYC tCHH tCES tCEH tCPH tDS tDH tSCKR tSCKF tDV tCHZ tMR 390 10 10 40 35 30 30 10 10 195 100 150 ns ns ns ns ns ns ns ns ns ns ns ns RECEIVER TIMING Delay - Last bit of received ARINC word to RFLAG(Full or Empty) - Hi Speed Delay - Last bit of received ARINC word to RFLAG(Full or Empty) - Lo Speed Received data available to SPI interface. RFLAG to CS active SPI receiver read or clear FIFO instruction to RFLAG tRFLG tRFLG tRXR tSPIF HOLT INTEGRATED CIRCUITS 10 16 126 0 155 µs µs ns ns HI-3588 ORDERING INFORMATION HI - 3588 xx x x PART NUMBER Blank LEAD FINISH Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free, RoHS compliant) F PART NUMBER TEMPERATURE RANGE FLOW BURN IN I -40°C TO +85°C I No T -55°C TO +125°C T No PART NUMBER PACKAGE DESCRIPTION PC 44 PIN PLASTIC CHIP-SCALE, QFN (44PCS) PQ 44 PIN PLASTIC QUAD FLAT PACK, PQFP (44PMQS) HOLT INTEGRATED CIRCUITS 11 HI-3588 REVISION HISTORY P/N Rev DS3588 NEW A B C D E F G Date 05/08/08 10/10/08 05/22/09 07/02/09 02/03/10 04/20/10 05/19/10 07/24/12 Description of Change Initial Release Revised AC Electrical Characteristics. Clarified relationship between SPI bit order and the ARINC 429 bit order. Removed references to V+, V-, which are not connected in this device Clarified op code 09hex description. Removed op code 09hex. Corrected ARINC receiver nomenclature. Clarified the description of receiver parity. Updated PQFP package drawing. Updated QFN package drawing and clarified heat sink connection. Corrected typo in clock source tolerance on p. 5 from 0.1% to 1%. Updated SPI Interface Timing at 5.0V and 3.3V. Updated Maximum Ratings table, Solder Temperature (package) from 220C to 260C. HOLT INTEGRATED CIRCUITS 12 HI-3588 PACKAGE DIMENSIONS inches (millimeters) 44-PIN PLASTIC CHIP-SCALE PACKAGE Package Type: 44PCS .276 BSC (7.00) .216 ± .002 (5.5 ± .05) .020 BSC (0.50) .276 BSC (7.00) .216 ± .002 (5.5 ± .05) Top View Bottom View .010 (0.25) typ .039 max (1.00) .008 typ (0.2) .016 ± .002 (0.40 ± .05) Electrically isolated heat sink pad on bottom of package. Connect to any ground or power plane for optimum thermal dissipation. BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) inches (millimeters) 44-PIN PLASTIC QUAD FLAT PACK (PQFP) Package Type: 44PMQS .009 MAX. (.23) .0315 BSC (.80) .394 ± .004 (10.0 ± .10) SQ. .520 ± .010 (13.20 ± .25) SQ. .014 ± .003 (.37 ± .08) .035 ± .006 (.88 ± .15) .012 R MAX. (.30) See Detail A .096 MAX. (2.45) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) .079 ± .008 (2.0 ± .20) .005 R MIN. Detail A (.13) HOLT INTEGRATED CIRCUITS 13 0° £ Q £ 7°