HI-3582, HI-3583 ARINC 429 3.3V Terminal IC August 2013 GENERAL DESCRIPTION APPLICATIONS • Avionics data communication • Serial to parallel conversion • Parallel to serial conversion PIN CONFIGURATIONS (Top View) (See page 14 for additional pin configuration) See Note below 64 - N/C 63 - RIN2B 62 - RIN2A 61 - RIN1B 60 - RIN1A 59 - N/C 58 - VDD 57 - VDD 56 - VDD 55 - N/C 54 - TEST 53 - MR 52 - TXCLK 51 - CLK 50 - RSR 49 - N/C The HI-3582/HI-3583 from Holt Integrated Circuits are silicon gate CMOS devices for interfacing a 16-bit parallel data bus directly to the ARINC 429 serial bus. The HI-3582/HI-3583 design offers many enhancements to the industry standard HI-8282 architecture. The device provides two receivers each with label recognition, 32 by 32 FIFO, and analog line receiver. Up to 16 labels may be programmed for each receiver. The independent transmitter has a 32 X 32 FIFO and a built-in line driver. The status of all three FIFOs can be monitored using the external status pins, or by polling the HI-3582/HI-3583 status register. Other new features include a programmable option of data or parity in the 32nd bit, and the ability to unscramble the 32 bit word. Also, versions are available with different values of input resistance and output resistance to allow users to more easily add external lightning protection circuitry. N/C - 1 D/R1 - 2 FF1 - 3 HF1 - 4 D/R2 - 5 FF2 - 6 HF2 - 7 SEL - 8 EN1 - 9 EN2 - 10 N/C - 11 BD15 - 12 BD14 - 13 BD13 - 14 BD12 - 15 BD11 - 16 The HI-3582/HI-3583 apply the ARINC protocol to the receivers and transmitter. Timing is based on a 1 Megahertz clock. 48 - CWSTR 47 - ENTX 46 - N/C 45 - V+ 44 - TXBOUT 43 - TXAOUT 42 - V41 - N/C 40 - FFT 39 - HFT 38 - TX/R 37 - PL2 36 - PL1 35 - BD00 34 - BD01 33 - N/C N/C - 17 BD10 - 18 BD09 - 19 BD08 - 20 BD07 - 21 BD06 - 22 GND - 23 N/C - 24 N/C - 25 N/C - 26 N/C - 27 BD05 - 28 BD04 - 29 BD03 - 30 BD02 - 31 N/C - 32 The 16-bit parallel data bus exchanges the 32-bit ARINC data word in two steps when either loading the transmitter or interrogating the receivers. The databus and all control signals are CMOS and TTL compatible. HI-3582PCI HI-3582PCT HI-3582PCM & HI-3583PCI HI-3583PCT HI-3583PCM (Note: All 3 VDD pins must be connected to the same 3.3V supply) 64 - Pin Plastic 9mm x 9mm Chip-Scale Package (QFN) 52 - D/R1 51 - RIN2B 50 - RIN2A 49 - RIN1B 48 - RIN1A 47 - VDD 46 - N/C 45 - TEST 44 - MR 43 - TXCLK 42 - CLK 41 - RSR 40 - N/C Although the line driver shares a common substrate with the receivers, the design of the physical isolation does not allow parasitic crosstalk, and thereby achieves the same isolation as common hybrid layouts. FEATURES • ARINC specification 429 compatible ((DS3582 Rev. K) FF1 - 1 HF1 - 2 D/R2 - 3 FF2 - 4 HF2 - 5 SEL - 6 EN1 - 7 EN2 - 8 BD15 - 9 BD14 - 10 BD13 - 11 BD12 - 12 BD11 - 13 HI-3582PQI HI-3582PQT HI-3582PQM & HI-3583PQI HI-3583PQT HI-3583PQM 39 - N/C 38 - CWSTR 37 - ENTX 36 - V+ 35 - TXBOUT 34 - TXAOUT 33 - V32 - FFT 31 - HFT 30 - TX/R 29 - PL2 28 - PL1 27 - BD00 BD10 - 14 BD09 - 15 BD08 - 16 BD07 - 17 BD06 - 18 N/C - 19 GND - 20 N/C - 21 BD05 - 22 BD04 - 23 BD03 - 24 BD02 - 25 BD01 - 26 • 3.3V logic supply operation • Dual receiver and transmitter interface • Analog line driver and receivers connect directly to ARINC bus • Programmable label recognition • On-chip 16 label memory for each receiver • 32 x 32 FIFOs each receiver and transmitter • Independent data rate selection for Transmitter and each receiver • Status register • Data scramble control • 32nd transmit bit can be data or parity • Self test mode • Low power • Industrial & extended temperature ranges 52 - Pin Plastic Quad Flat Pack (PQFP) HOLT INTEGRATED CIRCUITS www.holtic.com 08/13 HI-3582, HI-3583 PIN DESCRIPTIONS SIGNAL FUNCTION VDD RIN1A RIN1B RIN2A RIN2B D/R1 FF1 HF1 D/R2 FF2 HF2 SEL EN1 EN2 BD15 BD14 BD13 BD12 BD11 BD10 BD09 BD08 BD07 BD06 GND BD05 BD04 BD03 BD02 BD01 BD00 PL1 PL2 TX/R POWER INPUT INPUT INPUT INPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT INPUT INPUT INPUT I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O POWER I/O I/O I/O I/O I/O I/O INPUT INPUT OUTPUT +3.3V power supply pin ARINC receiver 1 positive input ARINC receiver 1 negative input ARINC receiver 2 positive input ARINC receiver 2 negative input Receiver 1 data ready flag FIFO full Receiver 1 FIFO Half full, Receiver 1 Receiver 2 data ready flag FIFO full Receiver 2 FIFO Half full, Receiver 2 Receiver data byte selection (0 = BYTE 1) (1 = BYTE 2) Data Bus control, enables receiver 1 data to outputs Data Bus control, enables receiver 2 data to outputs if EN1 is high Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus 0V Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Latch enable for byte 1 entered from data bus to transmitter FIFO. Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow PL1. Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high after transmission and FIFO empty. DESCRIPTION HFT FFT VTXAOUT TXBOUT V+ ENTX CWSTR RSR CLK TX CLK MR TEST OUTPUT OUTPUT POWER OUTPUT OUTPUT POWER INPUT INPUT INPUT INPUT OUTPUT INPUT INPUT Transmitter FIFO Half Full Transmitter FIFO Full -9.5V to -10.5V Line driver output - A side Line driver output - B side +9.5V to +10.5V Enable Transmission Clock for control word register Read Status Register if SEL=0, read Control Register if SEL=1 Master Clock input Transmitter Clock equal to Master Clock (CLK), divided by either 10 or 80. Master Reset, active low Disable Transmitter output if high (pull-down) HOLT INTEGRATED CIRCUITS 2 HI-3582, HI-3583 FUNCTIONAL DESCRIPTION CONTROL WORD REGISTER STATUS REGISTER The HI-3582/HI-3583 contain a 16-bit control register which is used to configure the device. The control register bits CR0 - CR15 are loaded from BD00 - BD15 when CWSTR is pulsed low. The control register contents are output on the databus when SEL = 1 and RSR is pulsed low. Each bit of the control register has the following function: The HI-3582/HI-3583 contain a 9-bit status register which can be interrogated to determine the status of the ARINC receivers, data FIFOs and transmitter. The contents of the status register are output on BD00 - BD08 when the RSR pin is taken low and SEL = 0. Unused bits are output as Zeros. The following table defines the status register bits. CR Bit CR0 CR1 CR2 CR3 CR4 CR5 CR6 FUNCTION STATE DESCRIPTION SR Bit Receiver 1 Data clock Select 0 Data rate = CLK/10 SR0 1 Data rate = CLK/80 Label Memory Read / Write 0 Normal operation 1 Load 16 labels using PL1 / PL2 Read 16 labels using EN1 / EN2 Enable Label Recognition (Receiver 1) 0 Disable label recognition 1 Enable label recognition Enable Label Recognition (Receiver 2) 0 Disable Label Recognition 1 Enable Label recognition Enable 32nd bit as parity 0 Transmitter 32nd bit is data 1 Transmitter 32nd bit is parity Self Test 0 The transmitter’s digital outputs are internally connected to the receiver logic inputs 1 Normal operation 0 Receiver 1 decoder disabled 1 ARINC bits 9 and 10 must match CR7 and CR8 Receiver 1 decoder SR1 SR2 SR3 SR4 CR7 - - If receiver 1 decoder is enabled, the ARINC bit 9 must match this bit CR8 - - If receiver 1 decoder is enabled, the ARINC bit 10 must match this bit CR9 Receiver 2 Decoder 0 Receiver 2 decoder disabled 1 ARINC bits 9 and 10 must match CR10 and CR11 - If receiver 2 decoder is enabled, the ARINC bit 9 must match this bit SR5 SR6 CR10 - CR11 - - If receiver 2 decoder is enabled, the ARINC bit 10 must match this bit CR12 Invert Transmitter parity 0 Transmitter 32nd bit is Odd parity 1 Transmitter 32nd bit is Even parity Transmitter data clock select 0 Data rate=CLK/10, O/P slope=1.5us 1 Data rate=CLK/80, O/P slope=10us Receiver 2 data clock select 0 Data rate=CLK/10 1 Data rate=CLK/80 Data format 0 Scramble ARINC data 1 Unscramble ARINC data CR13 CR14 CR15 SR7 SR8 FUNCTION STATE Data ready (Receiver 1) 0 Receiver 1 FIFO empty 1 Receiver 1 FIFO contains valid data Resets to zero when all data has been read. D/R1 pin is the inverse of this bit 0 Receiver 1 FIFO holds less than 16 words 1 Receiver 1 FIFO holds at least 16 words. HF1 pin is the inverse of this bit. 0 Receiver 1 FIFO not full 1 Receiver 1 FIFO full. To avoid data loss, the FIFO must be read within one ARINC word period. FF1 pin is the inverse of this bit 0 Receiver 2 FIFO empty 1 Receiver 2 FIFO contains valid data Resets to zero when all data has been read. D/R2 pin is the inverse of this bit 0 Receiver 2 FIFO holds less than 16 words 1 Receiver 2 FIFO holds at least 16 words. HF2 pin is the inverse of this bit. 0 Receiver 2 FIFO not full 1 Receiver 2 FIFO full. To avoid data loss, the FIFO must be read within one ARINC word period. FF2 pin is the inverse of this bit 0 Transmitter FIFO not empty 1 Transmitter FIFO empty. 0 Transmitter FIFO not full 1 Transmitter FIFO full. FFT pin is the inverse of this bit. 0 Transmitter FIFO contains less than 16 words 1 Transmitter FIFO contains at least 16 words.HFT pin is the inverse of this bit. FIFO half full (Receiver 1) FIFO full (Receiver 1) Data ready (Receiver 2) FIFO half full (Receiver 2) FIFO full (Receiver 2) Transmitter FIFO empty Transmitter FIFO full Transmitter FIFO half full HOLT INTEGRATED CIRCUITS 3 DESCRIPTION HI-3582, HI-3583 FUNCTIONAL DESCRIPTION (cont.) The HI-3582/HI-3583 guarantee recognition of these levels with a common mode Voltage with respect to GND less than ±4V for the worst case condition (3.0V supply and 13V signal level). ARINC 429 DATA FORMAT Control register bit CR15 is used to control how individual bits in the received or transmitted ARINC word are mapped to the HI-3582/ HI-3583 data bus during data read or write operations. The following table describes this mapping: BYTE 1 The tolerances in the design guarantee detection of the above levels, so the actual acceptance ranges are slightly larger. If the ARINC signal is out of the actual acceptance ranges, including the nulls, the chip rejects the data. RECEIVER LOGIC OPERATION ARINC BIT CR15=0 13 12 11 10 ARINC BIT CR15=1 16 15 14 13 12 11 10 Label Label Label 9 8 7 6 5 4 3 2 1 Label Label Label SDI Label BIT TIMING Label Figure 2 shows a block diagram of the logic section of each receiver. Label 8 Label 7 Label 6 Label 5 Label 4 Label 3 Label 2 Label 1 Parity 31 30 32 SDI 9 SDI SDI BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 DATA BUS BYTE 2 BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 ARINC BIT CR15=0 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 ARINC BIT CR15=1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Parity DATA BUS The ARINC 429 specification contains the following timing specification for the received data: HIGH SPEED LOW SPEED 100K BPS ± 1% 12K -14.5K BPS BIT RATE 10 ± 5 µsec PULSE RISE TIME 1.5 ± 0.5 µsec 10 ± 5 µsec PULSE FALL TIME 1.5 ± 0.5 µsec 5 µsec ± 5% 34.5 to 41.7 µsec PULSE WIDTH The HI-3582/HI-3583 accept signals that meet these specifications and rejects signals outside the tolerances. The way the logic operation achieves this is described below: 1. Key to the performance of the timing checking logic is an accurate 1MHz clock source. Less than 0.1% error is recommended. THE RECEIVERS ARINC BUS INTERFACE Figure 1 shows the input circuit for each receiver. The ARINC 429 specification requires the following detection levels: STATE ONE NULL ZERO DIFFERENTIAL VOLTAGE +6.5 Volts to +13 Volts +2.5 Volts to -2.5 Volts -6.5 Volts to -13 Volts vDD DIFFERENTIAL AMPLIFIERS RIN1A OR RIN2A 3. Each data bit must follow its predecessor by not less than 8 samples and no more than 12 samples. In this manner the bit rate is checked. With exactly 1MHz input clock frequency, the acceptable data bit rates are as follows: COMPARATORS ONES vDD GND NULL ZEROES RIN1B OR RIN2B 2. The sampling shift registers are 10 bits long and must show three consecutive Ones, Zeros or Nulls to be considered valid data. Additionally, for data bits, the One or Zero in the upper bits of the sampling shift registers must be followed by a Null in the lower bits within the data bit time. For a Null in the word gap, three consecutive Nulls must be found in both the upper and lower bits of the sampling shift register. In this manner the minimum pulse width is guaranteed. DATA BIT RATE MIN DATA BIT RATE MAX HIGH SPEED LOW SPEED 83K BPS 125K BPS 10.4K BPS 15.6K BPS 4. The Word Gap timer samples the Null shift register every 10 input clocks (80 for low speed) after the last data bit of a valid reception. If the Null is present, the Word Gap counter is incremented. A count of 3 will enable the next reception. GND FIGURE 1. ARINC RECEIVER INPUT HOLT INTEGRATED CIRCUITS 4 HI-3582, HI-3583 FUNCTIONAL DESCRIPTION (cont.) RECEIVER PARITY RETRIEVING DATA The 32nd bit of received ARINC words stored in the receive FIFO is used as a Parity Flag indicating whether good Odd parity is received from the incoming ARINC word. Once 32 valid bits are recognized, the receiver logic generates an End of Sequence (EOS). Depending upon the state of control register bits CR2-CR11, the received ARINC 32-bit word is then checked for correct decoding and label matching before being loaded into the 32 x 32 receive FIFO. ARINC words which do not meet the necessary 9th and 10th ARINC bit or label matching are ignored and are not loaded into the receive FIFO. The following table describes this operation. Odd Parity Received The parity bit is reset to indicate correct parity was received and the resulting word is written to the receive FIFO. Even Parity Received The receiver sets the 32nd bit to a “1”, indicating a parity error and the resulting word is then written to the receive FIFO. Therefore, the 32nd bit retrieved from the receiver FIFO will always be “0” when valid (odd parity) ARINC 429 words are received. CR2(3) ARINC word CR6(9) ARINC word matches bits 9,10 label match CR7,8 (10,11) FIFO 0 X 0 X Load FIFO 1 No 0 X Ignore data 1 Yes 0 X Load FIFO 0 X 1 No Ignore data 0 X 1 Yes Load FIFO 1 Yes 1 No Ignore data 1 No 1 Yes Ignore data 1 No 1 No Ignore data 1 Yes 1 Yes Load FIFO HOLT INTEGRATED CIRCUITS 5 HI-3582, HI-3583 FUNCTIONAL DESCRIPTION (cont.) TO PINS SEL EN MUX CONTROL 32 TO 16 DRIVER CONTROL BITS R/W CONTROL HF FF D/R 32 X 32 FIFO LOAD CONTROL FIFO / CONTROL BIT LABEL / DECODE COMPARE CLOCK OPTION CONTROLBITS CR0, CR14 CLK CLOCK 16 x 8 LABEL MEMORY 32 BIT SHIFT REGISTER DATA PARITY CHECK 32ND BIT BIT COUNTER AND END OF SEQUENCE BIT CLOCK EOS ONES WORD GAP SHIFT REGISTER WORD GAP TIMER BIT CLOCK END START NULL SHIFT REGISTER ZEROS SHIFT REGISTER SEQUENCE CONTROL ERROR ERROR DETECTION FIGURE 2. RECEIVER BLOCK DIAGRAM HOLT INTEGRATED CIRCUITS 6 CLOCK HI-3582, HI-3583 FUNCTIONAL DESCRIPTION (cont.) Once a valid ARINC word is loaded into the FIFO, then EOS clocks the data ready flag flip flop to a "1", D/R1 or D/R2 (or both) will go low. The data flag for a receiver will remain low until both ARINC bytes from that receiver are retrieved and the FIFO is empty. This is accomplished by first activating EN with SEL, the byte selector, low to retrieve the first byte and then activating EN with SEL high to retrieve the second byte. EN1 retrieves data from receiver 1 and EN2 retrieves data from receiver 2. READING LABELS After the write that changes CR1 from 0 to 1, the next 16 data reads of the selected receiver (EN taken low) are labels. EN1 is used to read labels for receiver 1, and EN2 to read labels for receiver 2. Label data is presented on BD0-BD7. When writing to, or reading from the label memory, SEL must be a one, all 16 locations should be accessed, and CR1 must be written to zero before returning to normal operation. Label recognition must be disabled (CR2/3=0) during the label read sequence. Up to 32 ARINC words may be loaded into each receiver’s FIFO. The FF1 (FF2) pin will go low when the receiver 1 (2) FIFO is full. Failure to retrieve data from a full FIFO will cause the next valid ARINC word received to overwrite the existing data in FIFO location 32. A FIFO half full flag HF1 (HF2) goes low if the FIFO contains 16 or more received ARINC words. The HF1 (HF2) pin is intended to act as an interrupt flag to the system’s external microprocessor, allowing a 16 word data retrieval routine to be performed, without the user needing to continually poll the HI-8582/HI-8583 status register bits. TRANSMITTER FIFO OPERATION The FIFO is loaded sequentially by first pulsing PL1 to load byte 1 and then PL2 to load byte 2. The control logic automatically loads the 31 bit word (or 32 bit word if CR4=0) in the next available position of the FIFO. If TX/R, the transmitter ready flag is high (FIFO empty), then up to 32 words, each 31 or 32 bits long, may be loaded. If TX/R is low, then only the available positions may be loaded. If all 32 positions are full, the FFT flag is asserted and the FIFO ignores further attempts to load data. LABEL RECOGNITION The chip compares the incoming label to the stored labels if label recognition is enabled. If a match is found, the data is processed. If a match is not found, no indicators of receiving ARINC data are presented. Note that 00(Hex) is treated in the same way as any other label value. Label bit significance is not changed by the status of control register bit CR15. Label bits BD00 - BD07 are always compared to received ARINC bits 1 - 8 respectively. A transmitter FIFO half-full flag HFT is provided. When the transmit FIFO contains less than 16 words, HFT is high, indicating to the system microprocessor that a 16 ARINC word block write sequence can be initiated. LOADING LABELS In normal operation (CR4=1), the 32nd bit transmitted is a parity bit. Odd or even parity is selected by programming control register bit CR12 to a zero or one. If CR4 is programmed to a 0, then all 32-bits of data loaded into the transmitter FIFO are treated as data and are transmitted. After a write that takes CR1 from 0 to 1, the next 16 writes of data (PL pulsed low) load label data into each location of the label memory from the BD00 - BD07 pins. The PL1 pin is used to write label data for receiver 1 and PL2 for receiver 2. Note that ARINC word reception is suspended during the label memory write sequence. CR4,12 32 BIT PARALLEL LOAD SHIFT REGISTER BIT CLOCK PARITY GENERATOR DATA AND NULL TIMER SEQUENCER LINE DRIVER TXAOUT TXBOUT TEST BIT AND WORD GAP COUNTER WORD CLOCK 32 x 32 FIFO START SEQUENCE ADDRESS TX/R WORD COUNTER AND FIFO CONTROL LOAD HFT FFT ENTX INCREMENT WORD COUNT FIFO LOADING SEQUENCER PL1 PL2 DATA BUS DATA CLOCK CR13 FIGURE 3. DATA CLOCK DIVIDER TRANSMITTER BLOCK DIAGRAM HOLT INTEGRATED CIRCUITS 7 CLK TX CLK HI-3582, HI-3583 FUNCTIONAL DESCRIPTION (cont.) DATA TRANSMISSION When ENTX goes high, enabling transmission, the FIFO positions are incremented with the top register loading into the data transmission shift register. Within 2.5 data clocks the first data bit appears at TXAOUT and TXBOUT. The 31 or 32 bits in the data transmission shift register are presented sequentially to the outputs in the ARINC 429 format with the following timing: ARINC DATA BIT TIME DATA BIT TIME NULL BIT TIME WORD GAP TIME HIGH SPEED 10 Clocks 5 Clocks 5 Clocks 40 Clocks LOW SPEED 80 Clocks 40 Clocks 40 Clocks 320 Clocks The word counter detects when all loaded positions have been transmitted and sets the transmitter ready flag, TX/R, high. The HI-3582 has 37.5 ohms in series with each line driver output. The HI-3583 has 10 ohms in series. The HI-3583 is for applications where external series resistance is needed, typically for lightning protection devices. REPEATER OPERATION Repeater mode of operation allows a data word that has been received by the HI-3582/HI-3583 to be placed directly into the transmitter FIFO. Repeater operation is similar to normal receiver operation. In normal operation, either byte of a received data word may be read from the receiver latches first by use of SEL input. During repeater operation however, the lower byte of the data word must be read first. This is necessary because, as the data is being read, it is also being loaded into transmitter FIFO which is always loaded with the lower byte of the data word first. Signal flow for repeater operation is shown in the Timing Diagrams section. TRANSMITTER PARITY HI-3582-10 and HI-3583-10 The parity generator counts the Ones in the 31-bit word. If control register bit CR12 is set low, the 32nd bit transmitted will make parity odd. If the control bit is high, the parity is even. Setting CR4 to a Zero bypasses the parity generator, and allows 32 bits of data to be transmitted. The HI-3582-10/HI-3583-10 options are similar to the HI-3582/ HI-3583 with the exception that they allow an external 10 Kohm resistor to be added in series with each ARINC input without affecting the ARINC input thresholds. This option is especially useful in applications where lightning protection circuitry is also required. SELF TEST If control register bit CR5 is set low, the transmitter serial output data are internally connected to each of the two receivers, bypassing the analog interface circuitry. Data is passed unmodified to receiver 1 and inverted to receiver 2. Taking TEST high forces TXAOUT and TXBOUT into the null state regardless of the state of CR5. SYSTEM OPERATION The two receivers are independent of the transmitter. Therefore, control of data exchanges is strictly at the option of the user. The only restrictions are: 1. The received data will be overwritten if the receiver FIFO is full and at least one location is not retrieved before the next complete ARINC word is received. 2. The transmitter FIFO can store 32 words maximum and ignores attempts to load additional data if full. Each side of the ARINC bus must be connected through a 10 Kohm series resistor in order for the chip to detect the correct ARINC levels. The typical 10 volt differential signal is translated and input to a window comparator and latch. The comparator levels are set so that with the external 10 Kohm resistors, they are just below the standard 6.5 volt minimum ARINC data threshold and just above the standard 2.5 volt maximum ARINC null threshold. Please refer to the Holt AN-300 Application Note for additional information and recommendations on lightning protection of Holt line drivers and line receivers. HIGH SPEED OPERATION The HI-3582 and HI-3583 may be operated at clock frequencies beyond that required for ARINC compliant operation. For operation at Master Clock (CLK) frequencies up to 5MHz, please contact Holt applications engineering. POWER SUPPLY SEQUENCING LINE DRIVER OPERATION The line driver in the HI-8582/HI-8583 are designed to directly drive the ARINC 429 bus. The two ARINC outputs (TXAOUT and TXBOUT) provide a differential voltage to produce a +10 volt One, a -10 volt Zero, and a 0 volt Null. Control register bit CR13 controls both the transmitter data rate, and the slope of the differential output signal. No additional hardware is required to control the slope. Programming CR13 to Zero causes a 100 kbits/s data rate and a slope of 1.5 µs on the ARINC outputs; a One on CR13 causes a 12.5 kbit/s data rate and a slope of 10 µs. Timing is set by on-chip resistor and capacitor and tested to be within ARINC requirements. The power supplies should be controlled to prevent large currents during supply turn-on and turn-off. The recommended sequence is V+ followed by VDD, always ensuring that V+ is the most positive supply. The V- supply is not critical and can be asserted at any time. MASTER RESET (MR) On a Master Reset data transmission and reception are immediately terminated, all three FIFOs are cleared as are the FIFO flags at the device pins and in the Status Register. The Control Register is not affected by a Master Reset. HOLT INTEGRATED CIRCUITS 8 HI-3582, HI-3583 TIMING DIAGRAMS DATA RATE - EXAMPLE PATTERN TXAOUT ARINC BIT TXBOUT NULL DATA DATA DATA NULL BIT 1 NEXT WORD WORD GAP BIT 32 BIT 31 BIT 30 NULL RECEIVER OPERATION ARINC DATA BIT 31 BIT 32 D/R, HF, FF tEND/R tD/R DON'T CARE SEL tEN tSELEN tSELEN tENSEL EN tENEN tD/REN tSELEN tENSEL tREADEN tDATAEN tDATAEN BYTE 2 VALID BYTE 1 VALID DATA BUS tENDATA BYTE 1 tENDATA tENDATA TRANSMITTER OPERATION BYTE 2 VALID BYTE 1 VALID DATA BUS tDWSET tDWSET tDWHLD tDWHLD PL1 tPL12 tPL PL2 tPL12 tPL tTX/R TX/R, FFT tHFT HFT LOADING CONTROL WORD VALID DATA BUS tCWSET tCWHLD CWSTR tCWSTR HOLT INTEGRATED CIRCUITS 9 HI-3582, HI-3583 TIMING DIAGRAMS (cont.) STATUS REGISTER READ CYCLE BYTE SELECT DON'T CARE SEL DON'T CARE tSELEN tENSEL RSR tDATAEN DATA VALID DATA BUS tENDATA CONTROL REGISTER READ CYCLE BYTE SELECT SEL DON'T CARE DON'T CARE tSELEN tENSEL RSR tDATAEN DATA VALID DATA BUS tENDATA LABEL MEMORY LOAD SEQUENCE tCWSTR CWSTR tCWSET DATA BUS Set CR1=1 tCWHLD Label #1 Label #2 Label #16 Set CR1=0 tDWSET tDWHLD PL1 or PL2 tPL tLABEL LABEL MEMORY READ SEQUENCE tCWSTR CWSTR tREADEN EN1 or EN2 tCWHLD tDATAEN tCWSET DATA BUS Set CR1=1 Label #1 Label #2 tENDATA HOLT INTEGRATED CIRCUITS 10 Label #16 Set CR1=0 HI-3582, HI-3583 TIMING DIAGRAMS (cont.) TRANSMITTING DATA PL2 tDTX/R tPL2EN TXR tENTX/R ENTX ARINC BIT DATA BIT 1 tENDAT ARINC BIT DATA BIT 2 ARINC BIT DATA BIT 32 +5V +5V TXAOUT -5V +5V TXBOUT -5V -5V tfx +10V +10V 90% V DIFF (TXAOUT) - TXBOUT) tfx 10% trx one level trx 10% 90% zero level null level -10V REPEATER OPERATION TIMING RIN BIT 32 tEND/R D/R tD/R tD/REN tEN tENEN tEN EN tSELEN SEL tENSEL DON'T CARE DON'T CARE tENPL tSELEN tPLEN tENSEL PL1 tPLEN tENPL PL2 tTX/R TXR tTX/REN tENTX/R ENTX tDTX/R tENDAT TXAOUT TXBOUT BIT 1 BIT 32 tNULL HOLT INTEGRATED CIRCUITS 11 HI-3582, HI-3583 ABSOLUTE MAXIMUM RATINGS Supply Voltages VDD ......................................... -0.3V to +4.0V V+ ......................................................... +11.0V V- ......................................................... -11.0V Power Dissipation at 25°C Plastic Quad Flat Pack ..................1.5 W, derate 10mW/°C Ceramic J-LEAD CERQUAD ...... 1.0 W, derate 7mW/°C Voltage at pins RIN1A, RIN1B, RIN2A, RIN2B .. -120V to +120V DC Current Drain per pin .............................................. ±10mA Voltage at any other pin ............................... -0.3V to VDD +0.3V Storage Temperature Range ........................ -65°C to +150°C Solder temperature (Reflow) ............................................. 260°C Operating Temperature Range (Industrial): .... -40°C to +85°C (Extended): .....-55°C to +125°C NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. HEAT SINK - CHIP-SCALE PACKAGE ONLY The HI-3582PCI/T/M and HI-3583PCI/T/M use a 44-pin plastic chip-scale package. This package has a metal heat sink pad on its bottom surface. This heat sink is electrically connected to the die. To enhance thermal dissipation, the heat sink can be soldered to matching circuit board pad. The heat sink may be connected to V+ or left floating. Do not connect heat sink pad to VDD, GND or V-. HOLT INTEGRATED CIRCUITS 12 HI-3582, HI-3583 DC ELECTRICAL CHARACTERISTICS VDD = 3.3V , V+ = 10V, V- = -10V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). LIMITS PARAMETER ARINC INPUTS - SYMBOL CONDITIONS VIH VIL VNUL Common mode voltages less than ±4V with respect to GND MIN TYP MAX 6.5 -13.0 -2.5 10.0 -10.0 0 13.0 -6.5 2.5 46 38 38 UNIT Pins RIN1A, RIN1B, RIN2A, RIN2B Differential Input Voltage: (RIN1A to RIN1B, RIN2A to RIN2B) ONE ZERO NULL Input Resistance: Differential To GND To VDD RI RG RH 12 12 12 Input Sink Input Source IIH IIL -450 Differential To GND To VDD CI CG CH Input Voltage HI Input Voltage LO VIH VIL Input Sink Input Source IIH IIL Input Voltage HI Input Voltage LO VIH VIL Input Sink Input Source Pull-down Current (TEST Pin) IIH IIL IPD Input Current: Input Capacitance: (Guaranteed but not tested) (RIN1A to RIN1B, RIN2A to RIN2B) V V V KW KW KW 200 µA µA 20 20 20 pF pF pF 30% VDD V V BI-DIRECTIONAL INPUTS - Pins BD00 - BD15 Input Voltage: Input Current: 70% VDD 1.5 -1.5 µA µA OTHER INPUTS Input Voltage: Input Current: 70% VDD 30% VDD 1.5 -1.5 50 V V 150 µA µA µA ARINC OUTPUTS - Pins TXAOUT, TXBOUT ARINC output voltage (Ref. To GND) One or zero Null VDOUT VNOUT No load and magnitude at pin, VDD = 3.3 V 4.50 -0.25 5.00 5.50 0.25 V V ARINC output voltage (Differential) One or zero Null VDDIF VNDIF No load and magnitude at pin, VDD = 3.3 V 9.0 -0.5 10.0 11.0 0.5 V V ARINC output current IOUT 80 mA OTHER OUTPUTS Output Voltage: Output Current: (All Outputs & Bi-directional Pins) Output Capacitance: Logic "1" Output Voltage Logic "0" Output Voltage VOH VOL IOH = -100µA IOL = 1.0mA VDD - 0.2V Output Sink Output Source IOL IOH VOUT = 0.4V VOUT = VDD - 0.4V 1.6 CO 10% VDD V V -1.0 mA mA 15 pF Operating Voltage Range VDD 3.15 3.45 V V+ 9.5 10.5 V V- -9.5 -10.5 V 2.5 7 mA 4 10 21 10 21 mA mA mA mA Operating Supply Current VDD IDD1 V+ IDD2 V- IEE1 Quiescent current Max. Load Quiescent current Max. Load HOLT INTEGRATED CIRCUITS 13 4 HI-3582, HI-3583 AC ELECTRICAL CHARACTERISTICS VDD = 3.3V, V+=10V, V-=-10V, GND = 0V, TA = Oper. Temp. Range and fclk=1MHz +0.1% with 60/40 duty cycle PARAMETER SYMBOL LIMITS MIN TYP MAX UNITS CONTROL WORD TIMING Pulse Width - CWSTR Setup - DATA BUS Valid to CWSTR HIGH Hold - CWSTR HIGH to DATA BUS Hi-Z tCWSTR tCWSET tCWHLD 50 100 40 ns ns ns RECEIVER FIFO AND LABEL READ TIMING Delay - Start ARINC 32nd Bit to D/R LOW: High Speed Low Speed tD/R tD/R Delay - D/R LOW to EN LOW Delay - EN HIGH to D/R HIGH tD/REN tEND/R 0 Setup - SEL to EN LOW Hold - SEL to EN HIGH tSELEN tENSEL 10 10 Delay - EN LOW to DATA BUS Valid Delay - EN HIGH to DATA BUS Hi-Z tENDATA tDATAEN Pulse Width - EN1 or EN2 Spacing - EN HIGH to next EN LOW (Same ARINC Word) Spacing -EN HIGH to next EN LOW (Next ARINC Word) tEN tENEN 420 16 128 µs µs 520 ns ns ns ns 235 80 ns ns tREADEN 60 65 200 ns ns ns tPL 120 ns Setup - DATA BUS Valid to PL HIGH Hold - PL HIGH to DATA BUS Hi-Z tDWSET tDWHLD 190 70 ns ns Spacing - PL1 or PL2 Spacing between Label Write pulses tPL12 tLABEL 110 150 ns ns Delay - PL2 HIGH to TX/R LOW tTX/R 240 ns Delay - PL2 HIGH to HFT low tHFT 560 ns TRANSMITTER FIFO AND LABEL WRITE TIMING Pulse Width - PL1 or PL2 TRANSMISSION TIMING Spacing - PL2 HIGH to ENTX HIGH tPL2EN Delay - 32nd ARINC Bit to TX/R HIGH tDTX/R Spacing - TX/R HIGH to ENTX LOW tENTX/R 0 ns 50 0 ns ns LINE DRIVER OUTPUT TIMING Delay - ENTX HIGH to TXAOUT or TXBOUT: High Speed Delay - ENTX HIGH to TXAOUT or TXBOUT: Low Speed Line driver transition differential times: (High Speed, control register CR13 = Logic 0) tENDAT tENDAT 25 200 µs µs high to low low to high tfx trx 1.0 1.0 1.5 1.5 2.0 2.0 µs µs high to low low to high tfx trx 5.0 5.0 10 10 15 15 µs µs Delay - EN LOW to PL LOW tENPL 0 ns Hold - PL HIGH to EN HIGH tPLEN 0 ns tTX/REN 0 ns tMR 175 ns (Low Speed, control register CR13 = Logic 1) REPEATER OPERATION TIMING Delay - TX/R LOW to ENTX HIGH MASTER RESET PULSE WIDTH ARINC DATA RATE AND BIT TIMING ± 1% HOLT INTEGRATED CIRCUITS 14 HI-3582, HI-3583 7 - D/R1 6 - RIN2B 5 - RIN2A 4 - RIN1B 3 - RIN1A 2 - VDD 1 - N/C 52 - TEST 51 - MR 50 - TXCLK 49 - CLK 48 - RSR 47 - N/C ADDITIONAL HI-3582 / HI-3583 PIN CONFIGURATIONS FF1 - 8 HF1 - 9 D/R2 - 10 FF2 - 11 HF2 - 12 SEL - 13 EN1 - 14 EN2 -15 BD15 - 16 BD14 - 17 BD13 - 18 BD12 - 19 BD11 - 20 46 - N/C 45 - CWSTR 44 - ENTX 43 - V+ 42 - TXBOUT 41 - TXAOUT 40 - V39 - FFT 38 - HFT 37 - TX/R 36 - PL2 35 - PL1 34 - BD00 BD10 - 21 BD09 - 22 BD08 - 23 BD07 - 24 BD06 - 25 N/C - 26 GND - 27 N/C - 28 BD05 - 29 BD04 - 30 BD03 - 31 BD02 - 32 BD01 - 33 HI-3582CJI HI-3582CJT HI-3582CJM & HI-3583CJI HI-3583CJT HI-3583CJM 52 - Pin Cerquad J-Lead (See page 1 for additional pin configuration) ORDERING INFORMATION HI - 35xx xx x x - xx PART NUMBER INPUT SERIES RESISTANCE BUILT-IN REQUIRED EXTERNALLY No dash number 35K Ohm 0 -10 25K Ohm 10K Ohm PART NUMBER Blank PACKAGE DESCRIPTION Tin / Lead (Sn / Pb) Solder F 100% Matte Tin (Pb-free RoHS compliant) PART NUMBER TEMPERATURE RANGE FLOW BURN IN I -40°C TO +85°C I No T -55°C TO +125°C T No M -55°C TO +125°C M Yes PART NUMBER PACKAGE DESCRIPTION CJ 52 PIN J-LEAD CERQUAD (52U) not available Pb-free PC 64 PIN PLASTIC CHIP-SCALE LPCC (64PCS) PQ 52 PIN PLASTIC QUAD FLAT PACK PQFP (52PQS) PART NUMBER OUTPUT SERIES RESISTANCE BUILT-IN REQUIRED EXTERNALLY 3582 37.5 Ohms 0 3583 10 Ohms 27.5 Ohms HOLT INTEGRATED CIRCUITS 15 HI-3582, HI-3583 REVISION HISTORY Revision Date Description of Change DS3582, Rev. H 07/21/08 DS3582, Rev. I 12/19/12 DS3582, Rev J DS3582, Rev K 04/18/13 08/12/13 Added “M” process part numbers to Pin Descriptions and Ordering Information and clarified temperature ranges in Features Clarified description of receiver parity. Updated PQFP and QFN package drawings. Corrected description of receiver parity. Removed reference to note 1 on ordering information page and updated operating temperatures from “military” to “extended”. Update Voltage at ARINC input pins from +/-29V to +/-120V. Add conditions that IDD2 and IEE2 are max. quiescent values. Add two lines to show same for full ARINC load conditions is 21mA. HOLT INTEGRATED CIRCUITS 16 HI-3582 / HI-3583 PACKAGE DIMENSIONS inches (millimeters) 52-PIN J-LEAD CERQUAD Package Type: 52U 7 1 52 47 8 .788 max (20.0) SQ. .720 ±.010 (18.29 ±.25) .750 ±.007 (19.05 ±.18) .190 max (4.826) .040 ± .005 (1.02 ± .013) .019 ±.002 (.483 ±.051) .050 BSC (1.27) 52-PIN PLASTIC QUAD FLAT PACK (PQFP) inches (millimeters) Package Type: 52PQS .0256 BSC (.65) .520 BSC SQ (13.2) .394 BSC SQ (10.0) .012 ± .004 (.310 ± .09) .035 ± .006 (.88 ± .15) .063 typ (1.6) .008 min (.20) See Detail A .106 MAX. (2.7) .005 (.13) R min .079 ± .008 (2.0 ± .20) .005 R min (.13) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) DETAIL A HOLT INTEGRATED CIRCUITS 17 0° £ Q £ 7° HI-3582 / HI-3583 PACKAGE DIMENSIONS inches (millimeters) 64-PIN PLASTIC CHIP-SCALE PACKAGE (QFN) Package Type: 64PCS Electrically isolated heat sink pad on bottom of package .354 BSC (9.00) Connect to any ground or power plane for optimum thermal dissipation .268 ± .039 (6.80 ± .05) .0197 BSC (0.50) .354 BSC (9.00) .268 ± .039 (6.80 ± .05) Top View Bottom View .010 typ (0.25) .016 ± .002 (0.40 ± .05) .008 typ (0.20) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) .039 max (1.00) HOLT INTEGRATED CIRCUITS 18