HOLTIC HI

HI-3593
3.3V ARINC 429 Dual Receiver,
Single Transmitter with SPI Interface
August 2011
GENERAL DESCRIPTION
FEATURES
·
·
·
·
·
44
43
42
41
40
39
38
37
36
35
34
-
AMPA
TXAOUT
AMPB
TXBOUT
TFULL
TEMPTY
R1FLAG
R1INT
R2FLAG
R2INT
-
- VDD
- VDD
- CP- CP+
- V+
- GND
- GND
- CN+
- CN- V44
43
42
41
40
39
38
37
36
35
34
-1
RIN1A-40 - 2
RIN1A - 3
RIN1B - 4
RIN1B-40 - 5
RIN2A-40 - 6
RIN2A - 7
RIN2B - 8
RIN2B-40 - 9
MR - 10
ACLK - 11
HI-3593PQI
HI-3593PQT
HI-3593PQM
33 - AMPA
32 - TXAOUT
31 - AMPB
30 - TXBOUT
29 28 - TFULL
27 - TEMPTY
26 - R1FLAG
25 - R1INT
24 - R2FLAG
23 - R2INT
ARINC 429 specification compliant
Single 3.3V power supply
On-chip analog line driver and receiver connect
directly to ARINC 429 bus
Programmable label recognition for 256 labels
32 x 32 Receive FIFOs and Priority-Label buffers
CS - 12
SI - 13
SCK - 14
SO - 15
GND - 16
MB1-1 - 17
MB1-2 - 18
MB1-3 - 19
MB2-1 - 20
MB2-2 - 21
MB2-3 - 22
·
·
·
HI-3593PCI
HI-3593PCT
HI-3593PCM
33
32
31
30
29
28
27
26
25
24
23
44 - Pin Plastic 7mm x 7mm
Chip-Scale Package (QFN)
The Serial Peripheral Interface minimizes the number of
host interface signals resulting in a small footprint device
that can be interfaced to a wide range of industry-standard
microcontrollers supporting SPI. Alternatively, the SPI
signals may be controlled using just four general purpose
I/O port pins from a microcontroller or custom FPGA. The
SPI and all control signals are CMOS and TTL compatible
and support 3.3V operation.
The HI-3593 applies the ARINC 429 protocol to the
receivers and transmitter. ARINC 429 databus timing
comes from a 1 MHz clock input, or an internal counter can
derive it from higher clock frequencies having certain fixed
values, possibly the external host processor clock.
- 1
- 2
- 3
- 4
- 5
- 6
- 7
- 8
- 9
- 10
- 11
12
13
14
15
16
17
18
19
20
21
22
RIN1A-40
RIN1A
RIN1B
RIN1B-40
RIN2A-40
RIN2A
RIN2B
RIN2B-40
MR
ACLK
CS
SI
SCK
SO
GND
MB1-1
MB1-2
MB1-3
MB2-1
MB2-2
MB2-3
The HI-3593 from Holt Integrated Circuits is a CMOS
integrated circuit for interfacing a Serial Peripheral
Interface (SPI) enabled microcontroller to the ARINC 429
serial bus. The device provides two receivers, each with
user-programmable label recognition for any combination
of 256 possible labels, 32 x 32 Receive FIFO, 3 prioritylabel quick-access double-buffered registers and analog
line receiver. The independent transmitter has a 32 x 32
Transmit FIFO and built-in line driver. The line driver
operates from a single 3.3V supply and includes on-chip
DC/DC converter to generate the bipolar ARINC 429
differential voltage levels needed to directly drive the
ARINC 429 bus. The status of the transmit and receive
FIFOs and priority-label buffers can be monitored using
the programmable external interrupt pins, or by polling the
HI-3593 Status Registers. Other features include a
programmable option of data or parity in the 32nd bit, and
the ability to switch the bit-signifiance of ARINC 429 labels.
Pins are available with different input resistance and
output resistance values which provides flexibility when
using external lightning protection circuitry.
VDD
VDD
CPCP+
V+
GND
GND
CN+
CNV-
PIN CONFIGURATIONS (Top View)
44 - Pin Plastic Quad Flat Pack (PQFP)
Independent data rates for Transmit and Receive
10MHz, four-wire Serial Peripheral Interface (SPI)
Industrial & extended temperature ranges
(DS3593 Rev. A)
HOLT INTEGRATED CIRCUITS
www.holtic.com
08/11
HI-3593
BLOCK DIAGRAM
VDD (3.3V)
Transmitter
ARINC 429
Line Driver
V+
5W
AMPA
ARINC 429
Transmit
Data FIFO
37.5W
ARINC 429
Transmit
Formatter
TXAOUT
TXBOUT
37.5W
AMPB
5W
VTFULL
Transmit Status
MR
TEMPTY
Transmit Control
V+
SCK
CS
SI
V+
47uF
SPI
Interface
V-
V-
SO
47uF
DC / DC
Converter
3.3V
ARINC
Clock
Divider
ACLK
CP+
CP-
0.47uF
CN+
CN-
Receiver 2
Receiver 1
R2FLAG
Receive Status
Receive Control
RIN2A
RIN2B
R2INT
Label
Filter
Bit Map
Memory
R1FLAG
Flag /
Interrupt
R1INT
RIN2B-40
ARINC 429
Line Receiver
RIN2A-40
RIN1A
RIN1B
RIN1B-40
40 KW
40 KW
ARINC 429
Valid word
Checker
(See fig. 3)
Label
Filter
ARINC 429
Received
Data FIFO
(32 x 32)
RIN1A-40
Priority Label
Match (x3)
Buffer
P-L Reg 3
Buffer
P-L Reg 2
Buffer
P-L Reg 1
MB2-3
MB2-2
MB2-1
MB1-3
MB1-2
MB1-1
GND
HOLT INTEGRATED CIRCUITS
2
2.2uF
HI-3593
PIN DESCRIPTIONS
SIGNAL
FUNCTION
RIN1A-40
RIN1A
RIN1B
RIN1B-40
RIN2A-40
RIN2A
RIN2B
RIN2B-40
MR
ACLK
CS
SI
SCLK
SO
GND
MB1-1
MB1-2
MB1-3
MB2-1
MB2-2
MB2-3
R2INT
R2FLAG
R1INT
R1FLAG
TEMPTY
TFULL
TXBOUT
AMPB
TXAOUT
AMPA
VCNCN+
V+
CPCP+
VDD
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
OUTPUT
POWER
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
CONVERTER
CONVERTER
CONVERTER
CONVERTER
CONVERTER
CONVERTER
POWER
DESCRIPTION
INTERNAL PULL UP / DOWN
Alternate ARINC receiver 1 positive input. Requires external 40K ohm resistor
ARINC receiver 1 positive input. Direct connection to ARINC 429 bus
ARINC receiver 1 negative input. Direct connection to ARINC 429 bus
Alternate ARINC receiver 1 negative input. Requires external 40K ohm resistor
Alternate ARINC receiver 2 positive input. Requires external 40K ohm resistor
ARINC receiver 2 positive input. Direct connection to ARINC 429 bus
ARINC receiver 2 negative input. Direct connection to ARINC 429 bus
Alternate ARINC receiver 2 negative input. Requires external 40K ohm resistor
Master Reset. A positive pulse clears Receive and Transmit data FIFOs and flags
Master timing source for the ARINC 429 receiver and transmitter
Chip Select. Data is shifted into SI and out of SO when CS is low.
SPI interface serial data input
SPI Clock. Data is shifted into or out of the SPI interface using SCK
SPI interface serial data output
Chip 0V supply
Goes high when Receiver 1, Priority-Label Mail Box 1 contains a message
Goes high when Receiver 1, Priority-Label Mail Box 2 contains a message
Goes high when Receiver 1, Priority-Label Mail Box 3 contains a message
Goes high when Receiver 2, Priority-Label Mail Box 1 contains a message
Goes high when Receiver 2, Priority-Label Mail Box 2 contains a message
Goes high when Receiver 2, Priority-Label Mail Box 3 contains a message
Receiver 2 programmable Interrupt pin
Goes high as defined by Flag / Interrupt Assignment Register
Receiver 1 programmable Interrupt pin
Goes high as defined by Flag / Interrupt Assignment Register
Goes high when the Transmit FIFO is empty
Goes high when the Transmit FIFO contains the maximum 32 ARINC 429 words
ARINC line driver negative output. Direct connection to ARINC 429 bus
Alternate ARINC line driver negative output. Requires external 32.5 ohm resistor
ARINC line driver positive output. Direct connection to ARINC 429 bus
Alternate ARINC line driver positive output. Requires external 32.5 ohm resistor
DC/DC negative voltage output
DC/DC converter fly capacitor for VDC/DC converter fly capacitor for VDC/DC positive voltage output
DC/DC converter fly capacitor for V+
DC/DC converter fly capacitor for V+
Chip 3.3V supply
50K ohm pull-down
50K ohm pull-down
50K ohm pull-up
50K ohm pull-down
50K ohm pull-down
INSTRUCTIONS
Instruction op codes are used to read, write and configure the HI3593. When CS goes low, the next 8 clocks at the SCK pin shift an
instruction op code into the decoder, starting with the first rising
edge. The op code is fed into the SI pin, most significant bit first.
SPI Instructions are of a common format. The first bit specifies
whether the instruction is a write “0” or read “1” transfer. The next
five bits specify the source or destination of the associated data
byte(s), and the last two bits are “don’t care”.
For read instructions, the most significant bit of the requested data
word appears at the SO pin after the last op code bit is clocked into
the decoder, at the next falling SCK edge. As in write instructions,
the data field bit-length varies with read instruction type.
Source /
Destination
R
/W
For write instructions, the most significant bit of the data word must
immediately follow the instruction op code and is clocked into its
register on the next rising SCK edge. Data word length varies
depending on word type written: 8-bit Control Register writes, 32bit ARINC label writes or 256-bit writes to a channel’s labelmatching enable/disable memory.
MSB
HOLT INTEGRATED CIRCUITS
3
7
6
5
4
3
2
X
X
1
0
LSB
SPI INSTRUCTION FORMAT
HI-3593
TABLE 1. DEFINED INSTRUCTIONS
Op-Code R/W
# Data
bytes
DESCRIPTION
0x00
W
0
Instruction not implemented. No operation.
0x04
W
0
Software controlled Master Reset
0x08
W
1
Write Transmit Control Register
0x0C
W
4
Write ARINC 429 message to Transmit FIFO
0x10
W
1
Write Receiver 1 Control Register
0x14
W
32
Write label values to Receiver 1 label memory. Starting with label 0xFF, consecutively set or reset each
label in descending order. For example, if the first data byte is programmed to 10110010 then labels FF,
FD FC and F8 will be set and FE, FB, FA and F7 will be reset.
0x18
W
3
Write Receiver 1 Priority-Label Match Registers. The data field consists of three eight-bit labels. The first data
byte is written to P-L filter #3, the second to P-L filter #2, and the last byte to filter #1
0x24
W
1
Write Receiver 2 Control Register
0x28
W
32
Write label values to Receiver 2 label memory. Starting with label 0xFF, consecutively set or reset each
label in descending order. For example, if the first data byte is programmed to 10110010 then labels FF,
FD FC and F8 will be set and FE, FB, FA and F7 will be reset.
0x2C
W
3
Write Receiver 2 Priority-Label Match Registers. The data field consists of three eight-bit labels. The first
eight bits is written to P-L filter #3, the second to P-L filter #2, and the last byte to filter #1
0x34
W
1
Write Flag / Interrupt Assignment Register
0x38
W
1
Write ACLK Division Register
0x40
W
0
Transmit current contents of Transmit FIFO if Transmit Control Register bit 5 (TMODE) is a “0”
0x44
W
0
Software Reset. Clears the Transmit and Receive FIFOs and the Priority-Label Registers
0x48
W
0
Set all bits in Receiver 1 label memory to a “1”
0x4C
W
0
Set all bits in Receiver 2 label memory to a “1”
0x80
R
1
Read Transmit Status Register
0x84
R
1
Read Transmit Control Register
0x90
R
1
Read Receiver 1 Status Register
0x94
R
1
Read Receiver 1 Control Register
0x98
R
32
Read label values from Receiver 1 label memory.
0x9C
R
3
Read Receiver 1 Priority-Label Match Registers.
0xA0
R
4
Read one ARINC 429 message from the Receiver 1 FIFO
0xA4
R
3
Read Receiver 1 Priority-Label Register #1, ARINC429 bytes 2,3 & 4 (bits 9 - 32)
0xA8
R
3
Read Receiver 1 Priority-Label Register #2, ARINC429 bytes 2,3 & 4 (bits 9 - 32)
0xAC
R
3
Read Receiver 1 Priority-Label Register #3, ARINC429 bytes 2,3 & 4 (bits 9 - 32)
0xB0
R
1
Read Receiver 2 Status Register
0xB4
R
1
Read Receiver 2 Control Register
0xB8
R
32
Read label values from Receiver 2 label memory.
0xBC
R
3
Read Receiver 2 Priority-Label Match Registers.
0xC0
R
4
Read one ARINC 429 message from the Receiver 2 FIFO
0xC4
R
3
Read Receiver 2 Priority-Label Register #1, ARINC429 bytes 2,3 & 4 (bits 9 - 32)
0xC8
R
3
Read Receiver 2 Priority-Label Register #2, ARINC429 bytes 2,3 & 4 (bits 9 - 32)
0xCC
R
3
Read Receiver 2 Priority-Label Register #3, ARINC429 bytes 2,3 & 4 (bits 9 - 32)
0xD0
R
1
Read Flag / Interrupt Assignment Register
0xD4
R
1
Read ACLK Division Register
0xFF
R
0
Instruction not implemented. No operation.
HOLT INTEGRATED CIRCUITS
4
HI-3593
REGISTER DESCRIPTIONS
R
FL
SD IP
9
SD
1
SD 0
O
PA N
R
LA ITY
BR
PL E
O C
R N
AT
E
RECEIVE CONTROL REGISTER
(Receiver 1 Write, SPI Op-code 0x10)
(Receiver 1 Read, SPI Op-code 0x94)
(Receiver 2 Write, SPI Op-code 0x24)
(Receiver 2 Read, SPI Op-code 0xB4)
7 6
MSB
5
4
3
2
1
0
LSB
R/W
Default Description
7
RFLIP
R/W
0
Setting this bit reverses the bit order of the first 8 bits of each ARINC 429 message received.
See figure 1 for details.
6
SD9
R/W
0
If the receiver decoder is enable by setting the SDON bit to a “1”, then ARINC 429 message
bit 9 must match this bit for the message to be accepted.
5
SD10
R/W
0
If the receiver decoder is enable by setting the SDON bit to a “1”, then ARINC 429 message
bit 10 must match this bit for the message to be accepted.
4
SDON
R/W
0
If this bit is set, bits 9 and 10 of the received ARINC 429 message must match SD9 and SD10
3
PARITY
R/W
0
Received word parity checking is enabled when this bit is set. If “0”, all 32 bits of the received
ARINC 429 word are stored without parity checking.
2
LABREC
R/W
0
When “0”, all received messages are stored. If this bit is set, incoming ARINC message label
filtering is enabled. Only messages whose corresponding label filter table entry is set to a “1”
will be stored in the Receive FIFO.
1
PLON
R/W
0
Priority-Label Register enable. If PLON = “1” the three Priority-Label Registers are enabled
and received ARINC 429 messages with labels that match one of the three pre-programmed
values will be capured and stored in the corresponding Prioty-Label Mail Boxes. If PLON = “0”
the Priority-Label matching feature is turned off and no words are placed in the mail boxes.
0
RATE
R/W
0
If RATE is “0”, ARINC 429 high-speed data rate is selected. RATE = “1” selects low-speed
ARINC 429 data rate (high-speed / 8).
IZ
TF
LI
TM P
O
SE DE
LF
O TE
D
D S
TP EV T
AR EN
X IT
Y
R
AT
E
Bit Name
H
TRANSMIT CONTROL REGISTER
(Write, SPI Op-code 0x08)
(Read, SPI Op-code 0x84)
7 6
MSB
5
4
3
2
1
0
LSB
Bit Name
R/W
7
HIZ
R/W
Default Description
0
Setting this bit puts the on-chip line driver outputs to a high-impedance state.
6
TFLIP
R/W
0
Setting this bit reverses the bit order of the first 8 bits of each ARINC 429 message transmitted.
See figure 1 for details.
5
TMODE
R/W
0
If TMODE is “0”, data in the transmit FIFO is sent to the ARINC 429 bus only upon receipt of an
SPI op-code 0x40, transmit enable, command. If TMODE is a “1”, data is sent as soon as it is
available.
4
SELFTEST
R/W
0
Setting SELFTEST causes an internal connection to be made looping-back the transmitter
outputs to both receiver inputs for self-test purposes. When in self-test mode, the HI-3593
ignores data received on the two ARINC 429 receive channels and holds the on-chip line driver
outputs in the NULL state to prevent self-test data being transmitted to other receivers on the
bus.
3
ODDEVEN
R/W
0
If the TPARITY bit is set, the transmitter inserts an odd parity bit if ODDEVEN = “0”, or an even if
ODDEVEN = “1”.
2
TPARITY
R/W
0
If TPARITY = “0”, no parity bit is inserted and the 32nd transmitted bit is data. When TPARITY is
a “1” a parity bit is substituted for bit 32 according to the ODDEVEN bit value.
1
X
R/W
0
Not used.
0
RATE
R/W
0
If RATE is “0”, ARINC 429 high-speed data rate is selected. RATE = “1” selects low-speed
ARINC 429 data rate (high-speed / 8).
HOLT INTEGRATED CIRCUITS
5
X
(Receiver 1 Read, SPI Op-code 0x90)
(Receiver 2 Read, SPI Op-code 0xB0)
X
RECEIVE STATUS REGISTER
0
0
7 6
MSB
Bit Name
R/W
PL
3
PL
2
PL
1
FF
FU
FF LL
H
FF ALF
EM
PT
Y
HI-3593
5
4
3
2
1
0
LSB
Default Description
X
R
0
Not used. Always reads “0”
6
X
R
0
Not used. Always reads “0”
5
PL3
R
0
This bit is set when a message is received by Priority Label filter #3
4
PL2
R
0
This bit is set when a message is received by Priority Label filter #2
3
PL1
R
0
This bit is set when a message is received by Priority Label filter #1
2
FFFULL
R
0
This bit is set when the Receive FIFO contains 32 ARINC 429 messages
1
FFHALF
R
0
This bit is set when the Receive FIFO contains at least 16 ARINC 429 messages
0
FFEMPTY
R
1
This bit is set when the Receive FIFO is empty
Bit Name
R/W
X
X
X
X
(Read, SPI Op-code 0x80)
X
TRANSMIT STATUS REGISTER
0
0
0
0
0
7 6
MSB
5
4
3
TF
FU
TF LL
H
TF ALF
EM
PT
Y
7
2
1
0
LSB
Default Description
7
X
R
0
Not used. Always reads “0”
6
X
R
0
Not used. Always reads “0”
5
X
R
0
Not used. Always reads “0”
4
X
R
0
Not used. Always reads “0”
3
X
R
0
Not used. Always reads “0”
2
TFFULL
R
0
This bit is set when the Transmit FIFO contains 32 ARINC 429 messages
1
TFHALF
R
0
This bit is set when the Transmit FIFO contains at least 16 ARINC 429 messages
0
TFEMPTY
R
1
This bit is set when the Transmit FIFO is empty
0
0
7 6
MSB
5
IV
[
D 3]
IV
[
D 2]
IV
[
D 1]
IV
[
X 0]
X
0
D
X
(Write, SPI Op-code 0x38)
(Read, SPI Op-code 0xD4)
X
ACLK DIVISION REGISTER
0
4
3
2
1
0
LSB
Bit Name
R/W
7
X
R/W
0
Not used.
6
X
R/W
0
Not used.
5
X
R/W
0
Not used.
4 - 1 DIV[3:0]
R/W
0
The value programmed in DIV[3:0] sets the ACLK division ratio (see table 2)
0
R/W
0
Not used.
X
Default Description
HOLT INTEGRATED CIRCUITS
6
(Write, SPI Op-code 0x34)
(Read, SPI Op-code 0xD0)
R
R
FLAG / INTERRUPT ASSIGNMENT REGISTER
2I
N
T
2I [1]
N
R T[0
2F ]
R LAG
2F [
1
R LAG ]
1I
N [0]
R T[1
1I
N ]
R T[0
1F ]
R LAG
1F [
LA 1]
G
[0
]
HI-3593
7 6
MSB
Bit Name
R/W
7-6 R2INT[1:0]
R/W
0
10
11
0
10
11
R/W
0
01
10
11
R/W
1
0
LSB
0
R2INT pulses high when a valid message is received and
placed in the Receiver 2 FIFO or any of the Receiver 2 PriorityLabel mail boxes
R2INT pulses high when a message is received in Receiver 2
Priority-Label mail box #1
R2INT pulses high when a message is received in Receiver 2
Priority-Label mail box #2
R2INT pulses high when a message is received in Receiver 2
Priority-Label mail box #3
R2FLAG goes high when Receiver 2 FIFO is empty
R2FLAG goes high when Receiver 2 FIFO contains 32 ARINC
429 words (FIFO is full)
R2FLAG goes high when Receiver 2 FIFO contains at least
sixteen ARINC 429 words (FIFO is half-full)
R2FLAG goes high when Receiver 2 FIFO contains one or more
words (FIFO is not empty)
The value of R1INT[1:0] defines the function of the R1INT output pin, as follows:
00
1-0 R1FLAG[1:0]
2
The value of R2FLAG[1:0] defines the function of the R2FLAG output pin, as follows:
00
01
3-2 R1INT[1:0]
3
The value of R2INT[1:0] defines the function of the R2INT output pin, as follows:
01
R/W
4
Default Description
00
5-4 R2FLAG[1:0]
5
R1INT pulses high when a valid message is received and
placed in the Receiver 1 FIFO or any of the Receiver 1 PriorityLabel mail boxes
R1INT pulses high when a message is received in Receiver 1
Priority-Label mail box #1
R1INT pulses high when a message is received in Receiver 1
Priority-Label mail box #2
R1INT pulses high when a message is received in Receiver 1
Priority-Label mail box #3
The value of R1FLAG[1:0] defines the function of the R1FLAG output pin, as follows:
00
01
10
11
R1FLAG goes high when Receiver 1 FIFO is empty
R1FLAG goes high when Receiver 1 FIFO contains 32 ARINC
429 words (FIFO is full)
R1FLAG goes high when Receiver 1 FIFO contains at least
sixteen ARINC 429 words (FIFO is half-full)
R1FLAG goes high when Receiver 1 FIFO contains one or more
words (FIFO is not empty)
HOLT INTEGRATED CIRCUITS
7
HI-3593
ARINC 429 BIT ORDERING
ARINC 429 messages consist of a 32-bit sequence as shown
below. The first eight bits that appear on the ARINC 429 bus are
the label byte. The next twenty three bits comprise a data field
which presents data in a variety of formats defined in the ARINC
429 specification. The last bit transmitted is an odd parity bit.
ARINC 429 data is transmitted between the HI-3593 and host
microcontroller using the four-wire Serial Peripheral Interface
(SPI). A read or write operation consists of a single-byte op-code
followed by the data. When writing to the transmit FIFO or reading
from the receive FIFOs, the SPI data field is four bytes. Figure 1
shows how the SPI data bytes are mapped to the ARINC 429
message.
ARINC 429 specifies the MSB of the label as ARINC bit 1.
Conversely, the data field MSB is bit 31. So the bit significance of
the label byte and data fields are opposite.
The HI-3593 may be programmed to “flip” the bit ordering of the
label byte as soon as it is received and immediately prior to
transmission. This is accomplished by setting the TFLIP bit to a “1”
in the Transmit Control Register and/or the RFLIP bit in the
Receive Control Registers. The RFLIP bit does not control Priority
Label Match Registers.
Note that when reading ARINC 429 messages from the PriorityLabel Registers the label byte is omitted to permit a faster read
time. The label value will match the value loaded into the Match
Register and therefore does not need to be output each time a
message is read.
LSB
1 2 3 4 5 6 7 8
DATA
LSB
IT
LABEL
MSB
PA
R
MSB
SD
SDI
I
Y
ARINC 429 Message as received / transmitted on the ARINC 429 serial bus
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
time
0 0 0 0 1 1 0 0
DATA
MSB
LSB
SD
SDI
I
PA
R
SPI Op-Code
IT
Y
ARINC 429 Message as transferred on the SPI bus
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
LSB
LABEL
MSB
8 7 6 5 4 3 2 1
1 0 1 0 0 0 0 0
DATA
MSB
LSB
SD
SDI
I
SPI Op-Code
PA
R
IT
Y
Example 1. Write Transmit FIFO (Op-Code 0x0C) with TFLIP bit = “0”.
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
MSB
LABEL
1 2 3 4 5 6 7 8
1 1 0 0 1 1 0 0
DATA
MSB
LSB
SD
SDI
I
PA
R
IT
Y
Example 2. Read Receiver 1 FIFO (Op-Code 0xA0) with RFLIP bit = “1”.
SPI Op-Code
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Example 3. Read Receiver 2 Priority-Label Register #3 (Op-Code 0xCC).
SPI Op-Code
0 0 1 0 1 1 0 0
MSB
LABEL #3
LSB
1 2 3 4 5 6 7 8
MSB
LABEL #2
LSB
1 2 3 4 5 6 7 8
MSB
LABEL #1
LSB
1 2 3 4 5 6 7 8
Example 4. Write Receiver 2 Priority-Label Match Registers (Op-Code 0x2C)with RFLIP bit = “1” or “0”.
FIGURE 1.
ARINC 429 & SPI BIT ORDERING
HOLT INTEGRATED CIRCUITS
8
LSB
HI-3593
FUNCTIONAL DESCRIPTION
INITIALIZATION
ARINC 429 RECEIVERS
The HI-3593 may be initialized using the Master Reset (MR) pin or
under software control by executing SPI op-code 0x04. MR must
be pulsed high for 1 µs to bring the part to its completely reset
state. MR clears all three FIFOs, all six Priority-Label Mail Boxes,
clears the Filter memories and Match registers and sets all other
internal registers to their default state.
The HI-3593 has two completely independent ARINC 429 receive
channels. Each channel has an on-chip analog line receiver for
connection to the ARINC 429 incoming data bus. The ARINC 429
specification requires the following detection levels:
Software Reset is performed using SPI op-code 0x44. Software
Reset clears all three FIFOs and all six Priority-Label Mail Boxes,
but does not affect the values stored in the filter memories,
Priority-Label Match registers or other writeable registers. The
Transmit and Receive Status Registers will reflect the state of the
post-software reset device.
CLOCK FREQUENCY SELECTION
For correct ARINC 429 data rate transmission and reception, and
bit timing, the HI-3593 transmit and receive logic requires a 1 MHz
+/- 1% reference clock source. The clock is input at the ACLK pin
and must be 1 MHz or any even multiple of 1 MHz up to 30 MHz. If
a clock source greater than 1 MHz is used, then the ACLK Division
Register must be programmed with the appropriate scaling value.
Note that the least significant bit of the ACLK Division Register is
fixed at “0” allowing only even numbers to be programmed.
Similarly the three most significant bits are also fixed at “0” limiting
the maximum value to 0x1E. The ACLK Division Register is
cleared to 0x00 after Master Reset and is unaffected by Software
Reset. When programmed to 0x00, the ACLK division ratio is one,
and a 1 MHz clock should be applied to ACLK. The ACLK Division
Register is loaded using SPI Op-Code 0x38 and read using OpCode 0xD4.
The following table provides examples of ACLK frequency and
ACLK Division Register values for correct ARINC 429 operation:
ACLK Division Register value
External Clock
0x00
0x02
0x04
0x06
0x08
0x0A
“
“
0x1C
0x1E
1 MHz
2 MHz
4 MHz
6 MHz
8 MHz
10 MHz
“
“
28 MHz
30 MHz
TABLE 2. ACLK DIVISION
CONFIGURATION
The Transmit Control Register and Receiver Control Registers are
used to configure the ARINC 429 transmission channel and two
ARINC 429 receive channels. The registers may be written or read
at any time. They are reset to 0x00 following Master Reset and are
unchanged by Software Reset. Refer to the Receiver Control
Register and Transmit Control Register descriptions for detailed
information.
STATE
ONE
NULL
ZERO
DIFFERENTIAL VOLTAGE
+6.5 Volts to +13 Volts
+2.5 Volts to -2.5 Volts
-6.5 Volts to -13 Volts
The HI-3593 guarantees recognition of these levels with a common
mode voltage with respect to GND less than ±30V for the worst case
condition (3.15V supply and 13V signal level).
Design tolerances guarantee detection of the above levels, so the
actual acceptance ranges are slightly larger. If the ARINC signal
(including nulls) is outside the differential voltage ranges, the HI3593 receiver rejects the data.
BIT TIMING
The ARINC 429 specification defines the following timing tolerances for received data:
BIT RATE
PULSE RISE TIME
PULSE FALL TIME
PULSE WIDTH
HIGH SPEED
(RATE = “0”)
100K BPS ± 1%
1.5 ± 0.5 µsec
1.5 ± 0.5 µsec
5 µsec ± 5%
LOW SPEED
(RATE = “1”)
12K -14.5K BPS
10 ± 5 µsec
10 ± 5 µsec
34.5 to 41.7 µsec
The HI-3593 accepts signals within these tolerances and rejects
signals outside these tolerances. Receiver logic achieves this as
described below:
1. An accurate 1MHz clock source is required to validate the
receive signal timing.
2. The receiver uses three separate 10-bit sampling shift registers for Ones detection, Zeros detection and Null detection.
When the input signal is within the differential voltage range
for any shift register’s state (One, Zero or Null) sampling
clocks a “1” into that register. When the receive signal is outside the differential voltage range defined for any shift register, a “0” is clocked. Only one shift register can clock a “1” for
any given sample. All three registers clock zeros if the differential input voltage is between defined state voltage bands.
Valid data bits require at least three consecutive One or Zero
samples (three “1’s”) in the first five positions of the Ones or
Zeros sampling shift register, and at least three consecutive
Null samples (three “1’s”) in the second five positions of the
Null sampling shift register within the data bit interval.
A word gap Null requires at least three consecutive Null samples in the first half of the Null sampling shift register and at
least three consecutive Null samples in the second half of the
Null sampling shift register. This guarantees the minimum
pulse width.
HOLT INTEGRATED CIRCUITS
9
HI-3593
FUNCTIONAL DESCRIPTION (cont.)
3. To validate the receive data bit rate, each bit must follow its
preceding bit by not less than 8 samples and not more than 12
samples. With exactly 1MHz input clock frequency, the
acceptable data bit rates are:
DATA BIT RATE MIN
DATA BIT RATE MAX
HIGH SPEED
LOW SPEED
83K BPS
125K BPS
10.4K BPS
15.6K BPS
4. Following the last data bit of a valid reception, the Word
Gap timer samples the Null shift register every 10 input
clocks (every 80 clocks for low speed). If a Null is present,
the Word Gap counter is incremented. A Word Gap count of
3 enables the next reception.
RECEIVER PARITY
Receiver parity checking is enabled by setting the Receive Control
register PARITY bit to a “1”. When enabled, the receiver parity
circuit counts Ones received, including the parity bit. If the result is
odd, a "0" is stored in the 32nd bit position, overwriting the received
parity bit. The “0” indicates a parity bit check pass.
If receive parity is enabled and a word is received with bad odd
parity, the 32nd bit is overwritten with a “1” indicating a parity check
fail.
When the Receiver Control Register PARITY bit is a “0”, no parity
checking takes place and all 32 bits of the received word remain
unaltered.
All three Priority-Label Match Registers are loaded using SPI opcode 0x18 (Receiver 1) or 0x2C (Receiver 2), followed by three label
match values. The first byte is the match value for Priority-Label
Register #3, the second for Priority-Label Register #2 and the third
for Priority-Label #1. The match values may be checked by reading
the Priority-Label Match Registers using SPI op-code 0x9C
(Receiver 1) or 0xBC (Receiver 2).
When using the Priority-Label feature, all three Priority-Label Match
Registers must be loaded to avoid unintended matches occurring on
un-programmed Priority-Label Match Register random values. If
less than three Priority-Labels are required for a particular
application, duplicate copies of the same match value should be
stored in two (or three) registers.
Note that Priority-Label Registers (mail boxes) are only 24 bits long.
Because the ARINC 429 label byte value is pre-programmed for
each register it is not necessary to store it when words are received.
This allows a shorter and faster access of the data field using SPI
Op-Codes 0xA4, 0xA8 and 0xAC (Receiver 1 Priority-Label
Registers #1, #2 and #3) or 0xC4, 0xC8 and 0xCC (Receiver 2
Priority-Label Registers #1, #2 and #3).
The Receive Status Register bits PL1, PL2 and PL3 indicate when
Priority-Label data is available in the Priority-Label Registers. Six
status output pins MB1-1 through MB2-3 also indicate when data is
available at each of the six Priority-Label Registers. The R1INT and
R2INT interrupt pins can also be triggered when Priority Labels are
captured by programming bits 7, 6, 3 and 2 of the Flag / Interrupt
Assignment Register.
LABREC
ARINC word
matches
Enabled
label
SDON
ARINC word
bits 10, 9
match
SD10, SD9
0
X
0
X
Load FIFO
1
No
0
X
Ignore data
1
Yes
0
X
Load FIFO
0
X
1
No
Ignore data
0
X
1
Yes
Load FIFO
1
Yes
1
No
Ignore data
1
No
1
Yes
Ignore data
1
No
1
No
Ignore data
1
Yes
1
Yes
Load FIFO
RECEIVED DATA ACCEPTANCE AND STORAGE
The HI-3593 subjects incoming ARINC 429 messages to three
different data filter checks before data is accepted. First all words are
filtered for matching S/D bits, if enabled. Secondly, the word label
byte must match one of the three programmed Priority-Label Match
Register Values for the word to be stored in a Priority-Label Register,
and/or the label memory filter bit corresponding to the label must be
set to a “1” for the word to be stored in the Receiver FIFO.
S/D FILTERING
S/D filtering is enabled by setting the Receive Control Register
SDON bit to a “1”. When enabled, bits 9 and 10 of the incoming
ARINC 429 word are compared with Receive Control Register bits
SD9 and SD10. If they match, the word is accepted for the next
phase of filtering. If the bits do not match, the word is discarded and
never stored. The S/D filtering function may be disabled by
programming the SDON bit to a “0”. When disbled, all incoming
words are accepted for subsequent filtering.
PRIORITY LABELS
TABLE 3. FIFO LOADING CONTROL
RINA-40
VDD
DIFFERENTIAL
AMPLIFIERS
Priority-Label capture is enabled by setting the Receive Control
Register PLON bit to “1”. When PLON = “0” the Priority-Label feature
is disabled and no ARINC 429 words are stored in the Priority-Label
Registers.
COMPARATORS
ONE
RINA
The three Priority Label Registers store received data if the Priority
Label feature is enabled, and the incoming ARINC 429 word’s label
byte matches the value stored in Pririty-Label Match Register #1, # 2
or #3.
FIFO
GND
NULL
VDD
ZERO
RINB
RINB-40
GND
FIGURE 2. ARINC RECEIVER INPUT
HOLT INTEGRATED CIRCUITS
10
HI-3593
FUNCTIONAL DESCRIPTION (cont.)
RECEIVED ARINC 429 WORD
TO FILTERS (S/D, LABEL, PRIORITY-LABEL)
PARITY
CHECK
ONES
WORD GAP
TIMER
SHIFT REGISTER
32 BIT SHIFT REGISTER
WORD
GAP
END
1MHz
NULL
DATA
START
SHIFT REGISTER
SEQUENCE
CONTROL
BIT
CLOCK
1MHz
ZEROS
SHIFT REGISTER
ERROR
DETECTION
BIT
COUNTER
AND
END OF
SEQUENCE
EOS
NEW WORD
32ND
BIT
1MHz
ERROR
1MHz
FIGURE 3.
RECEIVER BLOCK DIAGRAM
RECEIVE DATA FIFO
RETRIEVING DATA
Following S/D Filtering, accepted ARINC 429 words are
conditionally stored in the Receive FIFO. If label filtering is
disabled, all words are stored. If label filtering is enabled, the
incoming ARINC429 word’s label byte value is checked against its
corresponding bit in the pre-programmed label look-up table. If the
bit is set to a “1” the word is stored in the FIFO. If the bit is a “0” the
word is not stored in the FIFO.
Each time a valid ARINC 429 word is loaded into the FIFO, the
Receive FIFO Status Register FFEMPTY, FFHALF and FFFULL bits
are updated. When the FIFO is EMPTY, the FFEMPTY bit is a “1” and
FFHALF and FFFULL are “0”. Once the first received and accepted
ARINC 429 word is loaded into the FIFO, FFEMPTY goes low. Each
received ARINC 429 word is retrieved via the SPI interface using SPI
Op-Code 0xA0 (Receiver 1) or 0xC0 (Receiver 2).
LABEL RECOGNITION
Up to 32 ARINC 429 words may be held in the Receive FIFO.
FFFULL goes high when the Receive FIFO is full. Failure to unload
the Receive FIFO when full causes additional valid ARINC 429
words to overwrite Receive FIFO location 32.
The user loads the 256-bit label look-up table to specify which 8-bit
incoming ARINC labels are stored in the Receive FIFO, and which
are not. Setting a “1” in the look-up table enables processing of
received ARINC words containing the corresponding label. A “0”
in the look-up table causes discard of received ARINC words
containing the label. The 256-bit look-up table is loaded using SPI
Op-Codes 0x14 (Receiver 1) and 0x28 (Receiver 2), as described
in Table 1. After the look-up table is initialized, the Control Register
bit LABREC must be set to enable label recognition.
All four bytes of the incoming ARINC429 word are stored in the
FIFO.
Table 3. defines the rules for Receive FIFO loading.
A FIFO half-full flag (FFHALF) is high whenever the Receive FIFO
contains 16 or more words. The FFHALF bit provides a useful
indicator to the host CPU that a sixteen word data retrieval routine
may be performed.
The FFEMPTY, FFHALF or FFFULL status bits can also be output on
the R1FLAG (Receiver 1) and R2FLAG (Receiver 2) pins. Flag /
Interrupt Assignment Register bits 5, 4, 1 and 0 select which flag
appears. Additionally, a FIFO not empty option may be programmed
for the R1FLAG / R2FLAG pins causing the pin to go high any time at
least one word is available in the FIFO.
READING THE LABEL LOOK-UP TABLE
The contents of the Label Look-up table may be read via the SPI
interface using Op-Code 0x98 (Receiver 1) or 0xB8 (Receiver 2) as
described in Table 1.
HOLT INTEGRATED CIRCUITS
11
HI-3593
FUNCTIONAL DESCRIPTION (cont.)
TRANSMITTER
SELF TEST
FIFO OPERATION
If Transmit Control Register bit SELFTEST is equal ”1”, the
transmitter serial output data is internally looped-back into the
receiver 1. The data will appear inverted (compliment) on receiver 2.
Data passes unmodified from transmitter to receiver 1. Setting
Transmit Control register bit SELFTEST to ”1” forces TXAOUT and
TXBOUT to the Null state to prevent self-test data from appearing on
the ARINC 429 bus.
Figure 4 shows a block diagram of the HI-3593 transmitter. The
Transmit FIFO is loaded with ARINC 429 words awaiting
transmission. SPI op-code 0x0C writes each ARINC 429 word into
the FIFO, at the next available FIFO location. If Transmit Status
Register bit TFEMPTY equals “1” (FIFO empty), then up to 32 words
(32 bits each) may be loaded. If Transmit Status Register bit
TFEMPTY equals “0” then only the available positions may be
loaded. If all 32 positions are full, Transmit Status Register bit
TFFULL is asserted. Further attempts to load the Transmit FIFO are
ignored until at least one ARINC 429 word is transmitted.
The Transmit FIFO half-full flag (Transmit Status Register bit
TFHALF) equals “0” when the Transmit FIFO contains less than 16
words. When TFHALF equals “0”, the system microprocessor can
safely initiate a 16-word ARINC 429 write sequence.
In normal operation (Transmit Control Register bit TPARITY = ”1”),
the 32nd bit transmitted is an odd parity bit. If Transmit Control
Register bit PARITY equals “0”, all 32 bits loaded into the Transmit
FIFO are treated as data and are transmitted.
The Transmit and Receive FIFOs may be cleared using Software
Reset (SPI op-code 0x44). The Transmit FIFO should be cleared
after a self-test before starting normal operation to avoid inadvertent
transmission of test data.
DATA TRANSMISSION
If Transmit Control Register bit TMODE equals “1”, ARINC 429 data
is transmitted immediately following the CS rising edge of the SPI
instruction that loaded data into the Transmit FIFO. Writing Transmit
Control Register bit TMODE to “0” allows the software to control
transmission timing; each time an SPI op-code 0x40 is executed, all
loaded Transmit FIFO words are transmitted. If new words are
loaded into the Transmit FIFO before transmission stops, the new
words will also be output. Once the Transmit FIFO is empty and
transmission of the last word is complete, the FIFO can be loaded
with new data which is held until the next SPI 0x40 instruction is
executed. Once transmission is enabled, the FIFO positions are
incremented with the top register loading into the data transmission
shift register. Within 2.5 data clocks the first data bit appears at
TXAOUT and TXBOUT. The 31 or 32 bits in the data transmission
shift register are presented sequentially to the outputs in the ARINC
429 format with the following timing:
ARINC DATA BIT TIME
DATA BIT TIME
NULL BIT TIME
WORD GAP TIME
HIGH SPEED
10 Clocks
5 Clocks
5 Clocks
40 Clocks
LOW SPEED
80 Clocks
40 Clocks
40 Clocks
320 Clocks
A word counter detects when all loaded positions have been
transmitted and sets the Transmit Status Register TFEMPTY bit
high.
TRANSMITTER PARITY
The parity generator counts the Ones in the 31-bit word. The 32nd
bit transmitted will make parity odd. Setting Transmit Control
Register bit TPARITY to “0” bypasses the parity generator, and
allows 32 bits of data to be transmitted.
SYSTEM OPERATION
The receivers are independent of the transmitter. Therefore,
control of data exchanges is strictly at the option of the user. The
only restrictions are:
1. The received data will be overwritten if the Receive FIFO is
full and at least one location is not retrieved before the next
complete ARINC 429 word is received.
2. The Transmit FIFO can store 32 words maximum and
ignores attempts to load additional data when full.
DC/DC CONVERTER
The HI-3593 requires only a single +3.3V power supply. An
integrated inverting / non-inverting voltage doubler generates the
rail voltages (+/- 6.6V) which then power the line driver to produce
the required +/- 5V ARINC 429 signal levels.
The internal dual-polarity charge pump requires four external
capacitors, two for each polarity generated by the doubler. Pins CP+
and CP- connect the external “fly” capacitor, CFLY, to the positive
portion of the doubler, resulting in twice VDD at the V+ pin. An output
“hold” capacitor, COUT, is placed between V+ and GND. COUT
should be ten times the size of CFLY. The inverting negative portion
of the converter works in a similar fashion, with CFLY and COUT
placed between CN+ / CN- and V- / GND respectively. Note that low
ESR capacitors should be used. Recommended values are given in
the block diagram on page 2.
LINE DRIVER OPERATION
The line driver in the HI-3593 directly drives the ARINC 429 bus.
The two ARINC 429 outputs (TXAOUT and TXBOUT) provide a
differential voltage to produce a +10V One, a -10V Zero, and a 0 Volt
Null. Transmit Control Register bit RATE controls both the
transmitter data rate and the slope of the differential output signal.
No additional hardware is required to control the slope.
Writing Transmit Control Register bit RATE to “0” causes a 100
Kbit/s data rate and a slope of 1.5 µs on the ARINC 429 outputs.
Setting RATE to “1” causes a 12.5 Kbit/s data rate and a slope of
10µs. Slope rate is set by an on-chip resistor and capacitor and
tested to be within ARINC 429 specification requirements.
LINE DRIVER OUTPUT PINS
The HI-3593 TXAOUT and TXBOUT pins have 37.5 Ohms in series
with each line driver output, and may be directly connected to an
ARINC 429 bus. The alternate AMPA and AMPB pins have 5 Ohms
of internal series resistance and require external 32.5 ohm resistors
at each pin. AMPA and AMPB are for applications where external
series resistance is applied, typically for lightning protection
HOLT INTEGRATED CIRCUITS
12
HI-3593
FUNCTIONAL DESCRIPTION (cont.)
mum ARINC 429 data threshold and just above the standard 2.5
volt maximum ARINC 429 null threshold.
devices.
The line driver outputs TXAOUT, TXBOUT, AMPA and AMPB may
be programmed to a high impedance state, allowing multiple line
drivers to be connected to a single ARINC 429 bus. To tri-state the
outputs bit HIZ in the Transmit Control Register must be
programmed to a “1”. Note that all other functions of the HI-3593
continue to operate as usual even though the outputs are tri-stated.
LINE RECEIVER INPUT PINS
The HI-3593 has two sets of Line Receiver input pins for each of
the two receivers, RINxA/B and RINxA/B-40. Only one pair may
be used to connect to the ARINC 429 bus. The unused pair must
be left floating. The RINxA/B pins may be connected directly to the
ARINC 429 bus. The RINxA/B-40 pins require external 40K ohm
resistors in series with each ARINC input. These do not affect the
ARINC receiver thresholds. By keeping excessive voltage outside
the device, this option is helpful in applications where lightning protection is required.
When using the RINxA/B-40 pins, each side of the ARINC 429 bus
must be connected through a 40K ohm series resistor in order for
the chip to detect the correct ARINC 429 levels. The typical 10 Volt
differential signal is translated and input to a window comparator
and latch. The comparator levels are set so that with the external
40K ohm resistors, they are just below the standard 6.5 volt mini-
Please refer to the Holt AN-300 Application Note for additional
information and recommendations on lightning protection of Holt
line drivers and line receivers.
MASTER RESET (MR)
Application of a Master Reset from the MR pin or execution
of Opcode (0x04) causes immediate termination of data
transmission and reception and clears the receive control
registers, transmit control register, ACLK and Flag/Interrupt
Registers to the default states. All FIFOs will be emptied and
status flags are set to the default state (TFULL is reset,
TEMPTY is set). NOTE: Reading an EMPTY FIFO may
result in invalid data.
SOFTWARE RESET
Opcode (0x044) clears the transmit and receive FIFOs and
the Priority-Label Registers only. All other registers are
unaffected by Software Reset.
TPARITY
32 BIT PARALLEL
LOAD SHIFT REGISTER
BIT CLOCK
PARITY
GENERATOR
DATA AND
NULL TIMER
SEQUENCER
LINE DRIVER
TXAOUT
TXBOUT
HIZ
BIT
AND
WORD GAP
COUNTER
WORD CLOCK
START
SEQUENCE
32 x 32 FIFO
ADDRESS
TFFULL
WORD COUNTER
AND
FIFO CONTROL
LOAD
TFHALF
TFEMPTY
INCREMENT
WORD COUNT
FIFO
LOADING
SEQUENCER
SCK
SPI COMMANDS
CS
SI
SPI INTERFACE
SPI COMMANDS
DATA
CLOCK
SO
DIV[3:0]
FIGURE 4.
DATA CLOCK
DIVIDER
TRANSMITTER BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
13
ACLK
HI-3593
SERIAL PERIPHERAL INTERFACE
SERIAL PERIPHERAL INTERFACE (SPI) BASICS
The SPI protocol transfers serial data as 8-bit bytes. Once
CS chip select is asserted, the next 8 rising edges on SCK
latch input data into the master and slave devices, starting
with each byte’s most-significant bit. The HI-3593 SPI can
be clocked at 10 MHz.
The HI-3593 uses an SPI synchronous serial interface for
host access to internal registers and data FIFOs. Host
serial communication is enabled through the Chip Select
(CS) pin, and is accessed via a three-wire interface
consisting of Serial Data Input (SI) from the host, Serial
Data Output (SO) to the host and Serial Clock (SCK). All
read / write cycles are completely self-timed.
Multiple bytes may be transferred when the host holds CS
low after the first byte transferred, and continues to clock
SCK in multiples of 8 clocks. A rising edge on CS chip
select terminates the serial transfer and reinitializes the
HI-3593 SPI for the next transfer. If CS goes high before a
full byte is clocked by SCK, the incomplete byte clocked
into the device SI pin is discarded.
The SPI (Serial Peripheral Interface) protocol specifies
master and slave operation; the HI-3593 operates as an
SPI slave.
In the general case, both master and slave simultaneously
send and receive serial data (full duplex), per Figure 5
below. However the HI-3593 operates half duplex,
maintaining high impedance on the SO output, except
when actually transmitting serial data. When the HI-3593
is sending data on SO during read operations, activity on
its SI input is ignored. Figures 6 and 7 show actual
behavior for the HI-3593 SO output.
The SPI protocol defines two parameters, CPOL (clock
polarity) and CPHA (clock phase). The possible CPOLCPHA combinations define four possible "SPI Modes".
Without describing details of the SPI modes, the HI-3593
operates in mode 0 where input data for each device (
master and slave) is clocked on the rising edge of SCK,
and output data for each device changes on the falling
edge (CPHA = 0, CPOL = 0). Be sure to set the host SPI
logic for mode 0.
As seen in Figure 5, SPI Mode 0 holds SCK in the low state
when idle.
SCK (SPI Mode 0)
SI
SO
High Z
0
1
2
3
4
5
6
7
MSB
LSB
MSB
LSB
CS
FIGURE 5. Generalized Single-Byte Transfer Using SPI Protocol Modes 0
HOLT INTEGRATED CIRCUITS
14
High Z
HI-3593
HOST SERIAL PERIPHERAL INTERFACE, cont.
HI-3593 SPI COMMANDS
Multiple byte read or write cycles may be performed by
transferring more than one byte before CS is negated.
Table 1. defines the required number of bytes for each
instruction.
For the HI-3593, each SPI read or write operation begins
with an 8-bit command byte transferred from the host to the
device after assertion of CS. Since HI-3593 command byte
reception is half-duplex, the host discards the dummy byte
it receives while serially transmitting the command byte.
Note: SPI Instruction op-codes not shown in Table 1 are
“reserved” and must not be used. Further, these op-codes
will not provide meaningful data in response to read
commands.
Figures 6 and 7 show read and write timing as it appears
for a single-byte and dual-byte register operation. The
command byte is immediately followed by a data byte
comprising the 8-bit data word read or written. For a single
register read or write, CS is negated after the data byte is
transferred.
0
1
2
3
4
5
6
Two instruction bytes cannot be “chained”; CS must
be negated after the command, then reasserted for the
following Read or Write command.
7
0
1
2
3
4
5
6
7
SCK
MSB
LSB
SI
Op-Code Byte
LSB MSB
MSB
High Z
SO
High Z
Data Byte
CS
Host may continue to assert CS
here to read sequential word(s)
when allowed by the instruction.
Each word needs 8 SCK clocks.
FIGURE 6. Single-Byte Read From a Register
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
SPI Mode 0
MSB
LSB MSB
LSB
LSB MSB
SI
Op-Code Byte
SO
Data Byte 0
Data Byte 1
High Z
CS
Host may continue to assert CS
here to write sequential byte(s)
when allowed by the SPI instruction.
Each byte needs 8 SCK clocks.
FIGURE 7. 2-Byte Write example
HOLT INTEGRATED CIRCUITS
15
HI-3593
TIMING DIAGRAMS
SERIAL INPUT TIMING DIAGRAM
t CPH
t CYC
CS
tCHH
t SCKF
t CES
t CEH
SCK
t DS
t SCKR
t DH
SI
MSB
LSB
SERIAL OUTPUT TIMING DIAGRAM
t CPH
t CYC
CS
t SCKH
tSCKL
SCK
t CHZ
t DV
SO
MSB
Hi Impedance
LSB
Hi Impedance
DATA RATE - EXAMPLE PATTERN
TXAOUT
ARINC BIT
TXBOUT
DATA
NULL
DATA
NULL
DATA
WORD GAP
BIT 32
BIT 31
BIT 30
NULL
BIT 1
NEXT WORD
RECEIVER OPERATION
BIT 31
ARINC DATA
BIT 32
FLAGS (1)
tINTW
R1INT / R2INT
tRFLG
tRXR
tSPIF
CS
SPI INSTRUCTION (E.g. 0xA0)
SI
ARINC
BIT 32
ARINC
BIT 31
ARINC
BIT 30
SO
(1) Receiver status flag outputs: R1FLAG, R2FLAG, MB1-1, MB1-2, MB1-3, MB2-1, MB2-2, MB2-3
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ARINC
BIT 1
HI-3593
TIMING DIAGRAMS (cont.)
OUTPUT WAVEFORMS
ARINC BIT
DATA
BIT 1
ARINC BIT
DATA
BIT 2
ARINC BIT
DATA
BIT 32
+5V
+5V
AOUT
-5V
+5V
BOUT
-5V
-5V
tfx
+10V
+10V
90%
V
DIFF
(AOUT - BOUT)
tfx
10%
trx
one level
trx
10%
zero level
90%
null level
-10V
TRANSMITTING DATA
CS
SPI INSTRUCTION 0x0C
SPI INSTRUCTION 0x40
SI
TEMPTY /
TFULL
t TFLG
t DATT
AOUT
t SDAT
BOUT
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HI-3593
HEAT SINK - CHIP-SCALE PACKAGE ONLY
The HI-3593PCx uses a 44-pin plastic chip-scale package.
This package has a metal heat sink pad on its bottom
surface. This heat sink is electrically isolated from the die.
To enhance thermal dissipation, the heat sink can be
soldered to matching circuit board pad.
ABSOLUTE MAXIMUM RATINGS
Supply Voltages VDD ......................................... -0.3V to +5.0V
V+ ......................................................... +7.0V
V- ......................................................... -7.0V
Power Dissipation at 25°C
Plastic Quad Flat Pack ............... 1.5 W, derate 10mW/°C
Voltage at pins RINxx-xx .................................. -120V to +120V
DC Current Drain per digital input pin ........................... ±10mA
Voltage at pins TXAOUT, TXBOUT, AMPA, AMPB ......... V- to V+
Storage Temperature Range ........................ -65°C to +150°C
Voltage at any other pin ............................... -0.3V to VDD +0.3V
Operating Temperature Range (Industrial): ..... -40°C to +85°C
(Hi-Temp): ..... -55°C to +125°C
Solder temperature (Leads) .................... 280°C for 10 seconds
(Package) .......................................... 220°C
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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HI-3593
DC ELECTRICAL CHARACTERISTICS
VDD = 3.3V, TA = Operating Temperature Range (unless otherwise specified).
LIMITS
PARAMETER
ARINC 429 INPUTS
-
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
Pins RIN1/2A, RIN1/2B, RIN1/2A-40 (with external 40KOhms), RIN1/2B-40 (with external 40KOhms)
Differential Input Voltage:
(RIN1A to RIN1B, RIN2A to RIN2B)
ONE
ZERO
NULL
Input Resistance:
VIH
VIL
VNUL
Common mode voltages
less than ±25V with
respect to GND
6.5
-13.0
-2.5
10.0
-10.0
0
13.0
-6.5
2.5
V
V
V
140
140
100
-
KW
KW
KW
200
µA
µA
20
20
20
pF
pF
pF
20% VDD
V
V
Differential
To GND
To VDD
RI
RG
RH
-
Input Sink
Input Source
IIH
IIL
-450
Differential
To GND
To VDD
CI
CG
CH
Input Voltage HI
Input Voltage LO
VIH
VIL
Input Sink
Input Source
Pull-down Current (MR, SI, SCK, ACLK pins)
Pull-up current (CS pin)
IIH
IIL
IPD
IPU
Input Current:
Input Capacitance:
(Guaranteed but not tested)
(RINxA to RINxB)
LOGIC INPUTS
Input Voltage:
Input Current:
80% VDD
1.5
µA
µA
µA
µA
-1.5
60
-60
ARINC 429 OUTPUTS - Pins TXAOUT, TXBOUT, (or AMPA, AMPB with external 32.5 Ohms)
ARINC output voltage (Ref. To GND)
One or zero
Null
VDOUT
VNOUT
No load and magnitude at pin,
4.50
-0.25
5.00
5.50
0.25
V
V
ARINC output voltage (Differential)
One or zero
Null
VDDIF
VNDIF
No load and magnitude at pin,
9.0
-0.5
10.0
11.0
0.5
V
V
IOUT
Momentary short-circuit current
80
Logic "1" Output Voltage
Logic "0" Output Voltage
VOH
VOL
IOH = -100µA
IOL = 1.0mA
90%VDD
Output Sink
Output Source
IOL
IOH
VOUT = 0.4V
VOUT = VDD - 0.4V
1.6
ARINC output current
mA
LOGIC OUTPUTS
Output Voltage:
Output Current:
Output Capacitance:
CO
10% VDD
V
V
-1.0
mA
mA
15
pF
OPERATING VOLTAGE RANGE
VDD
3.15
3.45
V
OPERATING SUPPLY CURRENT
Transmitting Data in High-Speed Mode.
IDD
Outputs Unloaded
50
mA
Transmitting Data in High-Speed Mode.
IDDL
400 Ohm Differential Output Load
75
mA
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HI-3593
AC ELECTRICAL CHARACTERISTICS
VDD = 3.3V, TA = Operating Temperature Range and fclk=1MHz +0.1%
LIMITS
PARAMETER
SYMBOL
UNITS
MIN
TYP
MAX
SPI INTERFACE TIMING
SCK clock period
CS active after last SCK rising edge
CS setup time to first SCK rising edge
CS hold time after last SCK falling edge
CS inactive between SPI instructions
SPI SI Data set-up time to SCK rising edge
SPI SI Data hold time after SCK rising edge
SCK rise time
SCK fall ime
SCK pulse width high
SCK pulse width low
SO valid after SCK falling edge
SO high-impedance after SCK falling edge
MR pulse width
tCYC
tCHH
tCES
tCEH
tCPH
tDS
tDH
tSCKR
tSCKF
tSCKH
tSCKL
tDV
tCHZ
tMR
100
10
10
10
55
10
10
10
10
20
25
35
30
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RECEIVER TIMING
Delay - Last bit of received ARINC word to Receive Flag change - Hi Speed
Delay - Last bit of received ARINC word to Receive Flag change - Lo Speed
Received data available to SPI interface. RxFLAG to CS active
SPI receiver read FIFO instruction to RxFLAG
RxINT pulse width
TRANSMITTER TIMING
tRFLG
tRFLG
tRXR
tSPIF
tINT
SPI transmit data write (FIFO Flag Empty or Full)
FIFO Flag delay after enable transmit instruction - Hi Speed
FIFO Flag delay to ARINC 429 data output - Hi Speed
FIFO Flag delay to ARINC 429 data output - Lo Speed
Line driver transition differential times:
high to low
High Speed
low to high
Low Speed
high to low
low to high
tTFLG
tDATT
tSDAT
tSDAT
tfx
trx
tfx
trx
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16
126
0
0
tCYC
500
1.0
1.0
5.0
5.0
1.5
1.5
10
10
µs
µs
ns
ns
ns
0
2
40
320
ns
µs
µs
µs
2.0
2.0
15
15
µs
µs
µs
µs
HI-3593
ORDERING INFORMATION
HI - 3593 xx x x
PART
NUMBER
Blank
LEAD
FINISH
Tin / Lead (Sn / Pb) Solder
100% Matte Tin (Pb-free, RoHS compliant)
F
PART
NUMBER
TEMPERATURE
RANGE
FLOW
BURN
IN
I
-40°C TO +85°C
I
No
T
-55°C TO +125°C
T
No
M
-55°C TO +125°C
M
Yes
PART
NUMBER
PACKAGE
DESCRIPTION
PC
44 PIN PLASTIC CHIP-SCALE, QFN (44PCS)
PQ
44 PIN PLASTIC QUAD FLAT PACK, PQFP (44PTQS)
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HI-3593
REVISION HISTORY
P/N
Rev
Date
DS3593 NEW 02/03/08
A
08/11/11
Description of Change
Initial Release
Modified AC Electrical Characteristics for 10 MHZ SPI operation.
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HI-3593 PACKAGE DIMENSIONS
inches (millimeters)
44-PIN PLASTIC CHIP-SCALE PACKAGE (QFN)
Package Type: 44PCS
.276
BSC
(7.00)
.203 ± .006
(5.15 ± .15)
.020 BSC
(0.50)
.276
BSC
(7.00)
.203 ± .006
(5.15 ± .15)
Top View
Bottom
View
.010
(0.25) typ
.039
max
(1.00)
.016 ± .002
(0.40 ± .05)
.008 typ
(0.2)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
inches (millimeters)
44-PIN PLASTIC QUAD FLAT PACK (PQFP)
Package Type:
44PTQS
.006 MAX.
(.15)
.0315
BSC
(.80)
.394 ± .004
(10.0 ± .10)
SQ.
.547 ± .010
(13.90 ± .25)
SQ.
.014 ± ..002
(.35 ± .05)
.035 ± .006
(.88 ± .15)
.012
R MAX.
(.30)
See Detail A
.055 ± .002
(1.4 ± .05)
.063
MAX.
(1.6)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
.005
R MIN. Detail A
(.13)
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0° £ Q £ 7°