INNOVASIC IA59032

IA59032
32-Bit High-Speed Microprocessor Slice
Data Sheet
August 19, 2008
IA59032
32-Bit High-Speed Microprocessor Slice
Data Sheet
IA211001108-03
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IA59032
32-Bit High-Speed Microprocessor Slice
Copyright
Data Sheet
August 19, 2008
2008 by Innovasic Semiconductor, Inc.
Published by Innovasic Semiconductor, Inc.
3737 Princeton Drive NE, Suite 130, Albuquerque, NM 87107
fido®, fido1100®, and SPIDER are trademarks of Innovasic Semiconductor, Inc.
I2C™ Bus is a trademark of Philips Electronics N.V.
Motorola is a registered trademark of Motorola, Inc.
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IA59032
32-Bit High-Speed Microprocessor Slice
Data Sheet
August 19, 2008
TABLE OF CONTENTS
Features ............................................................................................................................................4
Description .......................................................................................................................................6
BLOCK DIAGRAM ..............................................................................................................6
I/O Signal Description ...................................................................................................................10
FUNCTIONAL TABLES ....................................................................................................11
ALU SOURCE OPERAND CONTROL ....................................................................11
ALU FUNCTION CONTROL ....................................................................................11
ALU DESTINATION CONTROL .............................................................................11
SOURCE OPERAND AND ALU FUNCTION MATRIX ........................................12
SOURCE OPERANDS AND ALU FUNCTIONS ..............................................................13
ALU LOGIC MODE FUNCTIONS ...........................................................................13
ALU ARITHMETIC MODE FUNCTIONS ...............................................................14
AC/DC Parameters: .......................................................................................................................15
DC Characteristics: ........................................................................................................................15
CYCLE TIME AND CLOCK CHARACTERISTICS: ..............................................16
OUTPUT ENABLE/DISABLE TIME: .......................................................................16
SET-UP AND HOLD TIMES RELATIVE TO CLOCK (CP) INPUT: .....................17
Packaging Information ...................................................................................................................18
100 CPGA PACKAGE................................................................................................18
Ordering Information .....................................................................................................................19
Revision History ............................................................................................................................19
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IA59032
32-Bit High-Speed Microprocessor Slice
Data Sheet
August 19, 2008
Features
Eight CMOS 2901 Type Devices in a Single Package
32 x 32 Dual Port RAM
High Speed Operation
- 23MHz Read-Modify-Write Cycle
Fully Firmware Compatible with the 2901
The IA59032 is a "plug-and-play" drop-in replacement for the original WSI™ WS59032. This replacement IC
has been developed using innovASIC’s MILESTM, or Managed IC Lifetime Extension System, cloning
technology. This technology produces replacement ICs far more complex than "emulation" while ensuring
they are compatible with the original IC. MILESTM captures the design of a clone so it can be produced even
as silicon technology advances. MILESTM also verifies the clone against the original IC so that even the
"undocumented features" are duplicated. This data sheet documents all necessary engineering information
about the IA59032 including functional and I/O descriptions, electrical characteristics, and applicable timing.
WSI is a trademark of Waferscale Integration, Inc.
100 PIN PGA PACKAGE:
N M L K J H G F E D C B A
1
2
3
4
5
6
7
8
9
10
11
12
13
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ + + + + + + + + +
+ + + + + + + + + +
+ +
+ + +
+
+
+
+ +
+
+ +
+
+ +
+
+
+ + +
+
+ + + + + + + + + +
+ + + + + + + + + +
+
+
+
+
+
+
+
+
+
+
+
+
+
A B C D E F G H J K L M N
1
2
3
4
5
6
7
8
9
10
11
12
13
1
2
3
4
5
6
7
8
9
10
11
12
13
N M L K J H G F E D C B A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ + + + + + + + + + +
+ + + + + + + + + + +
+
+ + +
+ +
+ +
+ +
+
+ + +
+
+ + +
+
+ + +
+ +
+ +
+ + +
+ +
+ + + + + + + + + + +
+ + + + + + + + + + +
1
2
3
4
5
6
7
8
9
10
11
12
13
A B C D E F G H J K L M N
TOP VIEW
BOTTOM VIEW
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IA59032
32-Bit High-Speed Microprocessor Slice
Data Sheet
August 19, 2008
PIN DESIGNATOR:
PIN
NAME
VCC
VCC
GND
GND
GND
GND
RAM0
RAM31
Q0
Q31
CLK
CIN
CN-32
OVR
F-0
F31
OEN
A0
A1
A2
A3
A4
B0
B1
B2
PGA
GRID #
N1
A1
N7
G13
A12
C6
M7
B6
L7
A6
A7
N13
A9
C8
C13
B8
M12
J1
J2
K1
K2
L1
M1
L2
M2
PIN
NAME
B3
B4
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
PGA
GRID #
N2
M3
N6
M6
L6
N5
M5
N4
M4
N3
H3
H2
H1
G1
G3
G2
F1
F2
F3
E1
E2
D1
D2
C1
C2
PIN
NAME
D23
D24
D25
D26
D27
D28
D29
D30
D31
I0
I1
I2
I3
I4
I5
I6
I7
I8
Y0
Y1
Y2
Y3
Y4
Y5
Y6
IA211001108-03
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PGA
GRID #
B1
B2
B3
A2
A3
B4
A4
B5
A5
N8
M8
L8
N9
M9
N10
A8
B7
C7
M10
N11
N12
M11
M13
L12
L13
PIN
NAME
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30
Y31
PGA
GRID #
K12
K13
J12
J13
H11
H12
H13
G12
G11
F13
F12
F11
E13
E12
D13
D12
B13
C12
A13
B12
B11
A11
B10
A10
B9
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IA59032
32-Bit High-Speed Microprocessor Slice
Data Sheet
August 19, 2008
Description
The IA59032 is a 32-bit high-speed microprocessor that combines the functions of eight 2901 4-bit
slice processors and distributed look-ahead carry generation on a single high performance CMOS
device. The IA59032 dual port RAM is 32-bits wide and 32 words deep. This architecture provides
grater flexibility and eases the task of generating new microcode while maintaining 100%
compatibility with existing 2901 based microcode.
BLOCK DIAGRAM
0
ALU SOURCE
I(8:0)
INSTRUCTION BUS
2
3
4
ALU FUNCTION
5
6
7
MICROINSTRUCTION DECODE
1
DESTINATION
CONTROL
8
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IA59032
32-Bit High-Speed Microprocessor Slice
Data Sheet
August 19, 2008
FIGURE 1 (CONT):
RAM SHIFT
RAM0
A(READ)
ADDRESS
Q-SHIFT
Q31
B
WE
CP
Q0
RAM31
32X32 2 PORT RAM
A
OUT
B(READ/WRITE)
ADDRESS
A
B
OUT
Q REGISTER
LOGIC
"0"
B
0
F
Q
ALU SOURCE MUX
D(31:0)
R
S
FZERO
F31
8 FUNCTION 32-BIT ALU
F
Cn
A
OEn
OVR
OUTPUT DATA MUX
Cn32
F
Y(31:0)
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IA59032
32-Bit High-Speed Microprocessor Slice
Data Sheet
August 19, 2008
A detailed block diagram for the IA59032 is shown in Error! Reference source not found.. The
two key elements in the block diagram are the 32 word by 32-bit 2-port RAM and the high-speed
ALU.
Data in any of the 32 words of the RAM can be read from the A-port of the RAM as controlled by
the 4-bit A address field input. Likewise, data in any of the 32 words of the RAM as defined by the
B address field input can be simultaneously read from the B-port of the RAM. The same code can
be applied to the A select field and B select field in which case the identical file data will appear at
both the RAM A-port and B-port outputs simultaneously.
When enabled by the RAM write enable (CP low), new data is always written into the file (word)
defined by the B address field of the RAM. The RAM data input field is driven by a 3-input mux.
This configuration is used to shift the ALU output data F if desired. This three-input mux scheme
allows the data to be shifted up one bit position, shifted down one bit position, or not shifted in
either direction.
The high speed ALU can perform three binary arithmetic and five logic operations on the two 32-bit
input words R and S. The R input field is driven from a 2-input mux, while the S input field is
driven by a 3-input mux. Both muxes also have an inhibit capability; that is, no data is passed. This
is equivalent to a “zero” source operand.
Referring to Error! Reference source not found., the ALU R-input mux has the RAM A-port and
the direct data inputs (D) connected as inputs. Likewise, the ALU S-input mux has the RAM Aport, B-port, and the Q register connected as inputs.
This muxing scheme provides the capability of selecting various pairs of the A, B, D, Q, and zero
inputs as source operands to the ALU. These five inputs, when taken two at a time, result in ten
possible combinations of source operand pairs. The I(2:0) inputs are the microinstruction inputs
used to select the ALU source operands.
The two source operands not fully described as yet are the D input and the Q input. The D input is
the 32-bit wide direct data field input. This port is used to insert all data into the working registers
inside the device. Likewise, this input can be used in the ALU to modify any of the internal data
files. The Q register is a separate 32-bit file intended primarily for multiplication and division
routines but it can also be used as an accumulator or holding register for some applications.
The ALU itself is capable of performing three binary arithmetic and five logic functions. The I(5:3)
inputs are used to select the ALU function.
The ALU has three status-oriented outputs. These are F31, FZERO, and OVR. The F31 output is
the most significant (sign) bit of the ALU and can be used to determine positive or negative results
without enabling the three-state data outputs. F31 is non-inverted with respect to the sign bit
output Y(31). The FZERO output is used for zero detect. It is an open-collector output. FZERO
is HIGH when all F outputs are LOW. The overflow output (OVR) is used to flag arithmetic
operations that exceed the available two’s complement number range. The OVR output is HIGH
when overflow exists.
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IA59032
32-Bit High-Speed Microprocessor Slice
Data Sheet
August 19, 2008
The ALU data output is routed to several destinations. It can be a data output of the device and it
can also be stored in the RAM or the Q register. Eight possible combinations of ALU destination
functions are available, as defined by the I(8:6) inputs.
The 32-bit data output field (Y) features three-state outputs. An output control (OEn) is used to
enable the three-state outputs. When OEn is HIGH, the Y outputs are in the high-impedance state.
A two input mux is also used at the data output such that either the A-port of the RAM or the ALU
outputs (F) are selected at the device Y outputs. I(8:6) inputs control this selection.
As was discussed previously, the RAM inputs are driven from a three-input mux. This allows the
ALU outputs to be entered non-shifted, shifted up one position (X2) or shifted down one position
(/2). The shifter has two ports; one is labeled RAM0 and the other is RAM31. Both of these ports
consist of a buffer driver with a three-state output and an input to the mux. Thus, in the shift up
mode, the RAM31 buffer is enabled and the RAM0 mux input is enabled. Likewise, is in the shift
down mode, the RAM0 buffer and RAM31 input are enabled. In the no-shift mode, both buffers
are in the high-impedance state and the mux inputs are not selected. The I(8:6) inputs control the
shifter.
Similarly, the Q register is driven from a 3-input mux. In the no-shift mode, the mux enters the
ALU data into the Q register. In either the shift-up or shift-down mode, the mux selects the Q
register data appropriately shifted up or down. The Q shifter also has two ports; Q0 and Q31. The
operations of these two ports are similar to the RAM shifter and are also controlled from the I(8:6)
inputs.
The clock input controls the RAM, Q register, and the A and B data latches. When enabled, data is
clocked into the Q register on the LOW to HIGH transition of the clock. When CP is HIGH, the
A and B latches are open and will pass whatever data is present at the RAM outputs. When CP is
LOW, the latches are closed and will retain the last data entered. New data will be written into the
RAM defined by the B address field when the clock input is LOW.
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IA59032
32-Bit High-Speed Microprocessor Slice
Data Sheet
August 19, 2008
I/O Signal Description
The diagram below describes the I/O characteristics for each signal on the IC. The signal names
correspond to the signal names on the pinout diagrams provide.
I/O CHARACTERISTICS:
SIGNAL NAME
I/O
A(4:0)
I
B(4:0)
I
I(8:0)
I
Q31
RAM31
I/O
Q0
RAM0
I/O
D(31:0)
I
Y(31:0)
O
DESCRIPTION
The five address inputs to the on board RAM used to select word to be displayed
throught the A-port
Addresses which select the word of on board RAM which is to be diplayed through the Bport and into which data is written when the clock is low.
The nine instruction control lines. Used to determine what data sources will be applied
to the ALU(I(2:0)), what function the ALU will perform (I(5:3)), and what data is to be
deposited in the Q-register or on board RAM (I(8:6)).
Signal paths at the MSB of the on-board RAM and the Q-register which are used for
shifting data. When the destination code on I(8:6) indicates an up shift(Octal 6 or 7) the
three state outputs are enabled and the MSB of the Q-register is available on the Q31 pin.
Otherwise the pins appear as inputs. When the destination code calls for a down shift the
pins are used as the data inputs to the MSB of the Q-register (Octal 4) and RAM (Octal 4
and 5).
Shift lines similar to the Q31 and RAM 31; however the decription is applied to the LSB
of RAM and the Q-register.
Direct data inputs which may be selected as one of the ALU data sources for entering
data into the device. D0 is the LSB.
Tri-statable outputs which, when enabled, display either the data on the A-port of the
register stack or the outputs of the ALU as determined by the destination code I(8:6).
OEn
I
OVR
O
Output enable. When HIGH, the Y outputs are in the high impedance state. When
LOW, either the contents of the A-register or the outputs of the ALU are displayed on
Y(31:0).
Overflow. This signal indicates that an overflow into the sign bit has occurred as a result
of a two's complement operation.
FZERO
O
This output, when HIGH, indicates that the result of an ALU operation is zero.
F31
Cn
Cn32
O
I
O
The most significnt ALU output bit.
CP
I
The carry-in to the ALU.
The carry-out of the ALU.
The clock input. The clock low time is the write enable to the on-board dual port RAM,
including set-up time fot the A and B - portregisters. The A and B- port outputs change
while the clock is HIGH. The Q-register is latched on the clock LOW-to-HIGH
transition.
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IA59032
32-Bit High-Speed Microprocessor Slice
Data Sheet
August 19, 2008
FUNCTIONAL TABLES
ALU SOURCE OPERAND CONTROL
MNEMONIC
MICRO CODE
ALU
I1
I0
OCTAL CODE
L
L
0
L
H
1
H
L
2
H
H
3
L
L
4
L
H
5
H
L
6
H
H
7
I2
AQ
AB
ZQ
ZB
ZA
DA
DQ
DZ
L
L
L
L
H
H
H
H
SOURCE OPERANDS
R
S
A
Q
A
B
0
Q
0
B
0
A
D
A
D
Q
D
0
ALU FUNCTION CONTROL
MNEMONIC
ADD
SUBR
SUBS
OR
AND
NOTRS
EXOR
EXNOR
I5
MICRO CODE
ALU FUNCTION SYMBOL
I4
I3
OCTAL CODE
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
0
1
2
3
4
5
6
7
R PLUS S
S MINUS R
R MINUS S
R OR S
R AND S
Rn AND S
R EX-OR S
R EX-NOR S
R+S
S-R
R-S
R \/ S
R /\ S
Rn /\ S
R \-/ S
(R \-/ S)n
ALU DESTINATION CONTROL
MNEMONIC
QREG
NOP
RAMA
RAMF
RAMQD
RAMD
RAMQU
RAMU
MICRO CODE
RAM FUNCT'N Q REG FUNCT'N
I8 I7 I6 OCTAL CODE SHIFT LOAD SHIFT
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
0
1
2
3
4
5
6
7
X
X
NONE
NONE
DOWN
DOWN
UP
UP
LOAD
NONE NONE
F Q
NONE
X
NONE
F B
X
NONE
F B
X
NONE
F/2 B DOWN Q/2 Q
F/2 B
X
NONE
2F B
2Q Q
UP
2F B
X
NONE
Y OUTPUT
F
F
A
F
F
F
F
F
RAM SHIFT'R Q SHIFT'R
RAM0 RAM15 Q0
Q15
X
X
X
X
F0
F0
IN0
IN0
X
X
X
X
IN15
IN15
F15
F15
*X Don’t care
B=Register addressed by B inputs
DOWN is toward LSB, UP is toward MSB
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X
X
X
X
Q0
Q0
IN0
X
X
X
X
X
IN15
X
Q15
Q15
IA59032
32-Bit High-Speed Microprocessor Slice
Data Sheet
August 19, 2008
SOURCE OPERAND AND ALU FUNCTION MATRIX
I(5:3)
OCTAL ALU
CODE FUNCTION
0
Cn=L
0
1
A,Q
A,B
A+Q
I(2:0) OCTAL CODE
2
3
4
5
ALU SOURCE (R,S)
0,Q
0,B
0,A
D,A
6
7
D,Q
D,0
A+B
Q
B
A
D+A
D+Q
D
A+B+1
Q+1
B+1
A+1
D+A+1
D+Q+1
D+1
Q-A-1
B-A-1
Q-1
B-1
-A-1
A-D-1
Q-D-1
-D-1
Cn=H
Q-A
B-A
Q
B
-A
A-D
Q-D
-D
Cn=L
A-Q-1
A-B-1
-Q-1
-B-1
A
D-A-1
D-Q-1
D-1
Cn=H
A-Q
A-B
-Q
-B
A+1
D-A
D-Q
D
R OR S
R AND S
Rn AND S
R EXOR S
A \/ Q
A /\ Q
An /\ Q
A \-/ Q
A \/ B
A /\ B
An /\ B
A \-/ B
Q
0
Q
Q
B
0
B
B
A
0
A
A
D \/ A
D /\ A
Dn /\ A
D \-/ A
D \/ Q
D /\ Q
Dn /\ Q
D \-/ Q
D
0
0
D
R plus S
Cn=H
1
Cn=L
A+Q+1
S minus R
2
R minus S
3
4
5
6
* + = PLUS, - = Minus, \/ = OR, /\ = AND, \-/ = EX-OR
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IA59032
32-Bit High-Speed Microprocessor Slice
Data Sheet
August 19, 2008
SOURCE OPERANDS AND ALU FUNCTIONS
Eight source operand pairs are available to the ALU as determined by the I0-I2 instruction inputs.
The ALU performs eight functions; three of which are arithmetic and five of which are logic
functions. This function selection is controlled by the I3-I5 instruction inputs. When in the
arithmetic mode, the ALU results are also affected by the carry, Cn. In the logic mode, the Cn input
has no effect.
The matrix of Table 4 results when Cn and I0 through I5 are viewed together. Table 5 defines the
logic operation which the IA59032 has the capability to perform while Table 6 demonstrates the
arithmetic operations of the device. Both carry-in HIGH (Cn = 1) and carry-in LOW (Cn = 0) are
defined in these operations.
ALU LOGIC MODE FUNCTIONS
OCTAL
I(5:3), I(2:0)
4,0
4,1
4,5
4,6
3,0
3,1
3,5
3,6
6,0
6,1
6,5
6,6
7,0
7,1
7,5
7,6
7,2
7,3
7,4
7,7
6,2
6,3
6,4
6,7
3,2
3,3
3,4
3,7
4,2
4,3
4,4
4,7
5,0
5,1
5,5
5,6
GROUP
AND
OR
EXOR
EXNOR
INVERT
PASS
PASS
ZERO
MASK
IA211001108-03
Page 13 of 19
FUNCTION
A /\ Q
A /\ B
D /\ A
D /\ Q
A \/ Q
A \/ B
D \/ A
D \/ Q
A \-/ Q
A \-/ B
D \-/ A
D \-/ Q
(A \-/ Q)n
(A \-/ B)n
(D \-/ A)n
(D \-/ Q)n
Qn
Bn
An
Dn
Qn
Bn
An
Dn
Q
B
A
D
0
0
0
0
An /\ Q
An /\ B
Dn /\ A
Dn /\ Q
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IA59032
32-Bit High-Speed Microprocessor Slice
Data Sheet
August 19, 2008
ALU ARITHMETIC MODE FUNCTIONS
OCTAL
I(5:3), I(2,0)
Cn=0(LOW)
Cn=1(HIGH)
GROUP
FUNCTION
ADD
A+Q
A+B
D+A
D+Q
PASS
Q
B
A
D
1,2
1,3
1,4
2,7
2,2
2,3
2,4
1,7
0,0
0,1
0,5
0,6
0,2
0,3
0,4
0,7
1,0
1,1
1,5
1,6
2,0
2,1
2,5
2,6
GROUP
FUNCTION
ADD PLUS ONE
A+Q+1
A+B+1
D+A+1
D+Q+1
INCREMENT
Q+1
B+1
A+1
D+1
DECREMENT
Q-1
B-1
A-1
D-1
PASS
Q
B
A
D
1'S
COMPLEMENT
-Q-1
-B-1
-A-1
-D-1
2'S
COMPLEMENT
(NEGATE)
-Q
-B
-A
-D
SUBTRACT
1'S
COMPLEMENT
Q-A-1
B-A-1
A-D-1
Q-D-1
A-Q-1
A-B-1
D-A-1
D-Q-1
SUBTRACT
2'S
COMPLEMENT
Q-A
B-A
A-D
Q-D
A-Q
A-B
D-A
D-Q
IA211001108-03
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AC/DC Parameters:
Absolute maximum ratings:
Operating Temp (Comm’l)…….........................………...…..0°C to +70°C
(Mil)………………………………..…-55°C to +125°C
Storage temperature.......................................…........……...…- 55°C to 155°C
Voltage on any pin with
respect to GND………….....................................………..…...-0.6V to +7V
Latch Up Protection…................................................….....................>200mA
ESD Protection…………………………………….………….> 2000V
DC Characteristics:
SYMBOL PARAMETER
TEST CONDITIONS
Voh
Output High
Voltage
All outputs
Ioh=*
Vol
Output Low
Voltage
Y(31:0)
Iol=*
All others
Iol=*
Guaranteed Input High Voltage
Input High
Voltage
Vil
Input Low
Voltage
Input Load
Current
High Impedance
Output Current
Guaranteed Input Low Voltage
Power Supply
Current
VCC=Max
Ioz
ICC
MAX
VDD-1.0
UNITS
V
VSS+0.4
V
Iol=*
Vih
Iix
MIN
2
V
0.8
V
VCC=Max, Vin=Gnd or VCC
-10
10
uA
BCC=Max, VO=Gnd or VCC
-50
50
uA
70
85
mA
Comm'l (0C to 70C)
Mil (-55C to 125C)
* As per specific buffer
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CYCLE TIME AND CLOCK CHARACTERISTICS:
READ-MODIFY-WRITE (from select of A, B
registers to end of cycle)
Maximum Clock Frequency to Shift Q (50% duty
cycle, I=432 or 632)
Minimum Clock Low Time
Minimum Clock High
Minimum Clock Period
60ns
23.6 MHz
28ns
30ns
60ns
OUTPUT ENABLE/DISABLE TIME:
From OEn LOW to Y output enable
From OEn HIGH to Y output enable
36ns
30ns
COMBINATIONAL PROPAGATION DELAYS (Cl = 50 pf):
To Output
Y
F31 Cn+32 FZERO OVR
RAM0,
RAM31
Q0,
Q31
From
Input
A,B Address
D(31:0)
Cn
66
45
36
68
45
36
58
35
18
66
45
36
62
35
32
75
48
42
----
I(2:0)
I(5:3)
I(8:6)
A Bypass
ALU
(I=2XX)
46
51
22
48
46
51
---
35
41
---
46
51
---
41
46
---
58
53
22
--
--20
--
Clock
51
51
42
51
48
59
22
IA211001108-03
Page 16 of 19
UNITS
ns
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SET-UP AND HOLD TIMES RELATIVE TO CLOCK (CP) INPUT:
CP
Input
Set up before Hold after
H to L
H to L
A,B Source Address
B Destination Address
D(31:0)
Cn
I(2:0)
I(5:3)
I(8:6)
RAM0,31 and Q0, 31
20
10
----7
--
Set up before Hold after
L to H
L to H
1 (note 3)
53 (note 4)
Do not change (note 2)
-20
-22
-28
-30
Do not change (note 2)
-7
UNITS
0
0
-0
0
0
0
3
*Notes :
1) Dashes indicate that a set-up time constraint or a propagation delay path does not exist.
2) The phrase “Do Not Change” indicates that certain signals must remain LOW for the duration of the
clock LOW time. Otherwise, erroneous operation may be the result.
3) Prior to clock HIGH to LOW transition, source addresses must be stable to allow time for the
source data to be set up before the latch closes. After this transition the 'A' address may be changed. If it
is not being used as a destination, the B address may also be changed. If it is being used as a destination,
the B address must remain stable during the clock LOW period.
4) Set-up time before HIGH to LOW included here.
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Packaging Information
100 CPGA PACKAGE
A
D
e
Q
N
M
L
b
E
K
J
H
G
F
E
D
C
B
A
L
TOP
VIEW
1 2 3 4 5 6 7 8 9 10 11 12 13
BOTTOM
VIEW
A1 INDEX MARK
SEATING PLANE
Ø0.08" MAX
100 CPGA, (13X13 pins)
Symbol
A
b
D
E
e
L
Q
MILLIMETER
MIN
NOM
MAX
2.67
2.92
3.68
0.41
0.46
0.51
33.22
33.53
33.83
33.22
33.53
33.83
33.53
33.53
33.53
IA211001108-03
Page 18 of 19
MIN
0.105
0.016
1.308
1.308
INCH
NOM
0.115
0.018
0
0
0
0
0
MAX
0.145
0
1.332
1.332
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Ordering Information
Part Number
IA59032-CPGA100I
Environmental/ Qual Level
Industrial
Revision History
The table below presents the sequence of revisions to document IA211001108.
Date
August 19, 2008
Revision
03
Description
First edition released.
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