IS31FL3196 6-CHANNEL LIGHT EFFECT LED DRIVER April 2012 GENERAL DESCRIPTION FEATURES IS31FL3196 is a 6-channel light effect LED driver which features two-dimensional auto breathing mode and an audio modulated display mode. It has One Shot Programming mode and PWM Control mode for RGB lighting effects. The maximum output current can be adjusted in 8 levels (5mA~40mA). In PWM Control mode, the PWM duty cycle of each output can be independently programmed and controlled in 256 steps to simplify color mixing. In One Shot Programming mode, the timing characteristics for output current - current rising, holding, falling and off time, can be adjusted individually so that each output can independently maintain a pre-established pattern achieving mixing color breathing or a single color breathing without requiring any additional interface activity, thus saving valuable system resources. The IS31FL3196 includes an audio modulated display mode, wherein the brightness of LED can be modulated by audio signal. There is a cascade pin for the synchronization of two chips. 2.7V to 5.5V supply voltage I2C interface Two groups RGB, single color LED breathing system-free pre-established pattern 6 independently controlled automatic and semiautomatic breathing system-free pre-established pattern 6 independently controlled outputs of 256 PWM steps 8 levels programmable output current Audio mode with AGC function Cascade for the synchronization of chips Over-temperature protection QFN-20 (3mm × 3mm) package APPLICATIONS Mobile phones and other hand-held devices for LED display LED in home appliances IS31FL3196 is available in QFN-20 (3mm × 3mm). It operates from 2.7V to 5.5V over the temperature range of -40°C to +85°C. TYPICAL APPLICATION CIRCUIT Figure 1 Typical Application Circuit Note: The IC should be placed far away from the mobile antenna in order to prevent the EMI. Integrated Silicon Solution, Inc. — www.issi.com Rev.A, 03/27/2012 1 IS31FL3196 Figure 2 Typical Application Circuit (Cascade Mode) Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com Rev.A, 03/27/2012 2 IS31FL3196 PIN CONFIGURATION Package Pin Configuration (Top View) QFN-20 PIN DESCRIPTION No. Pin Description 1 VCC Power supply. 2 C_FILT Filter capacitor for audio control. 3~6 OUT1~OUT4 Current source outputs. 7 GND Ground. 8, 9 OUT5~OUT6 Current source outputs. 10~12 NC No connection. 13 SDB Shutdown the chip when pulled to low. 14 I_AUD Audio current input or output for cascade. 15 R_EXT Input terminal used to connect an external resistor. The value must be about 100kΩ. 16 AD I2C address setting. 17 IN Audio input. 18 SCL I2C serial clock. 19 SDA I2C serial data. 20 CLK/V_BM CLK input or output for cascade. When breathing mark function enable, this pin is V_BM pin. Thermal Pad Connect to GND. Integrated Silicon Solution, Inc. — www.issi.com Rev.A, 03/27/2012 3 IS31FL3196 ORDERING INFORMATION Industrial Range: -40°C to +85°C Order Part No. Package QTY/Reel IS31FL3196-QFLS2-TR QFN-20, Lead-free 2500 Integrated Silicon Solution, Inc. — www.issi.com Rev.A, 03/27/2012 4 IS31FL3196 ABSOLUTE MAXIMUM RATINGS Supply voltage, VCC Voltage at any input pin GND terminal current Maximum junction temperature, TJMAX Storage temperature range, TSTG Operating temperature range, TA ESD (HBM) -0.3V ~ +6.0V -0.3V ~ VCC+0.3V 400mA 150°C -65°C ~ +150°C -40°C ~ +85°C 2kV Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS TA = 25°C, VCC = 2.7V ~ 5.5V, unless otherwise noted. Typical value are TA = 25°C, VCC = 5V. Symbol Parameter Condition Min. Typ. VCC Supply voltage ICC Quiescent power supply current VSDB = VCC 3 ISD Shutdown current VSDB = 0V 1 VSDB = VCC, software shutdown 2 IOUT VHR Output current 2.7 PWM Control Mode, VDS = 0.4V PWM Register(07h~0Ch) = 0xFF Max. Unit 5.5 V mA μA 20 (Note 1) Audio Mode, Gain = 12dB VIN = 0.8VP-P, 1kHz square wave mA 18 (Note 1) Current sink headroom voltage IOUT = 20mA 400 mV Logic Electrical Characteristics (SDA, SCL, SDB, AD) VIL Logic “0” input voltage VCC = 2.7V VIH Logic “1” input voltage VCC = 5.5V IIL Logic “0” input current VINPUT = 0V (Note 2) IIH Logic “1” input current VINPUT = VCC (Note 2) Integrated Silicon Solution, Inc. — www.issi.com Rev.A, 03/27/2012 0.4 1.4 V V 5 5 nA nA 5 IS31FL3196 DIGITAL INPUT SWITCHING CHARACTERISTICS (Note 3) Symbol Parameter Condition Min. Typ. Max. Unit 400 kHz fSCL Serial-Clock frequency tBUF Bus free time between a STOP and a START condition 1.3 μs tHD, STA Hold time (repeated) START condition 0.6 μs tSU, STA Repeated START condition setup time 0.6 μs tSU, STO STOP condition setup time 0.6 μs tHD, DAT Data hold time tSU, DAT Data setup time 100 ns tLOW SCL clock low period 1.3 μs tHIGH SCL clock high period 0.7 μs 0.9 μs tR Rise time of both SDA and SCL signals, receiving (Note 4) 20+0.1Cb 300 ns tF Fall time of both SDA and SCL signals, receiving (Note 4) 20+0.1Cb 300 ns Note 1: The average current of each channel is IOUT. Note 2: All LEDs are on. Note 3: Guaranteed by design. Note 4: Cb = total capacitance of one bus line in pF. ISINK ≤ 6mA. tR and tF measured between 0.3 × VCC and 0.7 × VCC. Integrated Silicon Solution, Inc. — www.issi.com Rev.A, 03/27/2012 6 IS31FL3196 DETAILED DESCRIPTION I2C INTERFACE The IS31FL3196 uses a serial bus, which conforms to the I2C protocol, to control the chip’s functions with two wires: SCL and SDA. The IS31FL3196 has a 7-bit slave address (A7:A1), followed by the R/W bit, A0. Since IS31FL3196 only supports write operations, A0 must always be “0”. The value of bits A1 and A2 are decided by the connection of the AD pin. The complete slave address is: Table 1 Slave Address (Write only): Bit A7:A3 A2:A1 A0 Value 11001 AD 0 AD connected to GND, AD = 00; AD connected to VCC, AD = 11; AD connected to SCL, AD = 01; AD connected to SDA, AD = 10; The SCL line is uni-directional. The SDA line is bi-directional (open-collector) with a pull-up resistor (typically 4.7kΩ). The maximum clock frequency specified by the I2C standard is 400kHz. In this discussion, the master is the microcontroller and the slave is the IS31FL3196. The timing diagram for the I2C is shown in Figure 3. The SDA is latched in on the stable high level of the SCL. When there is no interface activity, the SDA line should be held high. Figure 3 Figure 4 Integrated Silicon Solution, Inc. — www.issi.com Rev.A, 03/27/2012 The “START” signal is generated by lowering the SDA signal while the SCL signal is high. The start signal will alert all devices attached to the I2C bus to check the incoming address against their own chip address. The 8-bit chip address is sent next, most significant bit first. Each address bit must be stable while the SCL level is high. After the last bit of the chip address is sent, the master checks for the IS31FL3196’s acknowledge. The master releases the SDA line high (through a pull-up resistor). Then the master sends an SCL pulse. If the IS31FL3196 has received the address correctly, then it holds the SDA line low during the SCL pulse. If the SDA line is not low, then the master should send a “STOP” signal (discussed later) and abort the transfer. Following acknowledge of IS31FL3196, the register address byte is sent, most significant bit first. IS31FL3196 must generate another acknowledge indicating that the register address has been received. Then 8-bit of data byte are sent next, most significant bit first. Each data bit should be valid while the SCL level is stable high. After the data byte is sent, the IS31FL3196 must generate another acknowledge to indicate that the data was received. The “STOP” signal ends the transfer. To signal “STOP”, the SDA signal goes high while the SCL signal is high. Interface Timing Bit Transfer 7 IS31FL3196 Figure 5 Writing to IS31FL3196 REGISTERS DEFINITIONS Table 2 Register Function Address Name Function Table Default 00h Shutdown Register Set software shutdown mode 3 0000 0000 01h LED Control Register OUT1~ OUT6 enable bit 4 0111 0111 03h Configuration Register 1 Set operation mode 5 04h Configuration Register 2 Set output current and audio input gain 6 05h Ramping Mode Register Set the ramping function mode 7 06h Breathing Mark Register Set the breathing mark function 8 PWM Register 6 channels PWM duty cycle data registers 9 Data Update Register Load PWM Registers and LED Control Registers’ data - 11h ~ 16h T0 Register Set the T0 time 10 1Ah ~ 1Bh T1~T3 Register Set the T1~T3 time 11 1Dh ~ 22h T4 Register Set the T4 time 12 26h Time Update Register Load time registers’ data - FFh Reset Register Reset all registers to default value - 07h ~ 0Ch 10h Table 3 00h Shutdown Register 0000 0000 xxxx xxxx 0000 0000 xxxx xxxx Table 4 01h LED Control Register (OUT1~OUT6) Bit D7:D1 D0 Bit D7 D6:D4 D3 D2:D0 Name - SSD Name - OUT6:OUT4 - OUT3:OUT1 Default 0000000 0 Default 0 111 0 111 The Shutdown Register sets software shutdown mode of IS31FL3196. SSD 0 1 Software Shutdown Enable Software shutdown mode Normal operation Integrated Silicon Solution, Inc. — www.issi.com Rev.A, 03/27/2012 The LED Control Registers store the on or off state of each channel LED. OUTx 0 1 LED State LED off LED on 8 IS31FL3196 Table 5 03h Configuration Register 1 Bit D7:D6 D5:D4 D3 D2 D1 D0 Name - RGB2:1 - AE AGCE AGCM Default 00 00 0 0 0 0 The Configuration Register 1 sets operation mode. RGBx 0 1 RGB Mode Selection PWM Control Mode One Shot Programming Mode AE 0 1 Audio Modulate Enable Disable Enable AGCE 0 1 AGC Function Enable Enable Disable AGCM 0 1 AGC Mode Selection Mode1 (Fast Modulation) Mode2 (Slow Modulation) Table 6 04h AGS 000 001 010 011 100 101 110 111 Audio Gain Selection Gain= 0dB Gain= 3dB Gain= 6dB Gain= 9dB Gain= 12dB Gain= 15dB Gain= 18dB Gain= 21dB Table 7 05h Ramping Mode Register Bit D7:D6 D5:D4 D3:D2 D1:D0 Name - RM(RGB2:1) - HT(RGB2:1) Default 00 00 00 00 The Ramping Mode Register sets the ramping function. Configuration Register 2 RM 0 1 Ramping Mode Enable Disable Enable HT 0 1 Hold Time Selection Breathing Hold on T2 Breathing Hold on T4 Bit D7 D6:D4 D3 D2:D0 Name CM CS - AGS Bit D7:D5 D4 D3 D2:D0 Default 0 000 0 000 Name - BME - CSS Default 000 0 0 000 The Configuration Register 2 stores the intensity control settings for all of the LEDs and the control mode. CM 0 1 Control Mode Master Slave CS 000 001 010 011 100 101 110 111 Current Setting 20mA 15mA 10mA 5mA 40mA 35mA 30mA 25mA Integrated Silicon Solution, Inc. — www.issi.com Rev.A, 03/27/2012 Table 8 06h Breathing Mark Register The Breathing Mark Register sets the breathing mark function (Detail information refers to Page 12). BME 0 1 Breathing Mark Enable Disable Enable CSS 000 001 010 011 100 101 Others Channel Selection OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 Unavailable 9 IS31FL3196 Table 9 07h~0Ch PWM Register(OUT1~OUT6) Bit D7:D0 Name PWM Default 0000 0000 The PWM Registers can modulate RGB light with 256 different items. The value of PWM Registers decide the average output current of OUT1~OUT6. The average output current may be computed using the Formula (1): I OUT I MAX 7 D[n] 2 n 256 n0 (1) Where “n” indicates the bit location in the respective PWM register. For example: D7:D0 = 10110101, IOUT = IMAX (20+22+24+25+27)/256 IMAX is set by Configuration Register2 (04h). 10h Data Update Register The data sent to the PWM Registers and the LED Control Registers will be stored in temporary registers. A write operation of any 8-bit value to the Data Update Register is required to update the registers (01h, 07h~0Ch). Table 10 11h~16h T0 Register (OUT1~OUT6) Bit D7:D6 D5:D4 D3:D0 Name - B A Default 00 00 0000 Double Time T3 =T1 T3 = 2T1 DT 0 1 The T0 Registers set the T0 time in One Shot Programming Mode. T0 = τ×A×2B A = 0~15, B = 0~3 and τ = 260ms (Typ.) For example, the max T0 is 260ms×15×23 = 31.2s If A = 0~4, T1 = T3 = τ×2A, τ = 260ms (Typ.) If A = 5~6, the breathing function disable. If A = 7, T1= T3 = 0.1ms. If B = 1~7, T2 = τ×2B-1, τ = 260ms (Typ.) If B = 0, T2 = 0s. For example, the max T1&T3 is 260ms×24 = 4.16s. The max T2 is 260ms×26 = 16.64s. Table 12 1Dh~22h T4 Register (OUT1~OUT6) Bit D7:D6 D5:D4 D3:D0 Name - B A Default 00 00 0000 The T4 Registers set the T4 time in One Shot Programming Mode. B T4 = τ×A×2 A = 0~15, B = 0~3 and τ = 260ms (Typ.) For example, the max T4 is 260ms×15×23 = 31.2s 26h Time Update Register The data sent to the time registers (11h~16h, 1Ah~1Bh, 1Dh~22h) will be stored in temporary registers. A write operation of any 8-bit data to the Time Update Register is required to update the registers (11h~16h, 1Ah~1Bh, 1Dh~22h). FFh Reset Register Once user writes any 8-bit data to the Reset Register, IS31FL3196 will reset all registers to default value. On initial power-up, the IS31FL3196 registers are reset to their default values for a blank display. Table 11 1Ah~1Bh T1~T3 Register (RGB1~RGB2) Bit D7 D6:D4 D3 D2:D0 Name DT B - A Default 0 000 0 000 The T1~T3 Registers set the T1~T3 time in One Shot Programming Mode. Integrated Silicon Solution, Inc. — www.issi.com Rev.A, 03/27/2012 10 IS31FL3196 FUNCTIONAL BLOCK DIAGRAM Integrated Silicon Solution, Inc. — www.issi.com Rev.A, 03/27/2012 11 IS31FL3196 TYPICAL APPLICATION GENERAL DESCRIPTION SEMIAUTOMATIC BREATHING IS31FL3196 is a 6-channel LED driver with two-dimensional auto breathing and PWM Control mode. It can drive nine LEDs or three groups RGB. By setting the RGBx bits of the Configuration Register1 (03h) to “1” and the RM bit of the Ramping Mode Register (05h) to “1”, the ramping function is enabled. HT is the time select bit. When HT bit is set to “0”, T2 will be held forever, and the LED will remain at the programmed maximum intensity. When HT bit is set to “1”, T3 will continue and T4 will be held, causing the LED to complete one breathing cycle and then remain off. PWM CONTROL By setting the RGBx bits of the Configuration Register1 (03h) to “0”, the IS31FL3196 will operate in PWM Control mode. The PWM Registers (07h~0Ch) can modulate LED brightness of 6 channels with 256 steps. For example, if the data in PWM Register is “0000 0100”, then the PWM is the fourth step. Writing new data continuously to the registers can modulate the brightness of the LEDs to achieve a breathing effect. RGB BREATHING CONTROL WITH AUTO COLOR CHANGING By setting the RGBx bits of the Configuration Register1 (03h) to “1”, the IS31FL3196 will operate in One Shot Programming mode. In this mode each group RGB can be modulated breathing cycle independently by T0~T4. The full cycle is T1 to T4 (Figure 7). Setting different T0~T4 can achieve RGB breathing with auto color changing. The maximum intensity of each RGB can be adjusted independently by the PWM Registers (07h~0Ch). Note, if IS31FL3196 operates in the One Shot Programming mode and then enters into the shutdown mode, an 8-bit data write operation to the Time Update Register is required to restart the LED breathing effect after the IC is re-enabled. Figure 7 Breathing Timing RGB AUTO BREATHING CONTROL WITH COLOR SETTING AUDIO MODULATE DISPLAY MODE WITH AGC FUNCTION In audio modulate display mode the output current can be modulated by the audio input signal. An AGC automatically adjusts the audio input gain to improve the dynamic range of the LED current modulation, thus improving the visual effect. When the input signal is large such that the amplifier output begins to clip, the gain goes down. If the input signal is small, the gain increases, adjusting the output to provide a good dynamic response to the input signal. The AGC can be disabled and the audio gain can be set by programming Configuration Register 1 (03h). BREATHING MARK FUNCTION By setting the BME bit of the Breathing Mark Register (06h) to “1”, the breathing mark function is enabled. The CLK/V_BM pin is used as V_BM. If the BME bit sets to “0”, the breathing mark function disabled. The CLK/V_BM pin is used as CLK. V_BM is an output pin. The breathing mark function is useful as a signal to notify the MCU when to update the color data. At the end of time period T1, V_BM will induce a falling edge and hold logic low, so the new data can be sent by MCU at this time. At the end of T3, V_BM will induce a rising edge and the MCU can send an update command to update all data simultaneously (Figure 8). The marking channel (OUT1~OUT6) is selected by the CSS bits of the Breathing Mark Register (06h). When IS31FL3196 operates as slave, the breathing mark function is unavailable. IS31FL3196 can pre-establish pattern achieving mixing color breathing. There are three groups RGB. Each RGB consists of three channels. Every channel has an 8-bit PWM data register. The color can be set by the PWM data register. For example, there are three PWM data: 20h, 80h, C8h, so the three data will determine a kind of color. After setting the color, T0~T4 time register will be set to control the LED breathing panel. And T0~T4 time should be same for one RGB or the pre-established color will change. Integrated Silicon Solution, Inc. — www.issi.com Rev.A, 03/27/2012 Figure 8 V_BM Signal 12 IS31FL3196 CASCADE FOR SYNCHRONIZATION OF CHIPS SOFTWARE SHUTDOWN Operating in the cascade mode can make two chips synchronize (Figure 2). By setting the CM bit of Configuration Register 2 (04h) to “0”, IS31FL3196 operates as a master. There are two pins (CLK, I_AUD) for synchronization of chips. CLK pin can synchronize the breathing and I_AUD pin can synchronize the audio current. By setting SSD bit of the Shutdown Register (00h) to “0”, the IS31FL3196 will operate in software shutdown mode, wherein they consume only 2μA (typ.) current. When the IS31FL3196 is in software shutdown mode, all current sources are switched off. SHUTDOWN MODE Shutdown mode can either be used as a means of reducing power consumption or generating a flashing display (repeatedly entering and leaving shutdown mode). During shutdown mode all registers retain their data. Integrated Silicon Solution, Inc. — www.issi.com Rev.A, 03/27/2012 HARDWARE SHUTDOWN The chip enters hardware shutdown mode when the SDB pin is pulled low, wherein they consume only 1μA (typ.) current. 13 IS31FL3196 CLASSIFICATION REFLOW PROFILES Profile Feature Pb-Free Assembly Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) 150°C 200°C 60-120 seconds Average ramp-up rate (Tsmax to Tp) 3°C/second max. Liquidous temperature (TL) Time at liquidous (tL) 217°C 60-150 seconds Peak package body temperature (Tp)* Max 260°C Time (tp)** within 5°C of the specified classification temperature (Tc) Max 30 seconds Average ramp-down rate (Tp to Tsmax) 6°C/second max. Time 25°C to peak temperature 8 minutes max. Figure 9 Classification Profile Integrated Silicon Solution, Inc. — www.issi.com Rev.A, 03/27/2012 14 IS31FL3196 PACKAGE INFORMATION QFN-20 Note: All dimensions in millimeters unless otherwise stated. Integrated Silicon Solution, Inc. — www.issi.com Rev.A, 03/27/2012 15