ISSI IS41C16100C

IS41C16100C
IS41LV16100C
1Mx16
16Mb DRAM WITH EDO PAGE MODE
FEBRUARY 2012
FEATURES
DESCRIPTION
• TTL compatible inputs and outputs; tristate I/O
The ISSI IS41C16100C and IS41LV16100C are 1,048,576
x 16-bit high-performance CMOS Dynamic Random Access Memories. These devices offer a cycle access called Extended Data Out (EDO) Page Mode. EDO Page Mode
allows 1,024 random accesses within a single row with
access cycle time as short as 30 ns per 16-bit word. It is
asynchronous, as it does not require a clock signal input
to synchronize commands and I/O.
•
•
Refresh Interval:
— Auto refresh Mode: 1,024 cycles /16 ms
— RAS-Only, CAS-before-RAS (CBR), and Hidden
— Self refresh Mode: 1,024 cycles /128 ms
JEDEC standard pinout
• Single power supply: 5V ± 10% (IS41C16100C)
3.3V ± 10% (IS41LV16100C)
• Byte Write and Byte Read operation via two CAS
• Industrial Temperature Range: -40oC to +85oC
These features make the IS41C/41LV16100C ideally suited
for high-bandwidth graphics, digital signal processing,
high-performance computing systems, and peripheral
applications that run without a clock to synchronize with
the DRAM.
The IS41C/41LV16100C is packaged in a 42-pin 400-mil
SOJ and 400-mil 50/44 pin TSOP (Type II).
KEY TIMING PARAMETERS
Parameter
Max. RAS Access Time (trac)
Max. CAS Access Time (tcac)
Max. Column Address Access Time (taa)
Min. EDO Page Mode Cycle Time (tpc)
Min. Read/Write Cycle Time (trc)
-50
50
14
25
30
85
Unit
ns
ns
ns
ns
ns
Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon
Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C
02/16/2012
1
IS41C16100C
IS41LV16100C
PIN CONFIGURATIONS
50(44)-Pin TSOP (Type II)
42-Pin SOJ
VDD
1
44
GND
VDD
1
42
GND
I/O0
2
43
I/O15
I/O0
2
41
I/O15
I/O1
3
42
I/O14
I/O1
3
40
I/O14
I/O2
4
41
I/O13
I/O3
5
40
I/O12
I/O2
4
39
I/O13
VDD
6
39
GND
I/O3
5
38
I/O12
I/O4
7
38
I/O11
VDD
6
37
GND
I/O5
8
37
I/O10
I/O4
7
36
I/O11
I/O6
9
36
I/O9
I/O5
8
35
I/O10
9
34
I/O9
I/O7
10
35
I/O8
I/O6
NC
11
34
NC
I/O7
10
33
I/O8
NC
11
32
NC
NC
12
33
NC
NC
13
32
LCAS
WE
14
31
UCAS
RAS
15
30
OE
NC
16
29
NC
17
A0
A1
NC
12
31
LCAS
WE
13
30
UCAS
RAS
14
29
OE
A9
NC
15
28
A9
28
A8
NC
16
27
A8
18
27
A7
A0
17
26
A7
19
26
A6
A1
18
25
A6
A2
20
25
A5
A3
21
24
A4
A2
19
24
A5
VDD
22
23
GND
A3
20
23
A4
VDD
21
22
GND
PIN DESCRIPTIONS
A0-A9
I/O0-15
WE
OE
RAS
UCAS
LCAS
Vdd
GND
NC
2
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Upper Column Address Strobe
Lower Column Address Strobe
Power
Ground
No Connection
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
02/16/2012
IS41C16100C
IS41LV16100C
FUNCTIONAL BLOCK DIAGRAM
OE
WE
LCAS
UCAS
CAS
CLOCK
GENERATOR
WE
CONTROL
LOGICS
CAS
WE
OE
CONTROL
LOGIC
OE
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
A0-A9
ADDRESS
BUFFERS
ROW DECODER
REFRESH
COUNTER
MEMORY ARRAY
1,048,576 x 16
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C
02/16/2012
DATA I/O BUFFERS
RAS
CLOCK
GENERATOR
RAS
RAS
I/O0-I/O15
3
IS41C16100C
IS41LV16100C
TRUTH TABLE(5)
Function
Standby
Read: Word
Read: Lower Byte
Read: Upper Byte
Write: Word (Early Write)
Write: Lower Byte (Early Write)
Write: Upper Byte (Early Write)
Read-Write(1,2)
(2)
EDO Page-Mode Read 1st Cycle:
2nd Cycle:
Any Cycle:
EDO Page-Mode Write(1) 1st Cycle:
2nd Cycle:
(1,2)
EDO Page-Mode 1st Cycle:
Read-Write
2nd Cycle:
Hidden Refresh
Read(2) Write(1,3) RAS-Only Refresh
CBR Refresh(4)
RAS LCAS
H
X
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
H→L
L
H→L
L
L→H
L
H→L
L
H→L
L
H→L
L
H→L
L→H→L L
L→H→L L
L
H
H→L
L
UCAS WE
X
X
L
H
H
H
L
H
L
L
H
L
L
L
L
H→L
H→L
H
H→L
H
L→H
H
H→L
L
H→L
L
H→L H→L
H→L H→L
L
H
L
L
H
X
L
H
OE
X
L
L
L
X
X
X
L→H
L
L
L
X
X
L→H
L→H
L
X
X
X
Address tr/tc
X
ROW/COL
ROW/COL
ROW/COL
ROW/COL
ROW/COL
ROW/COL
ROW/COL
ROW/COL
NA/COL
NA/NA
ROW/COL
NA/COL
ROW/COL
NA/COL
ROW/COL
ROW/COL
ROW/NA
X
I/O
High-Z
Dout
Lower Byte, Dout
Upper Byte, High-Z
Lower Byte, High-Z Upper Byte, Dout
Din
Lower Byte, Din
Upper Byte, High-Z
Lower Byte, High-Z Upper Byte, Din
Dout, Din
Dout
Dout
Dout
Din
Din
Dout, Din
Dout, Din
Dout
Dout
High-Z
High-Z
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3. EARLY WRITE only.
4. At least one of the two CAS signals must be active (LCAS or UCAS).
5. Commands valid only after proper initialization.
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
02/16/2012
IS41C16100C
IS41LV16100C
Functional Description
The IS41C/41LV16100C is a CMOS DRAM optimized
for high-speed bandwidth, low power applications. During
READ or WRITE cycles, each bit is uniquely addressed
through the 16 address bits. These are entered ten bits
(A0-A9) at time. The row address is latched by the Row
Address Strobe (RAS). The column address is latched by
the Column Address Strobe (CAS). RAS is used to latch
the first nine bits and CAS is used to latch the latter nine bits.
The IS41C/41LV16100C has two CAS controls, LCAS and
UCAS. The LCAS and UCAS inputs internally generates a
CAS signal functioning in an identical manner to the single
CAS input on the other 1M x 16 DRAMs. The key difference
is that each CAS controls its corresponding I/O tristate logic
(in conjunction with OE and WE and RAS). LCAS controls I/
O0 through I/O7 and UCAS controls I/O8 through I/O15.
The IS41C/41LV16100C CAS function is determined by
the first CAS (LCAS or UCAS) transitioning LOW and the
last transitioning back HIGH. The two CAS controls give
the IS41C16100C and IS41LV16100C both BYTE READ
and BYTE WRITE cycle capabilities.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or aborted
before the minimum tras time has expired. A new cycle
must not be initiated until the minimum precharge time
trp, tcp has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH.The column
address must be held for a minimum time specified by tar.
Data Out becomes valid only when trac, taa, tcac and toea
are all satisfied. As a result, the access time is dependent
on the timing relationships between these parameters.
Write Cycle
A write cycle is initiated by the falling edge of CAS and WE,
whichever occurs last. The input data must be valid at or
before the falling edge of CAS or WE, whichever occurs first.
Auto Refresh Cycle
To retain data, 1,024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory.
1. By clocking each of the 1,024 row addresses (A0 through
A9) with RAS at least once every tref max. Any read, write,
read-modify-write or RAS-only cycle refreshes the addressed
row.
2. Using a CAS-before-RAS refresh cycle. CAS-beforeRAS refresh is activated by the falling edge of RAS, while
holding CAS LOW. In CAS-before-RAS refresh cycle,
an internal 9-bit counter provides the row addresses
and the external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Self Refresh Cycle
The Self Refresh allows the user a dynamic refresh, data
retention mode at the extended refresh period of 128 ms.
i.e., 125 µs per row when using distributed CBR refreshes.
The feature also allows the user the choice of a fully static,
low power data retention mode. The optional Self Refresh
feature is initiated by performing a CBR Refresh cycle and
holding RAS LOW for the specified tRAS.
The Self Refresh mode is terminated by driving RAS HIGH for a minimum time of tRP. This delay allows for the
completion of any internal refresh cycles that may be in
process at the time of the RAS LOW-to-HIGH transition. If
the DRAM controller uses a distributed refresh sequence,
a burst refresh is not required upon exiting Self Refresh.
However, if the DRAM controller utilizes a RAS-only or burst
refresh sequence, all 1,024 rows must be refreshed within
the average internal refresh rate, prior to the resumption
of normal operation. Extended Data Out Page Mode
EDO page mode operation permits all 1,024 columns
within a selected row to be randomly accessed at a high
data rate.
In EDO page mode read cycle, the data-out is held to the
next CAS cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the CAS cycle time becomes shorter. Therefore, in EDO page mode, the timing margin in read cycle
is larger than that of the fast page mode even if the CAS
cycle time becomes shorter.
In EDO page mode, due to the extended data function,
the CAS cycle time can be shorter than in the fast page
mode if the timing margin is the same.
The EDO page mode allows both read and write operations
during one RAS cycle, but the performance is equivalent
to that of the fast page mode in that case.
Power-On
During Power-On, RAS, UCAS, LCAS, and WE must
all track with V dd (HIGH) to avoid current surges,
and allow initialization to continue. An initial pause of
200 µs is required followed by a minimum of eight initialization cycles (any combination of cycles containing a
RAS signal).
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02/16/2012
5
IS41C16100C
IS41LV16100C
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vt
Vdd
Iout
Pd
Ta
Tstg
Parameters
Voltage on Any Pin Relative to GND
5V
3.3V
Supply Voltage
5V
3.3V
Output Current
Power Dissipation
Industrial Operation Temperature
Storage Temperature
Rating
Unit
–1.0 to +7.0
V
–0.5 to +4.6
–1.0 to +7.0
V
–0.5 to +4.6
50
mA
1
W
-40 to +85
°C
–55 to +125 °C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(At Ta = -40°C to +85°C for Industrial grade. Voltages are referenced to GND.)
Symbol
Vdd
Vih
Vil
Iil
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current
Test Condition
5V
3.3V
5V
3.3V
5V
3.3V
Any input 0V ≤ Vin ≤ Vdd
Other inputs not under test = 0V
Iio
Output Leakage Current
Output is disabled (Hi-Z)
0V ≤ Vout ≤ Vdd
Voh
Output High Voltage Level
Vol
Output Low Voltage Level
Min. Typ.
Max.
4.5
5.0
5.5
3.0
3.3
3.6
2.4
— Vdd + 1.0
2.0
— Vdd + 0.3
–1.0 —
0.8
–0.3 —
0.8
–5
5
Unit
V V V µA
–5
5
µA
Ioh = –5.0 mA
Ioh = –2.0 mA
5V
3.3V
2.4
2.4
—
—
V Iol = 4.2 mA
Iol = 2.0 mA
5V
3.3V
—
—
0.4
0.4
V CAPACITANCE(1,2)
Symbol
Cin1
Cin2
Cio
Parameter
Input Capacitance: A0-A9
Input Capacitance: RAS, UCAS, LCAS, WE, OE Data Input/Output Capacitance: I/O0-I/O15
Max.
5
7
7
Unit
pF
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: Ta = 25°C, f = 1 MHz.
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
02/16/2012
IS41C16100C
IS41LV16100C
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
Vdd
Min.
Max.
Unit
Idd1 Standby Current: TTL
RAS, LCAS, UCAS ≥ Vih
5V
3.3V
—
—
2
2
mA
mA
Idd2 Standby Current: CMOS
RAS, LCAS, UCAS ≥ Vdd – 0.2V 5V
3.3V
—
—
1
1
mA
mA
Idd3 Operating Current: Random Read/Write(2,3,4)
Average Power Supply Current
RAS, LCAS, UCAS,
Address Cycling, trc = trc (min.)
5V
3.3V
—
—
90
90
mA
Idd4 Operating Current: EDO Page Mode(2,3,4)
Average Power Supply Current
RAS = Vil, LCAS, UCAS,
Cycling tpc = tpc (min.)
5V
3.3V
—
—
30
30
mA
Idd5 Refresh Current:
RAS-Only(2,3)
Average Power Supply Current
RAS Cycling, LCAS, UCAS ≥ Vih
trc = trc (min.)
5V
3.3V
—
—
60
60
mA
Idd6 Refresh Current: CBR(2,3,5)
Average Power Supply Current
RAS, LCAS, UCAS Cycling
trc = trc (min.)
5V
3.3V
­—
­ —
60
60
mA
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tref refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
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02/16/2012
7
IS41C16100C
IS41LV16100C
AC CHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50 -60
Symbol
Parameter
Min. Max.
Min. Max.
trc
Random READ or WRITE Cycle Time
85 —
110 —
(6, 7)
trac
Access Time from RAS — 50
— 60
(6, 8, 15)
tcac
Access Time from CAS
— 14
— 15
taa
Access Time from Column-Address(6)
— 25
— 30
tras
RAS Pulse Width
50 10K
60 10K
trp
RAS Precharge Time
30 —
40 —
(26)
tcas
CAS Pulse Width 8 10K
10 10K
tcp
CAS Precharge Time(9, 25)
9 —
10 —
tcsh
CAS Hold Time (21)
50 —
60 —
(10, 20)
trcd
RAS to CAS Delay Time
12 37
20 45
tasr
Row-Address Setup Time
0 —
0 —
trah
Row-Address Hold Time
8 —­
10 —
tasc
Column-Address Setup Time(20)
0 —
0 —
(20)
tcah
Column-Address Hold Time 8 —
10 —
tar
Column-Address Hold Time
30 —
40 —
(referenced to RAS)
trad
RAS to Column-Address Delay Time(11)
14 25
15 30
tral
Column-Address to RAS Lead Time
25 —
30 —
trpc
RAS to CAS Precharge Time
5 —
5 —
(27)
trsh
RAS Hold Time 14 —
15 —
trhcp
RAS Hold Time from CAS Precharge
37 —
37 —
tclz
CAS to Output in Low-Z(15, 29)
0 —
0 —
(21)
tcrp
CAS to RAS Precharge Time 5 —
5 —
(19, 28, 29)
tod
Output Disable Time
3 12
3 12
toe/toea Output Enable Time(15, 16)
— 14
— 15
toehc
OE HIGH Hold Time from CAS HIGH
15 —
15 —
toep
OE HIGH Pulse Width
10 —
10 —
toes
OE LOW to CAS HIGH Setup Time
5 —
5 —
trcs
Read Command Setup Time(17, 20)
0 —
0 —
trrh
Read Command Hold Time
0 —
0 —
(referenced to RAS)(12)
trch
Read Command Hold Time
0 —
0 —
(referenced to CAS)(12, 17, 21)
twch
Write Command Hold Time(17, 27)
8 —
10 —
twcr
Write Command Hold Time
40 —
50 —
(referenced to RAS)(17)
8
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
02/16/2012
IS41C16100C
IS41LV16100C
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50 -60 Symbol Parameter
Min. Max.
Min. Max.
(17)
twp
Write Command Pulse Width 8 —
10 —
twpz
WE Pulse Widths to Disable Outputs
10 —
10 —
(17)
trwl
Write Command to RAS Lead Time 13 —
15 —
tcwl
Write Command to CAS Lead Time(17, 21)
8 —
15 —
twcs
Write Command Setup Time(14, 17, 20)
0 —
0 —
tdhr
Data-in Hold Time (referenced to RAS)
39 —
40 —
tach
Column-Address Setup Time to CAS precharge
15 —
15 —
during WRITE cycle
toeh
OE Hold Time from WE during
14 —
15 —
READ-MODIFY-WRITE cycle(18)
tds
tdh
trwc
trwd
tcwd
tawd
tpc
trasp
tcpa
tprwc
tcoh
toff
twhz
tclch
tcsr
tchr
tord
twrp
twrh
tref
tref
tt
Data-In Setup Time(15, 22)
Data-In Hold Time(15, 22)
READ-MODIFY-WRITE Cycle Time
RAS to WE Delay Time during
READ-MODIFY-WRITE Cycle(14)
CAS to WE Delay Time(14, 20)
Column-Address to WE Delay Time(14)
EDO Page Mode READ or WRITE
Cycle Time(24)
RAS Pulse Width in EDO Page Mode
Access Time from CAS Precharge(15)
EDO Page Mode READ-WRITE
Cycle Time(24)
Data Output Hold after CAS LOW
Output Buffer Turn-Off Delay from
CAS or RAS(13,15,19, 29)
Output Disable Delay from WE
Last CAS going LOW to First CAS
returning HIGH(23)
CAS Setup Time (CBR REFRESH)(30, 20)
CAS Hold Time (CBR REFRESH)(30, 21)
OE Setup Time prior to RAS during
HIDDEN REFRESH Cycle
WE Setup Time (CBR Refresh)
WE Hold Time (CBR Refresh)
Auto Refresh Period (1,024 Cycles)
Self Refresh Period (1,024 Cycles)
Transition Time (Rise or Fall)(2, 3)
0
8
110
65
Units
ns
ns
ns
ns
ns
ns
ns ns
—
—
—
—
0
15
155
85
—
—
—
—
ns
ns
ns
ns
26 40 30 —
—
—
40 55 40 —
—
—
ns
ns
ns
50 100K
— 30
56 —
60 100K
— 35
56 —
ns
ns
ns
5
3
5
3
—
15
ns
ns
3 10
10 —
3 15
10 —
ns
ns
5
8
0
5 10 0 ns
ns
ns
5
8
—
—
1
—
—
16
128
50
—
12
—
—
—
5
10
—
—
1
—
—
—
—
—
16
128
50
ns
ns
ms
ms
ns
Note:
The -60 timing parameters are shown for reference only. The -50 speed option supports 50ns and 60ns timing specifications.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C
02/16/2012
9
IS41C16100C
IS41LV16100C
AC TEST CONDITIONS
Output load: Two TTL Loads and 100 pF (Vdd = 5.0V ±10%)
One TTL Load and 50 pF (Vdd = 3.3V ±10%)
Input timing reference levels: Vih = 2.4V, Vil = 0.8V (Vdd = 5.0V ±10%);
Vih = 2.0V, Vil = 0.8V (Vdd = 3.3V ±10%)
Output timing reference levels: Voh = 2.4V, Vol = 0.4V (Vdd = 5V ±10%, 3.3V ±10%)
Notes:
1.An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tref refresh requirement is exceeded.
2.Vih (MIN) and Vil (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between Vih
and Vil (or between Vil and Vih) and assume to be 1 ns for all inputs.
3.In addition to meeting the transition rate specification, all input signals must transit between Vih and Vil (or between Vil and Vih)
in a monotonic manner.
4.If CAS and RAS = Vih, data output is High-Z.
5.If CAS = Vil, data output may contain data from the last valid READ cycle.
6.Measured with a load equivalent to one TTL gate and 50 pF.
7.Assumes that trcd ≤ trcd (MAX). If trcd is greater than the maximum recommended value shown in this table, trac will increase
by the amount that trcd exceeds the value shown.
8.Assumes that trcd ≤ trcd (MAX).
9.If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the
data output buffer, CAS and RAS must be pulsed for tcp.
10.Operation with the trcd (MAX) limit ensures that trac (MAX) can be met. trcd (MAX) is specified as a reference point only; if trcd
is greater than the specified trcd (MAX) limit, access time is controlled exclusively by tcac.
11.Operation within the trad (MAX) limit ensures that trcd (MAX) can be met. trad (MAX) is specified as a reference point only; if trad
is greater than the specified trad (MAX) limit, access time is controlled exclusively by taa.
12.Either trch or trrh must be satisfied for a READ cycle.
13.toff (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to Voh or Vol.
14.twcs, trwd, tawd and tcwd are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If twcs ≤
twcs (MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If trwd ≤
trwd (MIN), tawd ≤ tawd (MIN) and tcwd ≤ tcwd (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read
from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go
back to Vih) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled)
cycle.
15.Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS.
16.During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a
LATE WRITE or READ-MODIFY-WRITE is not possible.
17.Write command is defined as WE going low.
18.LATE WRITE and READ-MODIFY-WRITE cycles must have both tod and toeh met (OE HIGH during WRITE cycle) in order to
ensure that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains
LOW and OE is taken back to LOW after toeh is met.
19.The I/Os are in open during READ cycles once tod or toff occur.
20.The first χCAS edge to transition LOW.
21.The last χCAS edge to transition HIGH.
22.These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles.
23.Last falling χCAS edge to first rising χCAS edge.
24.Last rising χCAS edge to next cycle’s last rising χCAS edge.
25.Last rising χCAS edge to first falling χCAS edge.
26.Each χCAS must meet minimum pulse width.
27.Last χCAS to go LOW.
28.I/Os controlled, regardless UCAS and LCAS.
29.The 3 ns minimum is a parameter guaranteed by design.
30.Enables on-chip refresh and address counters.
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
02/16/2012
IS41C16100C
IS41LV16100C
READ CYCLE
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRSH
tCAS tCLCH
tRCD
tRRH
UCAS/LCAS
tAR
tRAD
tRAH
tASR
ADDRESS
tRAL
tCAH
tASC
Row
Column
Row
tRCS
tRCH
WE
tAA
tRAC
tCAC
tCLC
I/O
tOFF(1)
Open
Open
Valid Data
tOE
tOD
OE
tOES
Undefined
Don’t Care
Note:
1. toff is referenced from rising edge of RAS or CAS, whichever occurs last.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C
02/16/2012
11
IS41C16100C
IS41LV16100C
EARLY WRITE CYCLE (OE = DON'T CARE)
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRSH
tCAS tCLCH
tRCD
UCAS/LCAS
tAR
tRAD
tRAH
tASR
ADDRESS
tRAL
tCAH
tACH
tASC
Row
Column
Row
tCWL
tRWL
tWCR
tWCS
tWCH
tWP
WE
tDHR
tDS
I/O
tDH
Valid Data
Don’t Care
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
02/16/2012
IS41C16100C
IS41LV16100C
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
tRWC
tRAS
tRP
RAS
tCSH
tCRP
tRSH
tCAS tCLCH
tRCD
UCAS/LCAS
tAR
tRAD
tASR
tRAH
tRAL
tCAH
tASC
tACH
ADDRESS
Row
Column
Row
tRWD
tCWL
tRWL
tCWD
tAWD
tRCS
tWP
WE
tAA
tRAC
tCAC
tCLZ
I/O
tDS
Open
Valid DOUT
tOE
tOD
tDH
Valid DIN
Open
tOEH
OE
Undefined
Don’t Care
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C
02/16/2012
13
IS41C16100C
IS41LV16100C
EDO-PAGE-MODE READ CYCLE
tRASP
tRP
RAS
tCSH
tCRP
tCAS,
tCLCH
tRCD
tPC(1)
tCAS,
tCP
tCLCH
tCP
tRSH
tCAS,
tCLCH
tCP
UCAS/LCAS
tAR
tRAD
tASR
ADDRESS
tASC
tCAH tASC
Row
Column
tRAL
tCAH
tCAH tASC
Column
Column
Row
tRAH
tRRH
tRCS
tRCH
WE
tAA
tRAC
tCAC
tCLZ
I/O
tAA
tCPA
tAA
tCPA
tCAC
tCOH
Open
Valid Data
tOE
tOES
tCAC
tCLZ
tOFF
Valid Data
tOEHC
Valid Data
Open
tOE
tOD
tOES
tOD
OE
tOEP
Undefined
Don’t Care
Note:
1. tpc can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the tpc­specifications.
14
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
02/16/2012
IS41C16100C
IS41LV16100C
EDO-PAGE-MODE EARLY-WRITE CYCLE
tRASP
tRHCP
RAS
tCSH
tCRP
tPC
tCAS,
tCLCH
tRCD
tCP
tCAS,
tCLCH
tCP
tRSH
tCAS,
tCLCH
tRP
tCP
UCAS/LCAS
tAR
tACH
tCAH tASC
tRAD
tASR
ADDRESS
tASC
Row
Column
tRAH
tACH
tRAL
tCAH
tACH
tCAH tASC
Column
tCWL
tWCS
Column
tCWL
tWCS
tWCH
tCWL
tWCS
tWCH
tWCH
tWP
tWP
Row
tWP
WE
tWCR
tDHR
tRWL
tDS
tDS
tDH
I/O
Valid Data
tDS
tDH
Valid Data
tDH
Valid Data
OE
Don’t Care
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C
02/16/2012
15
IS41C16100C
IS41LV16100C
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles)
tRASP
tRP
RAS
tCSH
tCRP
tCAS, tCLCH
tRCD
tCP
tPC / tPRWC(1)
tCAS, tCLCH
tRSH
tCAS, tCLCH
tCP
tCP
UCAS/LCAS
tASR
tRAH
ADDRESS
tAR
tRAD
tASC
tCAH
Row
tASC
tCAH
Column
tRWD
tRCS
tRAL
tCAH
tASC
Column
tCWL
tWP
Column
tRWL
tCWL
tWP
tCWL
tWP
tAWD
tCWD
Row
tAWD
tCWD
tAWD
tCWD
WE
tAA
tRAC
tCAC
tCLZ
I/O
Open
tAA
tCPA
tDH
tDS
DOUT
tCAC
tCLZ
DIN
tOE
tDS
DOUT
tOD
tAA
tCPA
tDH
tCAC
tCLZ
DIN
DOUT
tOD
tOE
tDH
tDS
Open
DIN
tOD
tOE
tOEH
OE
Undefined
Don’t Care
Note:
1. tpc can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the tpc specifications.
16
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
02/16/2012
IS41C16100C
IS41LV16100C
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Pseudo READ-MODIFY WRITE)
tRASP
tRP
RAS
tCSH
tPC
tPC
tCRP
tCAS
tRCD
tCAS
tCP
tRSH
tCAS
tCP
tCP
UCAS/LCAS
tASR
tRAH
ADDRESS
tAR
tRAD
tASC
Row
tCAH
tASC
tCAH
Column (A)
tASC
Column (B)
tRCS
tACH
tRAL
tCAH
Column (N)
Row
tRCH
tWCS
tWCH
WE
tRAC
tCAC
I/O
tAA
Open
tCPA
tCAC
tWHZ
tAA
tCOH
Valid Data (A)
tDS
Valid Data (B)
tDH
DIN
Open
tOE
OE
Don’t Care
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C
02/16/2012
17
IS41C16100C
IS41LV16100C
AC WAVEFORMS
READ CYCLE (With WE-Controlled Disable)
RAS
tCSH
tCRP
tRCD
tCP
tCAS
UCAS/LCAS
tAR
tRAD
tASR
ADDRESS
tRAH
tCAH
tASC
Row
tASC
Column
Column
tRCS
tRCH
tWPZ
WE
tAA
tRAC
tCAC
tCLZ
Open
I/O
tRCS
tWHZ
tCLZ
Valid Data
Open
tOE
tOD
OE
Undefined
Don’t Care
RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)
tRC
tRAS
tRP
RAS
tCRP
tRPC
UCAS/LCAS
tASR
ADDRESS
I/O
tRAH
Row
Row
Open
Don’t Care
18
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
02/16/2012
IS41C16100C
IS41LV16100C
CBR REFRESH CYCLE (Addresses; OE = DON'T CARE)
tRP
tRAS
tRP
tRAS
RAS
tCHR
tRPC
tCP
tCHR
tRPC
tCSR
tCSR
UCAS/LCAS
Open
I/O
WE
tWRP
tWRP
tWRH
tWRH
HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW)
tRAS
tRP
tRAS
RAS
tCRP
tRCD
tASR
tRAD
tRAH tASC
tRSH
tCHR
UCAS/LCAS
tAR
ADDRESS
Row
tRAL
tCAH
Column
tAA
tRAC
tOFF(2)
tCAC
tCLZ
I/O
Open
Valid Data
tOE
Open
tOD
tORD
OE
Undefined
Don’t Care
Notes:
1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH.
2. toff is referenced from rising edge of RAS or CAS, whichever occurs last.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C
02/16/2012
19
IS41C16100C
IS41LV16100C
ORDERING INFORMATION : 5V
Industrial Range: -40°C to +85°C
peed (ns)
S
50
Order Part No.
IS41C16100C-50KI
IS41C16100C-50KLI
IS41C16100C-50TI
IS41C16100C-50TLI
Package
400-mil SOJ
400-mil SOJ, Lead-free
400-mil TSOP (Type II)
400-mil TSOP (Type II), Lead-free
ORDERING INFORMATION : 3.3V
Industrial Range: -40°C to +85°C
peed (ns)
S
50
Order Part No.
IS41LV16100C-50KI
IS41LV16100C-50KLI
IS41LV16100C-50TI
IS41LV16100C-50TLI
Package
400-mil SOJ
400-mil SOJ, Lead-free
400-mil TSOP (Type II)
400-mil TSOP (Type II), Lead-free
Note:
The -50 speed option supports 50ns and 60ns timing specifications.
20
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
02/16/2012
IS41C16100C
IS41LV16100C
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C
02/16/2012
21
IS41C16100C
IS41LV16100C
22
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
02/16/2012