ICSI IC41C82052S-50J

IC41C82052S
IC41LV82052S
2M x 8 (16-MBIT) DYNAMIC
RAM
WITH FAST PAGE MODE
FEATURES
DESCRIPTION
• FAST Page Mode access cycle
• TTL compatible inputs and outputs
• Refresh Interval:
Refresh Mode: 4)5-Only,
+)5-before-4)5 (CBR), and Hidden,
2,048 cycles/32 ms
Self refresh Mode 2,048 cycles/128 ms
• JEDEC standard pinout
• Single power supply:
5V±10% or 3.3V ± 10%
• Byte Write and Byte Read operation via
+)5
PRODUCT SERIES OVERVIEW
Part No.
Refresh
Voltage
IC41C82052S
2K
5V ± 10%
IC41LV82052S
2K
3.3V ± 10%
PIN CONFIGURATION
28 Pin SOJ, TSOP-2
The 1+51 82052S Series is a 2,097,152 x 8-bit high-performance CMOS Dynamic Random Access Memory. The Fast
Page Mode allows 2,048 random accesses within a single row
with access cycle time as short as 20 ns per 8-bit word.
These features make the 82052S Series ideally suited for highbandwidth graphics, digital signal processing, high-performance
computing systems, and peripheral applications.
The 82052S Series is packaged in a 28-pin 300mil SOJ and a
28 pin TSOP-2
KEY TIMING PARAMETERS
Parameter
-50
-60
Unit
RAS Access Time (tRAC)
50
60
ns
CAS Access Time (tCAC)
13
15
ns
Column Address Access Time (tAA)
25
30
ns
EDO Page Mode Cycle Time (tPC)
20
25
ns
Read/Write Cycle Time (tRC)
84
104
ns
PIN DESCRIPTIONS
VCC
1
28
GND
I/O0
2
27
I/O7
I/O1
3
26
I/O2
4
I/O3
5
WE
A0-A10
Address Inputs
I/O6
I/O0-7
Data Inputs/Outputs
25
I/O5
WE
Write Enable
24
I/O4
OE
Output Enable
6
23
CAS
RAS
7
22
OE
RAS
Row Address Strobe
NC
8
21
A9
CAS
Column Address Strobe
A10
9
20
A8
Vcc
Power
A0
10
19
A7
GND
Ground
A1
11
18
A6
A2
12
17
A5
NC
No Connection
A3
13
16
A4
VCC
14
15
GND
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
1
IC41C82052S
IC41LV82052S
FUNCTIONAL BLOCK DIAGRAM
OE
WE
CAS
CAS
CONTROL
LOGIC
WE
CONTROL
LOGICS
CAS
WE
OE
CONTROL
LOGIC
OE
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
ROW DECODER
REFRESH
COUNTER
ADDRESS
BUFFERS
A0-A10
MEMORY ARRAY
2,097,152 x 8
DATA I/O BUFFERS
RAS
CLOCK
GENERATOR
RAS
RAS
I/O0-I/O7
TRUTH TABLE
Function
Standby
Read
Write: Word (Early Write)
Read-Write
Hidden Refresh
RAS-Only Refresh
CBR Refresh
Read
Write(1)
RAS
H
L
L
L
L→H→L
L→H→L
L
H→L
CAS
H
L
L
L
L
L
H
L
WE
X
H
L
H→L
H
L
X
X
OE
X
L
X
L→H
L
X
X
X
Address tR /tC I/O
X
High-Z
ROW/COL
DOUT
ROW/COL
DIN
ROW/COL
DOUT, DIN
ROW/COL
DOUT
ROW/COL
DOUT
ROW/NA
High-Z
X
High-Z
Note:
1. EARLY WRITE only.
2
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
IC41C82052S
IC41LV82052S
Functional Description
Refresh Cycle
The IC41C82052S and IC41LV82052S are CMOS DRAMs
optimized for high-speed bandwidth, low power
applications. During READ or WRITE cycles, each bit is
uniquely addressed through the 11 address bits. These
are entered 11 bits (A0-A10) at a time for the 2K refresh
device. The row address is latched by the Row Address
Strobe (RAS). The column address is latched by the
Column Address Strobe (CAS). RAS is used to latch the
first nine bits and CAS is used the latter ten bits.
To retain data, 2,048 refresh cycles are required in each
32 ms period. There are two ways to refresh the memory:
1. By clocking each of the 2,048 row addresses (A0
through A10) with RAS at least once every 32 ms. Any
read, write, read-modify-write or RAS-only cycle refreshes the addressed row.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time specified
by tAR. Data Out becomes valid only when tRAC, tAA, tCAC
and tOEA are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of CAS and WE,
whichever occurs last. The input data must be valid at or
before the falling edge of CAS or WE, whichever occurs
last.
2. Using a CAS-before-RAS refresh cycle. CAS-beforeRAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 11-bit counter provides the row addresses and the external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Self Refresh Cycle
The Self Refresh allows the user a dynamic refresh, data
retention mode at the extended refresh period of 128 ms.
i.e., 62.5 µs per row when using distributed CBR refreshes.
The feature also allows the user the choice of a fully static,
low power data retention mode. The optional Self Refresh
feature is initiated by performing a CBR Refresh cycle and
holding RAS LOW for the specified tRAS.
The Self Refresh mode is terminated by driving RAS HIGH
for a minimum time of t RP . This delay allows for the
completion of any internal refresh cycles that may be in
process at the time of the RAS LOW-to-HIGH transition. If
the DRAM controller uses a distributed refresh sequence,
a burst refresh is not required upon exiting Self Refresh.
However, if the DRAM controller utilizes a RAS-only or
burst refresh sequence, all 2,048 rows must be refreshed
within the average internal refresh rate, prior to the resumption of normal operation.
Power-On
After application of the VCC supply, an initial pause of
200 µs is required followed by a minimum of eight initialization cycles (any combination of cycles containing a
RAS signal).
During power-on, it is recommended that RAS track with
VCC or be held at a valid VIH to avoid current surges.
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
3
IC41C82052S
IC41LV82052S
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Parameters
VT
Voltage on Any Pin Relative to GND
VCC
Supply Voltage
IOUT
PD
TA
TSTG
Output Current
Power Dissipation
Commercial Operation Temperature
Storage Temperature
5V
3.3V
5V
3.3V
Rating
Unit
–1.0 to +7.0
–0.5 to +4.6
–1.0 to +7.0
–0.5 to +4.6
50
1
0 to +70
–55 to +125
V
V
mA
W
°C
°C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol
Parameter
VCC
Supply Voltage
VIH
Input High Voltage
VIL
Input Low Voltage
TA
Commercial Ambient Temperature
5V
3.3V
5V
3.3V
5V
3.3V
Min.
Typ.
Max.
Unit
4.5
3.0
2.4
2.0
–1.0
–0.3
0
5.0
3.3
—
—
—
—
—
5.5
3.6
VCC + 1.0
VCC + 0.3
0.8
0.8
70
V
V
V
°C
CAPACITANCE(1,2)
Symbol
Parameter
CIN1
CIN2
CIO
Input Capacitance: A0-A10
Input Capacitance: RAS, CAS, WE, OE
Data Input/Output Capacitance: I/O0-I/O7
Max.
Unit
5
7
7
pF
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz.
4
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
IC41C82052S
IC41LV82052S
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol
Parameter
Test Condition
IIL
Input Leakage Current
IIO
Speed
Min.
Max.
Unit
Any input 0V < VIN < Vcc
Other inputs not under test = 0V
–5
5
µA
Output Leakage Current
Output is disabled (Hi-Z)
0V < VOUT < Vcc
–5
5
µA
VOH
Output High Voltage Level
IOH = –5.0 mA with VCC=5V
IOH = –2.0 mA with VCC=3.3V
2.4
—
V
VOL
Output Low Voltage Level
IOL = 4.2 mA with VCC=5V
IOL = 2 mA with VCC=3.3V
—
0.4
V
ICC1
Standby Current: TTL
RAS, CAS > VIH
5V
3.3V
—
—
2
0.5
mA
ICC2
Standby Current: CMOS
RAS, CAS > VCC – 0.2V
5V
3.3V
—
—
1
0.5
mA
ICC3
Operating Current:
Random Read/Write(2,3,4)
Average Power Supply Current
RAS, CAS,
Address Cycling, tRC = tRC (min.)
-50
-60
—
—
120
110
mA
ICC4
Operating Current:
Fast Page Mode(2,3,4)
Average Power Supply Current
RAS = VIL, CAS,
tRC = tRC (min.)
-50
-60
—
—
90
80
mA
ICC5
Refresh Current:
RAS-Only(2,3)
Average Power Supply Current
RAS Cycling, CAS > VIH
tRC = tRC (min.)
-50
-60
—
—
120
110
mA
ICC6
Refresh Current:
CBR(2,3,5)
Average Power Supply Current
RAS, CAS Cycling
tRC = tRC (min.)
-50
-60
—
—
120
110
mA
Iccs
Self Refrsh Current
Self Refresh Mode
5V
—
400
µA
3.3V
—
300
µA
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
5
IC41C82052S
IC41LV82052S
AC CHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
Symbol
tRC
tRAC
tCAC
tAA
tRAS
tRP
tCAS
tCP
tCSH
tRCD
tASR
tRAH
tASC
tCAH
tAR
tRAD
tRAL
tRPC
tRSH
tRHCP
tCLZ
tCRP
tOD
tOE
tOED
tOEHC
tOEP
tOES
tRCS
tRRH
tRCH
tWCH
tWCR
tWP
tWPZ
tRWL
tCWL
tWCS
tDHR
6
Parameter
Random READ or WRITE Cycle Time
Access Time from RAS(6, 7)
Access Time from CAS(6, 8, 15)
Access Time from Column-Address(6)
RAS Pulse Width
RAS Precharge Time
CAS Pulse Width(23)
CAS Precharge Time(9)
CAS Hold Time (21)
RAS to CAS Delay Time(10, 20)
Row-Address Setup Time
Row-Address Hold Time
Column-Address Setup Time(20)
Column-Address Hold Time(20)
Column-Address Hold Time
(referenced to RAS)
RAS to Column-Address Delay Time(11)
Column-Address to RAS Lead Time
RAS to CAS Precharge Time
RAS Hold Time
RAS Hold Time from CAS Precharge
CAS to Output in Low-Z(15, 24)
CAS to RAS Precharge Time(21)
Output Disable Time(19, 24)
Output Enable Time(15, 16)
Output Enable Data Delay (Write)
OE HIGH Hold Time from CAS HIGH
OE HIGH Pulse Width
OE LOW to CAS HIGH Setup Time
Read Command Setup Time(17, 20)
Read Command Hold Time
(referenced to RAS)(12)
Read Command Hold Time
(referenced to CAS)(12, 17, 21)
Write Command Hold Time(17)
Write Command Hold Time
(referenced to RAS)(17)
Write Command Pulse Width(17)
WE Pulse Widths to Disable Outputs
Write Command to RAS Lead Time(17)
Write Command to CAS Lead Time(17, 21)
Write Command Setup Time(14, 17, 20)
Data-in Hold Time (referenced to RAS)
-50
Max.
Min.
-60
Max.
84
—
—
—
50
30
8
9
38
12
0
7
0
8
30
—
50
13
25
10K
—
10K
—
—
37
—
—
—
—
—
104
—
—
—
60
40
10
9
40
14
0
10
0
10
40
—
60
15
30
10K
—
10K
—
—
45
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
25
5
8
30
0
5
3
—
12
5
10
5
0
0
25
—
—
—
—
—
—
15
12
—
—
—
—
—
—
12
30
5
10
35
0
5
3
—
15
5
10
5
0
0
30
—
—
—
—
—
—
15
15
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
—
0
—
ns
8
40
—
—
10
50
—
—
ns
ns
8
7
13
8
0
39
—
—
—
—
—
—
10
7
15
10
0
39
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
Min.
Units
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
IC41C82052S
IC41LV82052S
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
Symbol
tACH
Parameter
Min.
tREF
Column-Address Setup Time to CAS
Precharge during WRITE Cycle
OE Hold Time from WE during
READ-MODIFY-WRITE cycle(18)
Data-In Setup Time(15, 22)
Data-In Hold Time(15, 22)
READ-MODIFY-WRITE Cycle Time
RAS to WE Delay Time during
READ-MODIFY-WRITE Cycle(14)
CAS to WE Delay Time(14, 20)
Column-Address to WE Delay Time(14)
EDO Page Mode READ or WRITE
Cycle Time
RAS Pulse Width in EDO Page Mode
Access Time from CAS Precharge(15)
EDO Page Mode READ-WRITE
Cycle Time
Data Output Hold after CAS LOW
Output Buffer Turn-Off Delay from
CAS or RAS(13,15,19, 24)
Output Disable Delay from WE
CAS Setup Time (CBR REFRESH)(20, 25)
CAS Hold Time (CBR REFRESH)( 21, 25)
OE Setup Time prior to RAS during
HIDDEN REFRESH Cycle
Auto Refresh Period
2,048 Cycles
tREF
Self Refresh Period
tT
Transition Time (Rise or Fall)(2, 3)
tOEH
tDS
tDH
tRWC
tRWD
tCWD
tAWD
tPC
tRASP
tCPA
tPRWC
tCOH
tOFF
tWHZ
tCSR
tCHR
tORD
-50
Max.
Min.
-60
Max.
Units
15
—
15
—
ns
8
—
10
—
ns
0
8
108
64
—
—
—
—
0
10
133
77
—
—
—
—
ns
ns
ns
ns
26
39
20
—
—
—
32
47
25
—
—
—
ns
ns
ns
50
—
56
100K
30
—
60
—
68
100K
35
—
ns
ns
ns
5
0
—
12
5
0
—
15
ns
ns
3
5
8
0
10
—
—
—
3
5
10
0
10
—
—
—
ns
ns
ns
ns
—
32
—
32
ms
2,048 Cycles
—
128
—
128
ms
1
50
1
50
ns
AC TEST CONDITIONS
Output load:
Two TTL Loads and 50 pF (Vcc = 5.0V + 10%)
One TTL Load and 50 pF (Vcc = 3.3V + 10%)
Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V + 10%)
VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V + 10%)
Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5.0V + 10%, 3.3V + 10%)
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
7
IC41C82052S
IC41LV82052S
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH
and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH)
in a monotonic manner.
4. If CAS and RAS = VIH, data output is High-Z.
5. If CAS = VIL, data output may contain data from the last valid READ cycle.
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that tRCD < tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase
by the amount that tRCD exceeds the value shown.
8. Assumes that tRCD > tRCD (MAX).
9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the
data output buffer, CAS and RAS must be pulsed for tCP.
10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD
is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.
11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD
is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.
12. Either tRCH or tRRH must be satisfied for a READ cycle.
13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS > tWCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD > tRWD
(MIN), tAWD > tAWD (MIN) and tCWD > tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from
the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back
to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.
15. Output parameter (I/O) is referenced to corresponding CAS input.
16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a
LATE WRITE or READ-MODIFY-WRITE is not possible.
17. Write command is defined as WE going low.
18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW
and OE is taken back to LOW after tOEH is met.
19. The I/Os are in open during READ cycles once tOD or tOFF occur.
20. Determined by falling edge of CAS.
21. Determined by rising edge of CAS.
22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles.
23. CAS must meet minimum pulse width.
24. The 3 ns minimum is a parameter guaranteed by design.
25. Enables on-chip refresh and address counters.
8
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
IC41C82052S
IC41LV82052S
READ CYCLE
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRSH
tCAS tCLCH
tRCD
tRRH
CAS
tAR
tRAD
tASR
ADDRESS
tRAH
tRAL
tCAH
tASC
Row
Column
Row
tRCS
tRCH
WE
tAA
tRAC
tCAC
tCLC
I/O
tOFF(1)
Open
Open
Valid Data
tOE
tOD
OE
tOES
Don’t Care
Note:
1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
9
IC41C82052S
IC41LV82052S
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
tRWC
tRAS
tRP
RAS
tCSH
tCRP
tRSH
tCAS tCLCH
tRCD
CAS
tAR
tRAD
tRAH
tASR
tRAL
tCAH
tASC
tACH
ADDRESS
Row
Column
Row
tRWD
tCWL
tRWL
tCWD
tRCS
tAWD
tWP
WE
tAA
tRAC
tCAC
tCLZ
I/O
tDS
Open
Valid DOUT
tOE
tOD
tDH
Valid DIN
Open
tOEH
OE
Don’t Care
10
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
IC41C82052S
IC41LV82052S
EARLY WRITE CYCLE (OE = DON'T CARE)
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRSH
tCAS tCLCH
tRCD
CAS
tAR
tRAD
tASR
ADDRESS
tRAH
tRAL
tCAH
tACH
tASC
Row
Column
Row
tCWL
tRWL
tWCR
tWCS
tWCH
tWP
WE
tDHR
tDS
I/O
tDH
Valid Data
Don’t Care
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
11
IC41C82052S
IC41LV82052S
FAST PAGE MODE READ CYCLE
tRASP
tRP
RAS
tPRWC
tCAS
tCSH
tCAS
tCRP
tRCD
tRSH
tCAS
tCP
tCRP
tCP
CAS
tAR
tRAH
tRAD
tASC
tASR
ADDRESS
tCPWD
tRAL
tCAH
tCPWD
Row
tCAH
tASC
tAR
Column
tCAH
Column
tASC
Column
tRCS
WE
tAA
tAA
tCAC
tOE
OE
tRAC
tCAC
tOE
tOED
tCLZ
I/O
tAA
tCAC
tOED
tCLZ
OUT
tOE
tOED
tCLZ
OUT
OUT
Don’t Care
12
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
IC41C82052S
IC41LV82052S
FAST PAGE MODE READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
tRASP
tRP
RAS
tPRWC
tCAS
tCSH
tCAS
tCRP
tRCD
tRSH
tCAS
tCP
tCRP
tCP
CAS
tAR
tRAH
tRAD
tASC
tASR
ADDRESS
tCPWD
tRAL
tCAH
tCPWD
Row
tCAH
tAR
Column
tASC
Column
tCWL
tRWD
tAWD
tCWD
tRCS
tCAH
tASC
Column
tCWL
tRWL
tCWL
tAWD
tCWD
tWP
tAWD
tCWD
tWP
tWP
WE
tAA
tAA
tCAC
tAA
tCAC
tOE
tCAC
tOE
tOE
OE
tOEZ
tOED
tRAC
OUT
IN
tOEZ
tOED
tDH
tDH
tDS tCLZ
tCLZ
I/O
tOEZ
tOED
tDS
OUT
IN
tDH
tCLZ
OUT
tDS
IN
Don’t Care
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
13
IC41C82052S
IC41LV82052S
FAST PAGE MODE EARLY WRITE CYCLE
tRASP
tRP
RAS
tCAS
tCRP
tRHCP
tRSH
tCAS
tPC
tCAS
tCSH
tRCD
tCP
tCRP
tCP
CAS
tAR
tRAL
tRAH
tRAD
tASC
tASR
ADDRESS
Row
tCAH
tCAH
tAR
Column
tASC
Column
Column
tCWL
tWCS
tWCH
tCAH
tASC
tCWL
tWCH tWCS
tWCS
tWP
tCWL
tWP
tWCH
tWP
WE
tWCR
OE
tDHR
tDS
I/O
tDH
Valid DIN
tDS
tDH
Valid DIN
tDS
tDH
Valid DIN
Don’t Care
14
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
IC41C82052S
IC41LV82052S
AC WAVEFORMS
4)5
4)5-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)
tRC
tRAS
tRP
RAS
tCRP
tRPC
CAS
tASR
ADDRESS
I/O
tRAH
Row
Row
Open
Don’t Care
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
15
IC41C82052S
IC41LV82052S
+*4 REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)
tRP
tRAS
tRP
tRAS
RAS
tRPC
tCP
tCHR
tCHR
tRPC
tCSR
tCSR
CAS
Open
I/O
Don’t Care
HIDDEN REFRESH CYCLE (WE = HIGH; OE = LOW)
tRAS
tRP
tRAS
RAS
tCRP
tRCD
tASR
tRAD
tRAH tASC
tRSH
tCHR
CAS
tAR
ADDRESS
Row
tRAL
tCAH
Column
tAA
tRAC
tOFF(2)
tCAC
tCLZ
I/O
Open
Valid Data
tOE
Open
tOD
tORD
OE
Don’t Care
16
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
IC41C82052S
IC41LV82052S
SELF REFRESH CYCLE (Addresses : WE and OE = DON'T CARE)
tRP
tRASS
tRPS
VIH
RAS V
IL
tCHD
tRPC
tCP
tRPC
tCP
tCSR
VIH
CAS V
IL
VOH
DQ V
OL
Open
TIMING PARAMETERS
Symbol
tCHD
tCP
tCSR
tRASS
tRP
tRPS
tRPC
-50
Min. Max.
8
9
5
50
30
84
5
-60
Min. Max.
—
—
—
—
—
—
—
10
9
5
50
40
104
5
—
—
—
—
—
—
—
Units
ns
ns
ns
µs
ns
ns
ns
ORDERING INFORMATION
Commercial Range: 0°C to 70°C
Voltage: 5V
Speed (ns)
50
50
60
60
Order Part No.
Refresh
Package
IC41C82052S-50J
IC41C82052S-50T
IC41C82052S-60J
IC41C82052S-60T
2K
2K
2K
2K
300mil SOJ
400mil TSOP-2
300mil SOJ
400mil TSOP-2
Refresh
Package
2K
2K
2K
2K
300mil SOJ
400mil TSOP-2
300mil SOJ
400mil TSOP-2
Voltage: 3.3V
Speed (ns)
50
50
60
60
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
Order Part No.
IC41LV82052S-50J
IC41LV82052S-50T
IC41LV82052S-60J
IC41LV82052S-60T
17
IC41C82052S
IC41LV82052S
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
18
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001