IS64WV3216BLL IS61WV3216BLL 32K x 16 HIGH-SPEED CMOS STATIC RAM JULY 2009 FEATURES • • • • • • • • High-speed access time: 12 ns: 3.3V + 10% 15 ns: 2.5V-3.6V CMOS low power operation: 50 mW (typical) operating 25 µW (typical) standby TTL compatible interface levels Fully static operation: no clock or refresh required Three state outputs Data control for upper and lower bytes Automotive Temperature Available Lead-free available DESCRIPTION The ISSI IS61/64WV3216BLL is a high-speed, 524,288-bit static RAM organized as 32,768 words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 12ns (3.3V + 10%) and 15ns (2.5V-3.6V) with low power consumption. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61/64WV3216BLL is packaged in the JEDEC standard 44-pin TSOP-II, and 48-pin mini BGA (6mm x 8mm). FUNCTIONAL BLOCK DIAGRAM A0-A14 DECODER 32Kx16 MEMORYARRAY I/O DATA CIRCUIT COLUMNI/O VDD GND I/O0-I/O7 LowerByte I/O8-I/O15 UpperByte CE OE WE UB LB CONTROL CIRCUIT Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 07/22/09 1 IS64WV3216BLL IS61WV3216BLL PIN CONFIGURATIONS 44-Pin TSOP-II 48-Pin mini BGA (6mm x 8mm) 1 2 3 4 5 6 A LB OE A0 A1 A2 NC B I/O8 UB A3 A4 CE I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D GND I/O11 NC A7 I/O3 VDD E VDD I/O12 NC NC I/O4 GND F I/O14 I/O13 A14 NC I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H NC A8 A9 A10 A11 NC NC A14 A13 A12 A11 CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A10 A9 A8 A7 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A0 A1 A2 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A3 A4 A5 A6 NC PIN DESCRIPTIONS A0-A14 I/O0-I/O15 CE OE WE LB UB NC Vdd GND 2 Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 07/22/09 IS64WV3216BLL IS61WV3216BLL TRUTH TABLE I/O PIN Mode WE CE OE LB UB I/O0-I/O7 I/O8-I/O15 Not Selected X H X X X High-Z High-Z Output Disabled H L H X X High-Z High-Z X L X H H High-Z High-Z Read H L L L H Dout High-Z H L L H L High-Z Dout H L L L LDoutDout Write L L X L H Din High-Z L L X H L High-Z Din L L X L LDinDin Vdd Current Isb1, Isb2 Icc Icc Icc ABSOLUTE MAXIMUM RATINGS(1) Symbol Vterm Tstg Pt Vdd Parameter Terminal Voltage with Respect to GND Storage Temperature Power Dissipation Vdd Related to GND Value –0.5 to Vdd+0.5 –65 to +150 1.5 -0.2 to +3.9 Unit V °C W V Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE (Vdd) Range Commercial Industrial Automotive Ambient Temperature 0°C to +70°C –40°C to +85°C –40°C to +125°C Vdd (15 ns) 2.5V-3.6V 2.5V-3.6V 2.5V-3.6V Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 07/22/09 Vdd (12 ns) 3.3V + 10% 3.3V + 10% 3.3V + 10% 3 IS64WV3216BLL IS61WV3216BLL DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 2.5V-3.6V Symbol Voh Vol Vih Vil Ili Ilo Note: 1. Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage Test Conditions Vdd = Min., Ioh = –1.0 mA Vdd = Min., Iol = 1.0 mA GND ≤ Vin ≤ Vdd GND ≤ Vout ≤ Vdd, Outputs Disabled Min. 2.3 — 2.0 –0.3 –2 –2 Max. — 0.4 Vdd + 0.3 0.8 2 2 Unit V V V V µA µA Max. — 0.4 Vdd + 0.3 0.8 2 2 Unit V V V V µA µA Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width 2.0 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width 2.0 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 3.3V + 10% Symbol Voh Vol Vih Vil Ili Ilo Note: 1. 4 Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage Test Conditions Vdd = Min., Ioh = –4.0 mA Vdd = Min., Iol = 8.0 mA GND ≤ Vin ≤ Vdd GND ≤ Vout ≤ Vdd, Outputs Disabled Min. 2.4 — 2 –0.3 –2 –2 Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width 2.0 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width 2.0 ns). Not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 07/22/09 IS64WV3216BLL IS61WV3216BLL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Test ConditionsOptions Icc Vdd Dynamic Operating Vdd = Max., c om. Supply Current Iout = 0 mA, f = fmax ind. auto typ.(2) Icc1 Operating Supply Vdd = Max., com. Current Iout = 0mA, f = 0ind. auto Isb2 CMOS Standby Vdd = Max., com. Current (CMOS Inputs) CE ≥ Vdd – 0.2V, ind. Vin ≥ Vdd – 0.2V, or auto Vin ≤ 0.2V, f = 0typ.(2) -12 ns -15 ns Min. Max. Min. Max. — 35 — 30 — 45 — 40 — 60 — 50 — 20 — 20 — 5 — 5 — 5 — 5 — 5 — 5 — 20 — 20 — 50 — 50 — 75 — 75 — 6 — 6 Unit mA mA uA Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at Vdd=2.5V, Ta=25oC. Not 100% tested. CAPACITANCE(1) Symbol Cin Cout Parameter Input Capacitance Input/Output Capacitance Conditions Vin = 0V Vout = 0V Max. 6 8 Unit pF pF Note: 1. Tested initially and after any design or process changes that may affect these parameters. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 07/22/09 5 IS64WV3216BLL IS61WV3216BLL AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level (VRef) Output Load Unit (2.5V-3.6V) 0V to Vdd V 1.5ns Vdd/2 See Figures 1a and 1b Unit (3.3V + 10%) 0V to Vdd V 1.5ns Vdd/2 + 0.05 See Figures 1a and 1b AC TEST LOADS 319 Ω Zo=50Ω VRef OUTPUT 30pF Including jig and scope Figure 1a. 6 2.5V 50Ω OUTPUT 5 pF Including jig and scope 353 Ω Figure 1b. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 07/22/09 IS64WV3216BLL IS61WV3216BLL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter trc Read Cycle Time taa Address Access Time toha Output Hold Time tace CE Access Time tdoe OE Access Time (2) thzoe OE to High-Z Output tlzoe(2) OE to Low-Z Output thzce(2 CE to High-Z Output (2) tlzce CE to Low-Z Output tba LB, UB Access Time thzb LB, UB to High-Z Output tlzb LB, UB to Low-Z Output -12 ns Min. Max. 12 — — 12 3 — — 12 — 6 — 6 0 — 0 6 3 — — 6 0 6 0 — -15 ns Min. Max. Unit 15 — ns — 15 ns 3 — ns — 15 ns — 7 ns 0 6 ns 0 — ns 0 6 ns 3 — ns — 7 ns 0 6 ns 0 — ns Notes: 1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0V to Vdd V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 07/22/09 7 IS64WV3216BLL IS61WV3216BLL AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CS = OE = Vil, UB or LB = Vil) tRC ADDRESS tAA tOHA tOHA DOUT DATA VALID PREVIOUS DATA VALID READ CYCLE NO. 2(1,3) tRC ADDRESS tAA tOHA OE tHZOE tDOE tLZOE CE tACE tHZCE tBA tHZB tLZCE LB, UB DOUT HIGH-Z tLZB DATA VALID Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = Vil. 3. Address is valid prior to or coincident with CE LOW transition. 8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 07/22/09 IS64WV3216BLL IS61WV3216BLL WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) Symbol Parameter twc Write Cycle Time tsce CE to Write End taw Address Setup Time to Write End tha Address Hold from Write End tsa Address Setup Time tpwb LB, UB Valid to End of Write tpwe1 WE Pulse Width (OE = HIGH) tpwe2 WE Pulse Width (OE = LOW) tsd Data Setup to Write End thd Data Hold from Write End thzwe(3) WE LOW to High-Z Output (3) tlzwe WE HIGH to Low-Z Output -12 ns Min. Max. 12 — 9 — 9 — 0 0 9 9 11 9 0 — 3 — — — — — — — 6 — -15 ns Min. Max. 15 — 10 — 10 — 0 0 10 10 12 9 0 — 3 — — — — — — — 7 — Unit ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Test conditions for IS61WV3216BLL assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input pulse levels of 0V to Vdd V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 07/22/09 9 IS64WV3216BLL IS61WV3216BLL WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW) t WC VALID ADDRESS ADDRESS t SA t SCE t HA CE t AW t PWE1 t PWE2 WE t PBW UB, LB t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID UB_CEWR1.eps 10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 07/22/09 IS64WV3216BLL IS61WV3216BLL WRITE CYCLE NO. 2(1) (WE Controlled, OE = HIGH during Write Cycle) t WC ADDRESS VALID ADDRESS t HA OE CE LOW t AW t PWE1 WE t SA t PBW UB, LB t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN UB_CEWR2.eps WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) t WC ADDRESS VALID ADDRESS OE LOW CE LOW t HA t AW t PWE2 WE t SA t PBW UB, LB t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID UB_CEWR3.eps Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 07/22/09 11 IS64WV3216BLL IS61WV3216BLL WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3) t WC ADDRESS t WC ADDRESS 1 ADDRESS 2 OE t SA CE LOW t HA t SA WE UB, LB t HA t PBW t PBW WORD 1 WORD 2 t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t HD t SD DIN DATAIN VALID t HD t SD DATAIN VALID UB_CEWR4.eps Notes: 1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t sa, t ha, t sd, and t hd timing is referenced to the rising or falling edge of the signal that terminates the Write. 2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state. 3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function. 12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 07/22/09 IS64WV3216BLL IS61WV3216BLL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Test Condition Operations Vdr Vdd for Data Retention See Data Retention Waveform Idr Data Retention Current Vdd = 1.8V, CE ≥ Vdd – 0.2V com. ind. auto tsdr Data Retention Setup Time See Data Retention Waveform trdr Recovery Time See Data Retention Waveform Note: Min. 1.8 — — — 0 trc Typ.(1) — 6 6 6 — — Max. 3.6 20 50 75 — — Unit V µA ns ns 1. Typical values are measured at Vdd = 2.5V, Ta = 25oC. Not 100% tested. DATA RETENTION WAVEFORM (CE Controlled) tSDR DataRetentionMode tRDR VDD 1.65V 1.4V VDR CE GND CE ≥ VDD -0.2V Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 07/22/09 13 IS64WV3216BLL IS61WV3216BLL ORDERING INFORMATION Industrial Temperature Range: –40°C to +85°C Speed (ns) 12 12 12 12 Order Part No. IS61WV3216BLL-12TI IS61WV3216BLL-12TLI IS61WV3216BLL-12BI IS61WV3216BLL-12BLI Package Plastic TSOP Plastic TSOP, Lead-free mini BGA (6mm x 8mm) mini BGA (6mm x 8mm), Lead-free Temperature Range (A3): –40°C to +125°C Speed (ns) 15 (12*) 15 (12*) 15 (12*) 15 (12*) 15 (12*) Order Part No. IS64WV3216BLL-15TA3 IS64WV3216BLL-15TLA3 IS64WV3216BLL-15CTLA3 IS64WV3216BLL-15BA3 IS64WV3216BLL-15BLA3 Package Plastic TSOP Plastic TSOP, Lead-free Plastic TSOP, Lead-free, Copper Lead-frame mini BGA (6mm x 8mm) mini BGA (6mm x 8mm), Lead-free Note: 1. Speed = 12ns for Vdd = 3.3V + 10%. Speed = 15ns for Vdd = 2.5V- 3.6V. 14 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 07/22/09 IS64WV3216BLL IS61WV3216BLL NOTE : 08/12/2008 1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MO-207 Package Outline Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 07/22/09 15 IS64WV3216BLL IS61WV3216BLL NOTE : 1. CONTROLLING DIMENSION : MM 06/04/2008 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. 2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION. Package Outline Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 07/22/09 16