IS62WV1288DALL/DBLL IS65WV1288DALL/DBLL 128K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FEATURES • High-speed access time: 35ns, 45ns, 55ns • CMOS low power operation: 12 mW (typical) operating 4 µW (typical) CMOS standby • TTL compatible interface levels 1.65V--2.2V Vdd (62WV1288DALL) 2.3V--3.6V Vdd (62WV1288DBLL) DESCRIPTION The ISSI IS62/65WV1288DALL and IS62/65WV1288DBLL are high-speed, 1M bit static RAMs organized as 128K words by 8 bits. It is fabricated using ISSI's highperformance CMOS technology.This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CS1 is HIGH (deselected) or when CS2 is low (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. • Single power supply: DECEMBER 2010 • Fully static operation: no clock or refresh required • Three state outputs • Industrial and automotive temperature support Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS62/65WV1288DALL and IS62/65WV1288DBLL are packaged in the JEDEC standard 32-pin TSOP (TYPEI), sTSOP (TYPEI), SOP, and 36-pin mini BGA. • Lead-free available FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 128K x 8 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VDD GND I/O0-I/O7 CS2 CS1 OE CONTROL CIRCUIT WE Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com Rev. B 12/01/2010 1 IS62WV1288DALL/DBLL IS65WV1288DALL/DBLL PIN CONFIGURATION 36-pin mini BGA (B) (6mm x 8mm) 1 2 3 4 5 A0 A1 CS2 A3 A6 A8 B I/O4 A2 WE A4 A7 I/O0 C I/O5 NC A5 D GND VDD E VDD GND F I/O6 G I/O7 H A9 A0-A16 CS1 CS2 OE WE I/O0-I/O7 NC Vdd GND 2 6 A I/O1 I/O2 NC NC OE CS1 A16 A15 I/O3 A10 A11 A12 A13 A14 PIN DESCRIPTIONS Address Inputs Chip Enable 1 Input Chip Enable 2 Input Output Enable Input Write Enable Input Input/Output No Connection Power Ground 32-pin TSOP (TYPE I) (T), 32-pin sTSOP (TYPE I) (H) A11 A9 A8 A13 WE CS2 A15 VDD NC A16 A14 A12 A7 A6 A5 A4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 OE A10 CS1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 32-pin SOP (Q) NC 1 32 VDD A16 2 31 A15 A14 3 30 CS2 A12 4 29 WE A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 OE A2 10 23 A10 A1 11 22 CS1 A0 12 21 I/O7 I/O0 13 20 I/O6 I/O1 14 19 I/O5 I/O2 15 18 I/O4 GND 16 17 I/O3 Integrated Silicon Solution, Inc. — www.issi.com Rev. B 12/01/2010 IS62WV1288DALL/DBLL IS65WV1288DALL/DBLL TRUTH TABLE Mode Not Selected (Power-down) Output Disabled Read Write WE X X H H L CS1 H X L L L CS2 X L H H H OE X X H L X I/O Operation Vdd Current High-Z Isb1, Isb2 High-Z Isb1, Isb2 High-Z Icc Dout Icc Din Icc ABSOLUTE MAXIMUM RATINGS(1) Symbol Vterm Vdd Tstg Pt Parameter Terminal Voltage with Respect to GND Vdd Relates to GND Storage Temperature Power Dissipation Value –0.5 to Vdd + 0.5 –0.3 to 4.0 –65 to +150 1.0 Unit V V °C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1,2) Symbol Cin CI/O Parameter Input Capacitance Input/Output Capacitance Conditions Vin = 0V Vout = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V. Integrated Silicon Solution, Inc. — www.issi.com Rev. B 12/01/2010 3 IS62WV1288DALL/DBLL IS65WV1288DALL/DBLL AC TEST CONDITIONS Parameter Unit Unit (2.3V-3.6V) (3.3V + 5%) Input Pulse Level 0.4V to Vdd - 0.3V 0.4V to Vdd - 0.3V Input Rise and Fall Times 1V/ ns 1V/ ns Input and Output Timing VDD /2 VDD + 0.05 and Reference Level (VRef) 2 Output Load See Figures 1 and 2 See Figures 1 and 2 R1 ( Ω ) 317 317 R2 ( Ω ) 351 351 Vtm (V) 3.3V 3.3V Unit (1.65V-2.2V) 0.4V to Vdd - 0.3V 1V/ ns 0.9V See Figures 1 and 2 13500 10800 1.8V AC TEST LOADS R1 R1 VTM VTM OUTPUT OUTPUT 30 pF Including jig and scope Figure 1. 4 R2 5 pF Including jig and scope R2 Figure 2. Integrated Silicon Solution, Inc. — www.issi.com Rev. B 12/01/2010 IS62WV1288DALL/DBLL IS65WV1288DALL/DBLL DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 3.3V + 5% Symbol Voh Vol Vih Vil Ili Ilo Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage Test Conditions Vdd = Min., Ioh = –1 mA Vdd = Min., Iol = 2.1 mA GND ≤ Vin ≤ Vdd GND ≤ Vout ≤ Vdd, Outputs Disabled Min. 2.4 — 2 –0.3 –1 –1 Max. — 0.4 Vdd + 0.3 0.8 1 1 Unit V V V V µA µA Max. — 0.4 Vdd + 0.3 0.8 1 1 Unit V V V V µA µA Note: 1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 2.3V-3.6V Symbol Voh Vol Vih Vil Ili Ilo Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage Test Conditions Vdd = Min., Ioh = –1.0 mA Vdd = Min., Iol = 2.1 mA GND ≤ Vin ≤ Vdd GND ≤ Vout ≤ Vdd, Outputs Disabled Min. 1.8 — 2.0 –0.3 –1 –1 Note: 1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 1.65V-2.2V Symbol Voh Vol Vih Vil(1) Ili Ilo Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage Test Conditions Vdd Ioh = -0.1 mA 1.65-2.2V Iol = 0.1 mA 1.65-2.2V 1.65-2.2V 1.65-2.2V GND ≤ Vin ≤ Vdd GND ≤ Vout ≤ Vdd, Outputs Disabled Min. 1.4 — 1.4 –0.2 –1 –1 Max. — 0.2 Vdd + 0.2 0.4 1 1 Unit V V V V µA µA Note: 1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com Rev. B 12/01/2010 5 IS62WV1288DALL/DBLL IS65WV1288DALL/DBLL OPERATING RANGE (Vdd) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C Automotive –40°C to +125°C Vdd 1.65V-2.2V 1.65V-2.2V 1.65V-2.2V Speed 45ns 55ns 55ns Vdd (45 ns) 2.3V-3.6V 2.3V-3.6V Vdd (35 ns) 3.3V+5% 3.3V+5% OPERATING RANGE (Vdd) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C OPERATING RANGE (Vdd) Range Ambient Temperature Automotive –40°C to +125°C Vdd (45 ns) 2.3V-3.6V POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -35 Symbol Parameter Test Conditions Min. Max. Icc Vdd Dynamic Operating Vdd = Max., Com. — 8 Supply Current Iout = 0 mA, f = fmax Ind. — 12 CS1 = Vil Auto. — 15 Vin ≥ Vdd – 0.3V, or typ.(2) 4 Vin ≤ 0.4V Icc1 Operating Vdd = Max., Com. — 2.5 Supply Current Iout = 0 mA, f = 0 Ind. — 2.5 Auto. — 3 CS1 = Vil Vin ≥ Vdd – 0.3V, or Vin ≤ 0.4V Isb2 CMOS Standby Vdd = Max., Com. — 2 Current (CMOS Inputs) CS1 ≥ Vdd – 0.2V, Ind. — 4 Vin ≥ Vdd – 0.2V, or Auto. — 18 Vin ≤ 0.2V, f = 0 typ.(2) 0.6 -45 Min. Max. — 6 — 8 — 12 — 2.5 — 2.5 — 3 — — — 2 4 18 -55 Min. Max. — 5 — 7 — 12 — 2.5 — 2.5 — 3 — — — 2 4 18 Unit mA mA µA Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested. 6 Integrated Silicon Solution, Inc. — www.issi.com Rev. B 12/01/2010 IS62WV1288DALL/DBLL IS65WV1288DALL/DBLL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) 35 ns 45 ns 55 ns Symbol Parameter Min. Max. Min. Max. Min. Max. Unit trc taa toha tacs1/tacs2 tdoe thzoe(2) tlzoe(2) thzcs1/thzcs2(2) tlzcs1/tlzcs2(2) Read Cycle Time 35 — 45 — 55 — ns Address Access Time — 35 — 45 — 55 ns Output Hold Time 10 — 10 — 10 — ns CS1/CS2 Access Time — 35 — 45 — 55 ns OE Access Time — 10 — 20 — 25 ns OE to High-Z Output — 10 — 15 — 20 ns OE to Low-Z Output 3 — 5 — 5 — ns CS1/CS2 to High-Z Output 0 10 0 15 0 20 ns CS1/CS2 to Low-Z Output 5 — 10 — 10 — ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to Vdd-0.2V/Vdd-0.3V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com Rev. B 12/01/2010 7 IS62WV1288DALL/DBLL IS65WV1288DALL/DBLL AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = Vil, CS2 = WE = Vih) tRC ADDRESS tAA tOHA tOHA DOUT DATA VALID PREVIOUS DATA VALID AC WAVEFORMS READ CYCLE NO. 2(1,3) (CS1, CS2, OE Controlled) tRC ADDRESS tAA tOHA OE tHZOE tDOE CS1 tLZOE tACS1/tACS2 CS2 DOUT tLZCS1/ tLZCS2 tHZCS HIGH-Z DATA VALID Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CS1= Vil. CS2=WE=Vih. 3. Address is valid prior to or coincident with CS1 LOW and CS2 HIGH transition. 8 Integrated Silicon Solution, Inc. — www.issi.com Rev. B 12/01/2010 IS62WV1288DALL/DBLL IS65WV1288DALL/DBLL WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) 35ns 45ns 55 ns Symbol Parameter Min. Max. Min.Max. Min. Max. Unit twc Write Cycle Time 35 — 45 — 55 — ns tscs1/tscs2 CS1/CS2 to Write End 25 — 35 — 45 — ns taw Address Setup Time to Write End 25 — 35 — 45 — ns tha Address Hold from Write End 0 — 0 — 0 — ns tsa Address Setup Time 0 — 0 — 0 — ns tpwe WE Pulse Width 25 — 35 — 40 — ns tsd Data Setup to Write End 20 — 20 — 25 — ns thd Data Hold from Write End 0 — 0 — 0 — ns (3) thzwe WE LOW to High-Z Output — 10 — 20 — 20 ns (3) tlzwe WE HIGH to Low-Z Output 3 — 5 — 5 — ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4V to Vdd-0.2V/Vdd-0.3V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC WAVEFORMS WRITE CYCLE NO. 1 (CS1/CS2 Controlled, OE = HIGH or LOW) tWC ADDRESS tHA tSCS1 CS1 tSCS2 CS2 tAW tPWE WE tSA DOUT tHZWE DATA UNDEFINED tLZWE HIGH-Z tSD DIN Integrated Silicon Solution, Inc. — www.issi.com Rev. B 12/01/2010 tHD DATA-IN VALID 9 IS62WV1288DALL/DBLL IS65WV1288DALL/DBLL AC WAVEFORMS WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle) tWC ADDRESS OE tHA tSCS1 CS1 tSCS2 CS2 tAW tPWE WE tSA DOUT tHZWE tLZWE HIGH-Z DATA UNDEFINED tSD DIN tHD DATA-IN VALID WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) tWC ADDRESS OE tHA tSCS1 CS1 tSCS2 CS2 tAW tPWE WE tSA DOUT DATA UNDEFINED tHZWE tLZWE HIGH-Z tSD DIN 10 tHD DATA-IN VALID Integrated Silicon Solution, Inc. — www.issi.com Rev. B 12/01/2010 IS62WV1288DALL/DBLL IS65WV1288DALL/DBLL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Test Condition Vdr Vdd for Data Retention See Data Retention Waveform Idr Data Retention Current Vdd = 1.2V, CS1 ≥ Vdd – 0.2V Com. Ind. Auto. tsdr Data Retention Setup Time See Data Retention Waveform trdr Recovery Time See Data Retention Waveform o Note: 1. Typical values are measured at Vdd = 3.0V, Ta = 25 C and not 100% tested. Min. typ.(1) 1.2 — 0.5 0 trc Max. Unit 3.6 V 2 µA 4 18 — ns — ns DATA RETENTION WAVEFORM (CS1 Controlled) Data Retention Mode tSDR tRDR VDD VDR CS1 ≥ VDD - 0.2V CS1 GND DATA RETENTION WAVEFORM (CS2 Controlled) Data Retention Mode VDD CS2 tSDR tRDR VDR CS2 ≤ 0.2V GND Integrated Silicon Solution, Inc. — www.issi.com Rev. B 12/01/2010 11 IS62WV1288DALL/DBLL IS65WV1288DALL/DBLL ORDERING INFORMATION IS62WV1288DALL (1.65V - 2.2V) Industrial Range: –40°C to +85°C Speed (ns) 55 Order Part No. IS62WV1288DALL-55TI IS62WV1288DALL-55TLI IS62WV1288DALL-55HI IS62WV1288DALL-55HLI IS62WV1288DALL-55BI IS62WV1288DALL-55BLI Package TSOP-I TSOP-I, Lead-free sTSOP-I sTSOP-I, Lead-free mini BGA (6mm x 8mm) mini BGA (6mm x 8mm), Lead-free ORDERING INFORMATION IS62WV1288DBLL (2.3V - 3.6V) Industrial Range: –40°C to +85°C1 Speed (ns) 45 Order Part No. Package IS62WV1288DBLL-45TI TSOP-I IS62WV1288DBLL-45TLI TSOP-I, Lead-free IS62WV1288DBLL-45HI sTSOP-I IS62WV1288DBLL-45HLI sTSOP-I, Lead-free IS62WV1288DBLL-45QI SOP IS62WV1288DBLL-45QLI SOP, Lead-free IS62WV1288DBLL-45BI mini BGA (6mm x 8mm) IS62WV1288DBLL-45BLI mini BGA (6mm x 8mm), Lead-free Automotive Range: –40°C to +125°C Speed (ns) 45 Order Part No. IS65WV1288DBLL-45TLA3 IS65WV1288DBLL-45HLA3 IS65WV1288DBLL-45QLA3 Package TSOP-I, Lead-free sTSOP-I, Lead-free SOP, Lead-free Notes: 1. Speed = 35ns for temperature range of 0oC to +70oC or for Vdd = 3.3V ± 5%. 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. B 12/01/2010 IS62WV1288DALL/DBLL IS65WV1288DALL/DBLL Integrated Silicon Solution, Inc. — www.issi.com Rev. B 12/01/2010 13 IS62WV1288DALL/DBLL IS65WV1288DALL/DBLL 14 Integrated Silicon Solution, Inc. — www.issi.com Rev. B 12/01/2010 IS62WV1288DALL/DBLL IS65WV1288DALL/DBLL Integrated Silicon Solution, Inc. — www.issi.com Rev. B 12/01/2010 15 IS62WV1288DALL/DBLL IS65WV1288DALL/DBLL NOTE : 08/12/2008 1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MO-207 Package Outline 16 Integrated Silicon Solution, Inc. — www.issi.com Rev. B 12/01/2010