KERSEMI IRFU3412

IRFR3412
IRFU3412
Applications
Switch Mode Power Supply (SMPS)
l Motor Drive
l Bridge Converters
l All Zero Voltage Switching
Benefits
l Low Gate Charge Qg results in Simple
Drive Requirement
l Improved Gate, Avalanche and Dynamic
dv/dt Ruggedness
l Fully Characterized Capacitance and
Avalanche Voltage and Current
l Enhanced Body Diode dv/dt Capability
l
VDSS
RDS(on) max
ID
100V
0.025Ω
48A†
D-Pak
IRFR3412
I-Pak
IRFU3412
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
dv/dt
TJ
TSTG
Max.
48†
34†
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current 
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery dv/dt ƒ
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 second
Mounting torqe, 6-32 or M3 screw
190
140
0.95
± 20
6.4
-55 to + 175
Units
A
W
W/°C
V
V/ns
°C
300(1.6mm from case )
10 lbf•in (1.1N•m)
Diode Characteristics
Symbol
IS
ISM
VSD
trr
Qrr
IRRM
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode) 
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Reverse RecoveryCurrent
Forward Turn-On Time
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Min. Typ. Max. Units
–––
–––
48†
–––
–––
190
A
Conditions
MOSFET symbol
showing the
G
integral reverse
p-n junction diode.
TJ = 25°C, IS = 29A, VGS = 0V
TJ = 125°C, IF = 29A
di/dt = 100A/µs „
D
S
––– ––– 1.3
V
„
––– 68 100
ns
––– 160 240
nC
––– 4.5 6.8
A
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
1
1/22/02
IRFR/U3412
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
Gate Threshold Voltage
V(BR)DSS
IDSS
Drain-to-Source Leakage Current
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Min.
100
–––
–––
3.5
–––
–––
–––
–––
Typ.
–––
0.10
–––
–––
–––
–––
–––
–––
Max. Units
Conditions
–––
V
VGS = 0V, ID = 250µA
––– V/°C Reference to 25°C, ID = 1mA †
0.025
Ω
VGS = 10V, ID = 29A „
5.5
V
VDS = VGS, ID = 250µA
1.0
VDS = 95V, VGS = 0V
µA
250
VDS = 80V, VGS = 0V, TJ = 150°C
100
VGS = 20V
nA
-100
VGS = -20V
Dynamic @ TJ = 25°C (unless otherwise specified)
gfs
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
Min.
25
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
59
21
17
19
68
44
37
3430
270
150
1040
170
270
Max. Units
Conditions
–––
S
VDS = 50V, ID = 29A
89
ID = 29A
32
nC
VDS = 50V
26
VGS = 10V, „
–––
VDD = 50V
–––
ID = 29A
ns
–––
RG = 6.8Ω
–––
VGS = 10V „
–––
VGS = 0V
–––
VDS = 25V
–––
pF
ƒ = 1.0MHz
–––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 80V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 0V to 80V …
Avalanche Characteristics
Parameter
EAS
IAR
EAR
Single Pulse Avalanche Energy‚
Avalanche Current
Repetitive Avalanche Energy
Typ.
Max.
Units
–––
–––
–––
160
29
14
mJ
A
mJ
Typ.
Max.
Units
–––
–––
–––
1.05
50
110
°C/W
Thermal Resistance
Parameter
RθJC
RθJA
RθJA
Junction-to-Case
Junction-to-Ambient (PCB mount)*
Junction-to-Ambient
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature. (See Fig. 11)
‚ Starting TJ = 25°C, L = 0.38mH, RG = 25Ω,
IAS = 29A, (See Figure 12a)
ƒ ISD ≤ 29A, di/dt ≤ 420A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 150°C
2
„ Pulse width ≤ 300µs; duty cycle ≤ 2%.
… Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
†Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 30A.
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IRFR/U3412
TOP
I D, Drain-to-Source Current (A)
100
BOTTOM
1000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
10
1
0.1
4.5V
1
10
BOTTOM
100
10
4.5V
20µs PULSE WIDTH
T J= 175 ° C
20µs PULSE WIDTH
T J= 25 ° C
1
0.01
0.1
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
TOP
I D, Drain-to-Source Current (A)
1000
0.1
100
1
10
100
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
3.0
I D = 48A
°
JT = 175 C
10
°
T
J = 25 C
1
V DS= 25V
20µs PULSE WIDTH
0.1
4.0
5.0
6.0
7.0
8.0
V GS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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9.0
2.0
(Normalized)
100
RDS(on) , Drain-to-Source On Resistance
I D, Drain-to-Source Current (A)
2.5
1.5
1.0
0.5
V GS = 10V
0.0
-60
-40
-20
0
20
40
60
80
TJ , Junction Temperature
100 120 140 160 180
( °C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRFR/U3412
VGS = 0V,
f = 1 MHZ
C iss
= C gs + Cgd ,
SHORTED
20
C ds
VGS , Gate-to-Source Voltage (V)
C, Capacitance (pF)
100000
Crss = C gd
Coss = Cds + Cgd
10000
Ciss
1000
Coss
Crss
ID= 29A
VDS = 80V
VDS= 50V
VDS= 20V
16
12
8
4
0
100
0
1
10
20
40
60
80
100
100
Q G Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000
1000.0
100.0
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100
T J = 175°C
10.0
1.0
T J = 25°C
100µsec
10
1msec
1
VGS = 0V
0.1
0.1
0.0
0.5
1.0
1.5
2.0
2.5
VSD, Source-toDrain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
3.0
Tc = 25°C
Tj = 175°C
Single Pulse
1
10msec
10
100
1000
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRFR/U3412
50
RD
V DS
LIMITED BY PACKAGE
VGS
ID , Drain Current (A)
40
D.U.T.
RG
+
-VDD
VGS
30
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
20
Fig 10a. Switching Time Test Circuit
VDS
10
90%
0
25
50
75
100
125
TC , Case Temperature
150
175
( °C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
(Z thJC)
10
1
Thermal Response
D = 0.50
0.20
P DM
0.10
0.1
0.05
0.02
0.01
t1
SINGLE PULSE
(THERMAL RESPONSE)
t2
Notes:
1. Duty factor D =
2. Peak T
0.01
0.00001
0.0001
0.001
t1/ t 2
J = P DM x Z thJC
+T C
0.01
0.1
t 1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFR/U3412
300
ID
15V
TOP
12A
BOTTOM
21A
29A
250
VDS
D.U.T
RG
IAS
VGS
20V
tp
DRIVER
+
V
- DD
A
0.01Ω
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
EAS , Single Pulse Avalanche Energy (mJ)
L
200
150
100
50
0
25
50
75
100
125
150
175
( °C)
Starting T , Junction
Temperature
J
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I AS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
50KΩ
QG
12V
.2µF
.3µF
VGS
QGS
D.U.T.
QGD
+
V
- DS
VGS
VG
3mA
IG
Charge
Fig 13a. Basic Gate Charge Waveform
6
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
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IRFR/U3412
Peak Diode Recovery dv/dt Test Circuit
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D.U.T
ƒ
+
‚
-
-
„
+

RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Driver Gate Drive
P.W.
Period
D=
+
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFET® Power MOSFETs
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7
IRFR/U3412
TO-252AA (D-Pak) Package Outline
Dimensions are shown in millimeters (inches)
2.38 (.094)
2.19 (.086)
6.73 (.265)
6.35 (.250)
1.14 (.045)
0.89 (.035)
-A1.27 (.050)
0.88 (.035)
5.46 (.215)
5.21 (.205)
0.58 (.023)
0.46 (.018)
4
6.45 (.245)
5.68 (.224)
6.22 (.245)
5.97 (.235)
1.02 (.040)
1.64 (.025)
10.42 (.410)
9.40 (.370)
1
2
LEAD ASSIGNMENTS
3
1 - GATE
0.51 (.020)
MIN.
-B1.52 (.060)
1.15 (.045)
3X
2X
1.14 (.045)
0.76 (.030)
0.89 (.035)
0.64 (.025)
0.25 (.010)
2 - DRAIN
3 - SOURCE
4 - DRAIN
0.58 (.023)
0.46 (.018)
M A M B
NOTES:
2.28 (.090)
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
4.57 (.180)
2 CONTROLLING DIMENSION : INCH.
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).
TO-252AA (D-Pak) Part Marking Information
EXAMPLE: THIS IS AN IRFR120
WIT H ASS EMBLY
LOT CODE 1234
AS SEMBLED ON WW 16, 1999
IN T HE ASS EMBLY LINE "A"
PART NUMBER
INT ERNAT IONAL
RECT IFIER
LOGO
12
AS SEMBLY
LOT CODE
8
IRF U120
916A
34
DAT E CODE
YEAR 9 = 1999
WEEK 16
LINE A
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IRFR/U3412
TO-251AA (I-Pak) Package Outline
Dimensions are shown in millimeters (inches)
6.73 (.265)
6.35 (.250)
2.38 (.094)
2.19 (.086)
-A1.27 (.050)
0.88 (.035)
5.46 (.215)
5.21 (.205)
0.58 (.023)
0.46 (.018)
LEAD ASSIGNMENTS
4
1 - GATE
2 - DRAIN
6.45 (.245)
5.68 (.224)
1
2
3
-B2.28 (.090)
1.91 (.075)
3X
3 - SOURCE
4 - DRAIN
6.22 (.245)
5.97 (.235)
1.52 (.060)
1.15 (.045)
1.14 (.045)
0.76 (.030)
2.28 (.090)
3X
9.65 (.380)
8.89 (.350)
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH.
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).
0.89 (.035)
0.64 (.025)
1.14 (.045)
0.89 (.035)
0.25 (.010)
M A M B
2X
0.58 (.023)
0.46 (.018)
TO-251AA (I-Pak) Part Marking Information
EXAMPLE: THIS IS AN IRFR120
WIT H ASS EMBLY
LOT CODE 5678
ASSEMBLED ON WW 19, 1999
IN THE AS SEMBLY LINE "A"
PART NUMBER
INT ERNAT IONAL
RECT IFIER
LOGO
IRF U120
919A
78
56
DAT E CODE
YEAR 9 = 1999
WEEK 19
LINE A
AS SEMBLY
LOT CODE
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9
IRFR/U3412
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
FEED DIRECTION
TRL
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
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10