KERSEMI IRFU3704Z

PD - 94725
IRFR3704Z
IRFU3704Z
Applications
l High Frequency Synchronous Buck
Converters for Computer Processor Power
l High Frequency Isolated DC-DC
Converters with Synchronous Rectification
for Telecom and Industrial Use
HEXFET® Power MOSFET
VDSS RDS(on) max
8.4m:
20V
Benefits
l Very Low RDS(on) at 4.5V VGS
l Ultra-Low Gate Impedance
l Fully Characterized Avalanche Voltage
and Current
D-Pak
IRFR3704Z
Qg
9.3nC
I-Pak
IRFU3704Z
Absolute Maximum Ratings
Parameter
VDS
Drain-to-Source Voltage
Max.
Units
20
V
VGS
Gate-to-Source Voltage
± 20
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V
60
ID @ TC = 100°C
Continuous Drain Current, VGS @ 10V
42
IDM
Pulsed Drain Current
240
PD @TC = 25°C
Maximum Power Dissipation
48
PD @TC = 100°C
Maximum Power Dissipation
24
f
f
c
Linear Derating Factor
0.32
TJ
Operating Junction and
-55 to + 175
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
A
W
W/°C
°C
300 (1.6mm from case)
Thermal Resistance
Parameter
RθJC
Junction-to-Case
RθJA
Junction-to-Ambient (PCB Mount)
RθJA
Junction-to-Ambient
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g
Typ.
Max.
Units
–––
3.1
°C/W
–––
50
–––
110
1
07/10/03
IRFR/U3704Z
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
BVDSS
Drain-to-Source Breakdown Voltage
20
–––
–––
∆ΒVDSS/∆TJ
Breakdown Voltage Temp. Coefficient
–––
0.015
–––
RDS(on)
Static Drain-to-Source On-Resistance
–––
6.7
8.4
–––
9.2
11.4
V
V/°C Reference to 25°C, ID = 1mA
mΩ VGS = 10V, ID = 15A
VGS = 4.5V, ID = 12A
VGS(th)
Gate Threshold Voltage
1.65
2.1
2.55
V
∆VGS(th)/∆TJ
Gate Threshold Voltage Coefficient
–––
-5.5
–––
mV/°C
IDSS
Drain-to-Source Leakage Current
–––
–––
1.0
µA
–––
–––
150
IGSS
Gate-to-Source Forward Leakage
–––
–––
100
Gate-to-Source Reverse Leakage
–––
–––
-100
gfs
Qg
Conditions
VGS = 0V, ID = 250µA
e
e
VDS = VGS, ID = 250µA
VDS =16V, VGS = 0V
VDS = 16V, VGS = 0V, TJ = 125°C
nA
VGS = 20V
VGS = -20V
Forward Transconductance
41
–––
–––
Total Gate Charge
–––
9.3
14
S
VDS = 10V, ID = 12A
Qgs1
Pre-Vth Gate-to-Source Charge
–––
3.0
–––
Qgs2
Post-Vth Gate-to-Source Charge
–––
1.1
–––
nC
VGS = 4.5V
Qgd
Gate-to-Drain Charge
–––
2.7
–––
ID = 12A
Qgodr
–––
2.5
–––
See Fig. 16
Qsw
Gate Charge Overdrive
Switch Charge (Qgs2 + Qgd)
–––
3.8
–––
Qoss
Output Charge
–––
5.6
–––
td(on)
Turn-On Delay Time
–––
41
–––
VDD = 10V, VGS = 4.5V
tr
Rise Time
–––
8.9
–––
ID = 12A
td(off)
Turn-Off Delay Time
–––
4.9
–––
tf
Fall Time
–––
12
–––
Ciss
Input Capacitance
–––
1190
–––
Coss
Output Capacitance
–––
380
–––
Crss
Reverse Transfer Capacitance
–––
170
–––
VDS = 10V
nC
VDS = 10V, VGS = 0V
e
ns
Clamped Inductive Load
pF
VDS = 10V
VGS = 0V
ƒ = 1.0MHz
Avalanche Characteristics
EAS
Parameter
Single Pulse Avalanche Energy
IAR
Avalanche Current
EAR
Repetitive Avalanche Energy
c
Typ.
–––
d
c
Units
mJ
Max.
41
–––
12
A
–––
4.8
mJ
Diode Characteristics
Parameter
IS
Continuous Source Current
Min. Typ. Max. Units
f
–––
60
–––
–––
240
showing the
integral reverse
p-n junction diode.
TJ = 25°C, IS = 12A, VGS = 0V
(Body Diode)
ISM
Pulsed Source Current
c
MOSFET symbol
A
(Body Diode)
VSD
Diode Forward Voltage
–––
–––
1.0
V
trr
Reverse Recovery Time
–––
13
19
ns
Qrr
Reverse Recovery Charge
–––
4.2
6.3
nC
ton
2
Forward Turn-On Time
Conditions
–––
D
G
S
e
TJ = 25°C, IF = 12A, VDD = 10V
di/dt = 100A/µs
e
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
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IRFR/U3704Z
1000
1000
100
10
BOTTOM
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
10V
6.0V
4.5V
4.0V
3.3V
2.8V
2.6V
2.4V
1
0.1
2.4V
0.01
100
10
BOTTOM
VGS
10V
6.0V
4.5V
4.0V
3.3V
2.8V
2.6V
2.4V
2.4V
1
0.1
20µs PULSE WIDTH
Tj = 175°C
20µs PULSE WIDTH
Tj = 25°C
0.01
0.001
0.01
0.1
1
0.01
10
1
10
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
2.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
1000
ID, Drain-to-Source Current (Α)
0.1
T J = 175°C
100
10
1
T J = 25°C
0.1
VDS = 10V
20µs PULSE WIDTH
ID = 30A
VGS = 10V
1.5
1.0
0.5
0.01
2
3
4
5
6
7
8
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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9
-60 -40 -20 0
20 40 60 80 100 120 140 160 180
T J , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
vs. Temperature
3
IRFR/U3704Z
10000
6.0
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
VGS, Gate-to-Source Voltage (V)
ID= 12A
C, Capacitance(pF)
C oss = C ds + C gd
Ciss
1000
Coss
Crss
VDS= 18V
VDS= 10V
5.0
4.0
3.0
2.0
1.0
100
0.0
1
10
100
0
VDS, Drain-to-Source Voltage (V)
8
10
12
14
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
6
1000
1000.00
100.00
T J = 175°C
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100
10.00
T J = 25°C
100µsec
10
1msec
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
10msec
1
0.10
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
VSD, Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
4
QG Total Gate Charge (nC)
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
1.00
2
0
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRFR/U3704Z
60
Limited By Package
50
ID, Drain Current (A)
VGS(th) Gate threshold Voltage (V)
2.5
40
30
20
10
2.0
ID = 250µA
1.5
1.0
0.5
0
25
50
75
100
125
150
-75 -50 -25
175
0
25
50
75 100 125 150 175 200
T J , Temperature ( °C )
T C , Case Temperature (°C)
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Threshold Voltage vs. Temperature
Thermal Response ( Z thJC )
10
D = 0.50
1
0.20
0.10
0.05
0.1
0.02
0.01
τJ
SINGLE PULSE
( THERMAL RESPONSE )
0.01
R1
R1
τJ
τ1
τ1
R2
R2
τ2
R3
R3
Ri (°C/W)
R4
R4
τC
τ
τ2
τ3
τ3
Ci= τi/Ri
Ci i/Ri
τ4
τ4
τi (sec)
0.8190
0.000092
1.6018
0.000698
0.6592
0.009033
0.0418
0.046618
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFR/U3704Z
15V
D.U.T
RG
+
V
- DD
IAS
VGS
20V
A
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
EAS , Single Pulse Avalanche Energy (mJ)
DRIVER
L
VDS
180
ID
4.9A
6.5A
BOTTOM 12A
160
TOP
140
120
100
80
60
40
20
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
LD
I AS
VDS
Fig 12b. Unclamped Inductive Waveforms
+
VDD D.U.T
Current Regulator
Same Type as D.U.T.
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
50KΩ
12V
.2µF
.3µF
D.U.T.
+
V
- DS
Fig 14a. Switching Time Test Circuit
VDS
90%
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 13. Gate Charge Test Circuit
10%
VGS
td(on)
tr
td(off)
tf
Fig 14b. Switching Time Waveforms
6
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IRFR/U3704Z
D.U.T
Driver Gate Drive
+
P.W.
ƒ
+
‚
-
-
„
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+

RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D=
Period
VDD
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Id
Vds
Vgs
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 16. Gate Charge Waveform
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7
IRFR/U3704Z
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET
Synchronous FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
The power loss equation for Q2 is approximated
by;
*
Ploss = Pconduction + Pdrive + Poutput
(
2
Ploss = Irms × Rds(on)
)
Power losses in the control switch Q1 are given
by;
+ (Qg × Vg × f )
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
Q

+  oss × Vin × f + (Qrr × Vin × f )

 2
This can be expanded and approximated by;
*dissipated primarily in Q1.
Ploss = (Irms × Rds(on ) )
2

Qgs 2
 
Qgd
+I×
× Vin × f  +  I ×
× Vin ×
ig
ig
 


f

+ (Qg × Vg × f )
+
 Qoss
× Vin × f 
 2

This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (nonlinear) capacitance’s Cds and Cdg when multiplied by
the power supply input buss voltage.
For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the control IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Figure A: Qoss Characteristic
8
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IRFR/U3704Z
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
2.38 (.094)
2.19 (.086)
6.73 (.265)
6.35 (.250)
1.14 (.045)
0.89 (.035)
-A1.27 (.050)
0.88 (.035)
5.46 (.215)
5.21 (.205)
0.58 (.023)
0.46 (.018)
4
6.45 (.245)
5.68 (.224)
6.22 (.245)
5.97 (.235)
1.02 (.040)
1.64 (.025)
1
2
10.42 (.410)
9.40 (.370)
LEAD ASSIGNMENTS
1 - GATE
3
0.51 (.020)
MIN.
-B1.52 (.060)
1.15 (.045)
3X
2X
1.14 (.045)
0.76 (.030)
0.89 (.035)
0.64 (.025)
0.25 (.010)
2 - DRAIN
3 - SOURCE
4 - DRAIN
0.58 (.023)
0.46 (.018)
M A M B
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2.28 (.090)
4.57 (.180)
2 CONTROLLING DIMENSION : INCH.
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).
D-Pak (TO-252AA) Part Marking Information
Notes: T his part marking information applies to devices produced before 02/26/2001
EXAMPLE: T HIS IS AN IRFR120
WIT H AS S EMBLY
LOT CODE 9U1P
INT ERNAT IONAL
RECTIFIER
LOGO
IRFU120
9U
016
1P
DAT E CODE
YEAR = 0
WEEK = 16
AS S EMBLY
LOT CODE
Notes : T his part marking information applies to devices produced after 02/26/2001
EXAMPLE: T HIS IS AN IRFR120
WIT H AS S EMBLY
LOT CODE 1234
AS S EMBLED ON WW 16, 1999
IN T HE AS S EMBLY LINE "A"
INT ERNAT IONAL
RECT IFIER
LOGO
IRFU120
12
AS S EMBLY
LOT CODE
www.kersemi.com
PART NUMBER
916A
34
DAT E CODE
YEAR 9 = 1999
WEEK 16
LINE A
9
IRFR/U3704Z
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
6.73 (.265)
6.35 (.250)
2.38 (.094)
2.19 (.086)
-A-
0.58 (.023)
0.46 (.018)
1.27 (.050)
0.88 (.035)
5.46 (.215)
5.21 (.205)
LEAD ASSIGNMENTS
4
1 - GATE
2 - DRAIN
3 - SOURCE
4 - DRAIN
6.45 (.245)
5.68 (.224)
6.22 (.245)
5.97 (.235)
1.52 (.060)
1.15 (.045)
1
2
3
-B-
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2.28 (.090)
1.91 (.075)
3X
9.65 (.380)
8.89 (.350)
1.14 (.045)
0.76 (.030)
2.28 (.090)
3X
2 CONTROLLING DIMENSION : INCH.
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).
1.14 (.045)
0.89 (.035)
0.89 (.035)
0.64 (.025)
0.25 (.010)
M A M B
2X
0.58 (.023)
0.46 (.018)
I-Pak (TO-251AA) Part Marking Information
Notes : T his part marking information applies to devices produced before 02/26/2001
EXAMPLE: T HIS IS AN IRFR120
WIT H AS S EMBLY
LOT CODE 9U1P
INTERNATIONAL
RECT IFIER
LOGO
IRFU120
016
9U
1P
DAT E CODE
YEAR = 0
WEEK = 16
AS S EMBLY
LOT CODE
Notes : T his part marking information applies to devices produced after 02/26/2001
EXAMPLE: T HIS IS AN IRFR120
WIT H AS S EMBLY
LOT CODE 5678
AS S EMBLED ON WW 19, 1999
IN T HE AS S EMBLY LINE "A"
INT ERNAT IONAL
RECT IFIER
LOGO
IRFU120
919A
56
AS S EMBLY
LOT CODE
10
PART NUMBER
78
DAT E CODE
YEAR 9 = 1999
WEEK 19
LINE A
www.kersemi.com
IRFR/U3704Z
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
FEED DIRECTION
TRL
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature.
‚ Starting TJ = 25°C, L = 0.57mH, RG = 25Ω,
IAS = 12A.
ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%.
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„ Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 30A.
… When mounted on 1" square PCB (FR-4 or G-10 Material).
For recommended footprint and soldering techniques refer to
application note #AN-994.
11