IRFR014, IRFU014, SiHFR014, SiHFU014 Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • Dynamic dV/dt Rating 60 RDS(on) (Ω) VGS = 10 V Qg (Max.) (nC) 11 • Straight Lead (IRFU014/SiHFU014) Qgs (nC) 3.1 • Available in Tape and Reel Qgd (nC) 5.8 Configuration Available • Surface Mount (IRFR014/SiHFR014) 0.20 RoHS* COMPLIANT • Fast Switching Single • Ease of Paralleling D • Simple Drive Requirements DPAK (TO-252) • Lead (Pb)-free Available IPAK (TO-251) DESCRIPTION G Third generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The DPAK is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRFU/SiHFU series) is for through-hole mounting applications. Power dissipation levels up to 1.5 W are possible in typical surface mount applications. S N-Channel MOSFET ORDERING INFORMATION Package Lead (Pb)-free SnPb DPAK (TO-252) DPAK (TO-252) DPAK (TO-252) IPAK (TO-251) IRFR014PbF IRFR014TRLPbFa IRFR014TRPbFa IRFU014PbF SiHFR014-E3 SiHFR014TL-E3a SiHFR014T-E3a SiHFU014-E3 IRFR014 IRFR014TRLa IRFR014TRa IRFU014 SiHFR014 SiHFR014TLa SiHFR014Ta SiHFU014 Note a. See device orientation. ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 60 Gate-Source Voltage VGS ± 20 VGS at 10 V Continuous Drain Current TC = 25 °C TC = 100 °C Pulsed Drain Currenta ID IDM Linear Derating Factor Linear Derating Factor (PCB EAS Maximum Power Dissipation TC = 25 °C Maximum Power Dissipation (PCB Mount)e TA = 25 °C Peak Diode Recovery dV/dtc 4.9 PD dV/dt A 31 0.020 Single Pulse Avalanche Energyb V 7.7 0.20 Mount)e UNIT 47 25 2.5 4.5 W/°C mJ W V/ns www.kersemi.com 1 IRFR014, IRFU014, SiHFR014, SiHFU014 ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted PARAMETER Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) SYMBOL LIMIT UNIT TJ, Tstg - 55 to + 150 °C 260d for 10 s Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = 25 V, starting TJ = 25 °C, L = 924 µH, RG = 25 Ω, IAS = 7.7 A (see fig. 12). c. ISD ≤ 10 A, dI/dt ≤ 90 A/µs, VDD ≤ VDS, TJ ≤ 150 °C. d. 1.6 mm from case. e. When mounted on 1" square PCB (FR-4 or G-10 material). THERMAL RESISTANCE RATINGS PARAMETER SYMBOL MIN. TYP. MAX. Maximum Junction-to-Ambient RthJA - - 110 Maximum Junction-to-Ambient (PCB Mount)a RthJA - - 50 Maximum Junction-to-Case (Drain) RthJC - - 5.0 UNIT °C/W Note a. When mounted on 1" square PCB (FR-4 or G-10 material). SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS VGS = 0 V, ID = 250 µA 60 - - V ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.068 - V/°C VGS(th) VDS = VGS, ID = 250 µA 2.0 - 4.0 V Gate-Source Leakage IGSS VGS = ± 20 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS VDS = 60 V, VGS = 0 V - - 25 VDS = 48 V, VGS = 0 V, TJ = 125 °C - - 250 Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Drain-Source On-State Resistance Forward Transconductance RDS(on) gfs µA - - 0.20 Ω VDS = 25 V, ID = 4.6 A 2.4 - - S VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 - 300 - - 160 - - 29 - - - 11 - - 3.1 ID = 4.6 Ab VGS = 10 V Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs VGS = 10 V ID = 10 A, VDS = 48 V, see fig. 6 and 13b Gate-Drain Charge Qgd - - 5.8 Turn-On Delay Time td(on) - 10 - - 50 - - 13 - - 19 - - 4.5 - - 7.5 - Rise Time Turn-Off Delay Time Fall Time tr td(off) VDD = 30 V, ID = 10 A, RG = 24 Ω, RD = 2.7 Ω, see fig. 10b tf Internal Drain Inductance LD Internal Source Inductance LS Between lead, 6 mm (0.25") from package and center of die contactc D nC ns nH G S www.kersemi.com 2 pF IRFR014, IRFU014, SiHFR014, SiHFU014 SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. - - 7.7 - - 31 UNIT Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Currenta ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode D A G S TJ = 25 °C, IS = 7.7 A, VGS = 0 Vb TJ = 25 °C, IF = 10 A, dI/dt = 100 A/µsb - - 1.6 V - 70 140 ns - 0.20 0.40 µC Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %. TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted Fig. 1 - Typical Output Characteristics, TC = 25 °C Fig. 2 - Typical Output Characteristics, TC = 150 °C Fig. 3 - Typical Transfer Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature www.kersemi.com 3 IRFR014, IRFU014, SiHFR014, SiHFU014 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage www.kersemi.com 4 Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 8 - Maximum Safe Operating Area IRFR014, IRFU014, SiHFR014, SiHFU014 VDS VGS RD D.U.T. RG + - VDD 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Fig. 10a - Switching Time Test Circuit VDS 90 % 10 % VGS td(on) Fig. 9 - Maximum Drain Current vs. Case Temperature tr td(off) tf Fig. 10b - Switching Time Waveforms Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case www.kersemi.com 5 IRFR014, IRFU014, SiHFR014, SiHFU014 L Vary tp to obtain required IAS VDS VDS tp VDD D.U.T RG + - I AS V DD VDS 10 V 0.01 Ω tp Fig. 12a - Unclamped Inductive Test Circuit IAS Fig. 12b - Unclamped Inductive Waveforms Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ QG VGS 12 V 0.2 µF 0.3 µF QGS QGD + D.U.T. VG - VDS VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform www.kersemi.com 6 Fig. 13b - Gate Charge Test Circuit IRFR014, IRFU014, SiHFR014, SiHFU014 Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - + RG + • dV/dt controlled by RG • ISD controlled by duty factor "D" • D.U.T. - device under test Driver gate drive P.W. Period D= - VDD P.W. Period VGS = 10 V* D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage VDD Body diode forward drop Inductor current Ripple ≤ 5 % ISD * VGS = 5 V for logic level and 3 V drive devices Fig. 14 - For N-Channel www.kersemi.com 7