LSI/CSI LS8292 LS8293 LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405 PRELIMINARY MICRO-STEPPING MOTOR CONTROLLER June 2013 FEATURES: Controls Bipolar and Unipolar stepper motors Step modes: Full, 1/2, 1/4, 1/8, 1/16 and 1/32 PWM outputs for external H-bridge drivers Precision DAC reference for PWM sense comparators Fast, Slow and mixed decay modes Power saving holding torque for idling motor Automatic switching to holding torque with programmable delay when motor idles Programmable delay for sense input blanking Programmable delay for mixed decay cycles Input for Step command Input for Direction control Input for Reset to HOME Input for disabling PWM outputs Input/output for external clock or built-in oscillator Supply current < 400uA Supply voltage 4.5V to 5.5V LS8292 (DIP), LS8292-S (SOIC), LS8292-TS (TSSOP) LS8293 (DIP), LS8293-S (SOIC), LS8293-TS (TSSOP) DESCRIPTION: LS8292 and LS8293 are stepper motor controllers with selectable resolutions from Full to 1/32 step. There are four phase drive outputs and two inhibit outputs for controlling 2phase bipolar or 4-phase unipolar motors. These outputs are designed to drive two external H-bridge drivers for bipolar motor windings or four external transistors for center-tapped unipolar motor windings. These outputs can also be configured to drive discrete external transistors for bipolar motor windings. A lookup table sources the PWM duty cycle digital data for the two motor windings corresponding to the step sequence. Two internal DACs convert the PWM data to analog voltages as percentages of the reference voltage applied at the Vref input. Currents through the motor windings are monitored at the SENSE inputs as voltage drops across fractional-Ohm resistors in series with the H-bridge drivers. Upon turning on a PWM drive, when the voltage at the SENSE input reaches the DAC reference level, the PWM output is switched off for remainder of the cycle. The PWM cycle is fixed at Tpwm = 256/fc, where fc is the clock frequency at the XTLI input. The PWM cycles for the two drives are started 8292-061413-1 simultaneously but terminated separately per individual DAC references. An input is provided for the holding torque state at lower winding current in the motor idle state. The holding-torque current level is adjusted with a separate reference voltage applied at the Vrefh input. The Vrefh is automatically switched in if the motor idles for a programmable specified delay following a micro-step. PWM chopping can be applied either to the PHASE or to the INHIBIT outputs. The chopping mode affects the manner in which the winding current decays during a PWM cycle. There are four selectable decay modes: Fast-decay, Slowdecay, Single-mixed-decay and Dual-mixed-decay. In the Fast-decay mode the diagonal high side and low side transistors of the H-bridge are both turned off during the PWM off period. This causes the inductive current to be dissipated through the bypass diodes in a direction opposing the motor supply voltage resulting in fast decay. In the Slow-decay mode the low side transistor of the H-bridge is turned off keeping the high side transistor on during the PWM off period. This causes the inductive current to re-circulate through the high side transistor and diode loop. The current decays slowly because of the low loop voltage. The Slow-decay can be useful for motors that do not store enough energy in the windings leading to an average current too low for any useful torque. In the Single-mixed-decay mode, slow and fast decays are combined in the following way: ♦ When the motor is idle, slow decay is applied to both windings to guarantee lowest current ripple in a holding state. ♦ When the motor is stepping, if the step requires the current in a winding to decrease, fast decay is applied to the winding for a programmable duration followed by slow decay. If the step requires the current in a winding to increase, slow decay is applied to the winding. In Dual-mixed-decay mode, mixed decay is applied to both windings for every step with fast decay being followed by slow decay. One of six stepping modes can be selected by two input pins: Full, 1/2, 1/4, 1/8, 1/16 and 1/32. An internal oscillator generates the system clock and sets the PWM period. The oscillator pin can also be driven by an external clock. Other available inputs are for step command, direction control, resetting to home position, disabling the H-bridge drives, SENSE input blanking delay control and fast to slow switching delay control in the mixed decay modes. INPUT/OUTPUT DESCRIPTION: XTLI, XTLO A crystal connected between these two pins sets the system clock frequency. Alternatively, XTLI pin can be driven by an external clock for providing the system clock. The PWM period Tpwm, is related to the system clock frequency as follows: Tpwm = 256/fc, where, fc is the system clock frequency applied at the XTLI input. M0, M1 M0 is a 3-state input amd M1 is a 2-state input; together they select the step mode as follows: Table 1 M1 M0 Step Mode 0 0 Full Step 1 0 1/2 Step 0 float 1/4 Step 1 float 1/8 Step 0 1 1/16 Step 1 1 1/32 Step RESET/ When low, RESET/ input clears the step pointer to HOME position per table 4. This input has an internal pull-up resistor. STEP/ A low pulse at the STEP/ input causes the motor to advance one step forward or reverse. The step size is selected per Table 1. FWD When high, the FWD input causes the motor to step in the forward direction per incremental step sequence of Table 4. When low, the motor steps in the reverse direction per decremental step sequence of Table 4. EN/ When high, EN/ input causes all motor drive outputs to be disabled bringing INH1/, INH2/, PHA, PHB, PHC and PHD low. When ENABLE/ is low, all motor drive outputs are enabled. HOME/ HOME/ is an open drain output to indicate step0 per Table 4 with an active low. Vref Input for the chopper circuit DAC reference voltage. It regulates the peak motor winding current by regulating the PWM duty cycle. The DAC modifies the Vref input voltage for the current sensing comparators at every sequential motor step which can be estimated with the following equations: Vsens1 = | (Vref/7) x cos((90/32) x (n + 16))º | Vsens2 = | (Vref/7) x sin((90/32) x (n + 16))º | Where, n is the 1/32 column step number in Table 6. The sense resistors should satisfy the relation: Rs1 = Rs2 = Vref/(7 x Imax) 8292-021811-2 where, Imax is the maximum motor winding current and Rs1 and Rs2 are the fractional-Ohm sense resistors in series with each phase of the H-bridge driver transistors. Vrefh Input for the holding torque reference voltage when the holding torque mode is enabled. The holding torque reference voltage should satisfy the relation: Vrefh = 7 x Rs1 x Imaxh = 7 x Rs2 x Imaxh, Where, Imaxh is the maximum winding current intended in the holding state and Rs1 and Rs2 are the fractional Ohm sense resistors in series with each phase of the H-bridge driver transistors. SENSE1, SENSE2 Inputs for motor winding current sense. A fractional-Ohm resistor connected in series with each of the H-bridge drivers produce SENSE1 and SENSE2 voltages. These voltages are compared with the DAC modulated reference voltages for generating the PWM phase or inhibit outputs. PHA, PHB, PHC, PHD Phase drive outputs for power stages. In a bipolar motor, PHA and PHB are used for one H-bridge while PHC and PHD are used for the other. In the slow-decay mode the phase outputs are chopped by means of the current sense comparators. In the fast-decay mode the phase outputs are kept enabled while the inhibit outputs are chopped. INH1/, INH2/ These outputs are active low inhibit controls for motor drive outputs. INH1/ controls driver stage using PHA and PHB outputs while INH2/ controls driver stage using PHC and PHD outputs. In the fast-decay mode inhibit outputs are chopped by means of the current sense comparators. In the slow-decay mode the inhibit outputs are enabled while the phase outputs are chopped. SYNC/ This open drain output produces a negative-going pulse occurring at the beginning of every PWM cycle which can be use to drive an external slope compensation circuit. Slope compensation may be useful at PWM duty cycle exceeding 50%, particularly in the fast-decay mode. TBLNK A resistor-capacitor pair connected to the TBLNK input controls the delay for which the sense input sampling is inhibited at the beginning of each PWM cycle. The delay is given by: Tblnk = 1.2 x RbCb Where, Rb and Cb are the resistor and the capacitor connected to the TBLNK pin. THLD A resistor-capacitor pair connected to this pin produces the holding torque initiation delay following a step command. Upon delay timeout the normal torque reference voltage Vref is switched out from the sense comparators, being replaced with the holding torque reference voltage Vrefh. The holding torque at lower dissipation prevails as long as the motor remains idle. The delay is given by: Thld = 1.4 x RhCh Where, Rh and Ch are the resistor and the capacitor connected to the THLD pin. If the pin is tied low, holding torque mode is disabled and normal torque prevails in both dynamic and idle motor states. DCYM, TDCYD, TDCYU DCYM and TDCYD inputs control the PWM decay modes for the LS8292 as follows: DCYM 1 1 0 Table 2 TDCYD Decay Mode 0 Fast 1 Slow RdCd Single-Mixed DCYM, TDCYD and TDCYU inputs control the PWM decay modes for the LS8293 as follows: DCYM 1 1 0 0 Table3 TDCYD TDCYU 0 x 1 x RdCd 0 RdCd RuCu Decay Mode Fast Slow Single-Mixed Dual-Mixed Fast-Decay. Phase output are enabled while inhibit outputs are chopped in both dynamic and idle motor states. Slow-Decay. Inhibit output are enabled while phase outputs are chopped in both dynamic and idle motor states. Single-Mixed-Decay. Following a stepping event, if the step requires the current in a winding to decrease, fast decay is applied to the winding for a programmable duration followed by slow decay. The duration is given by: Tdcyd = 1.2 x RdCd, where Rd and Cd are the resistor and the capacitor connected to the TDCYD pin. PIN ASSIGNMENT TOP VIEW M0 24 1 2 23 INH1/ DCYM 3 22 INH2/ RESET/ 4 21 PHA STEP/ 5 20 PHB FWD 6 19 PHC EN/ 7 18 PHD HOME/ 8 17 TBLNK XTLO 9 16 TDCYD XTLI 10 15 SENSE1 DGND 11 14 SENSE2 Vref 12 13 AGND 1 28 VDD M0 LS8292 24 M1 24 2 27 DCYM 3 26 24 RESET/ If motor is idle, slow decay is applied to both windings. VDD Supply voltage positive terminal. DGND Supply negative terminal for digital ground. AGND Analog ground; must be connected together with DGND on the PCB. 8292-021811-3 STEP/ FWD 25 24 24 24 6 23 24 HOME/ 8 24 XTLO XTLI DGND SYNC/ TDCYU THLD 24 9 PHA 24 5 7 INH2/ 24 4 EN/ INH1/ 24 24 Dual-Mixed-Deacy. Following a stepping event fast decay is applied to both windings for programmable durations followed by slow decay. The duration of the fast decay for the winding requiring lower current following a stepping event is given by: Tdcyd = 1.2 x RdCd and the duration of the fast decay for the winding requiring higher current following a stepping event is given by: Tdcyu = 1.2 x RuCu. Ru and Cu are the resistor and the capacitor connected to the TDCYU pin. VDD M1 24 If the step requires the current in a winding to increase, slow decay is applied to the winding. If motor is idle, slow decay is applied to both windings. 24 24 24 LS8293 22 PHB PHC PHD PHD 24 21 24 20 24 24 10 19 24 24 11 18 24 24 12 17 24 24 13 16 24 24 14 15 24 24 TBLNK TDCYD SENSE1 SENSE2 AGND Vref Vrefh VDD EN/ DCYM M0 MODE SELECT M1 INH1/ Vr VDD INH2/ DAC RESET/ STEP/ FWD + STEP CONTROL & LOOK-UP TABLE Vr OUTPUT CONTROL PHA PHB PHC DAC HOME/ - PHD + THLD TBLNK XTLI Vr XTLO TDCYD TDCYU SENSE1 MUX SENSE2 DGND AGND Vref Vrefh FIG 2. LS8292/LS8293 BLOCK DIAGRAM 8292-021811-4 TABLE 4 ABSOLUTE MAXIMUM RATINGS SYMBOL VALUE PARAMETER DC Supply Voltage Input Voltage (all inputs) Operating Temperature Storage Temperature PARAMETER VDD Vin TA TSTG +7 GND – 0.3 to VDD + 0.3 -25 to +85 -65 to +125 V V ºC ºC TABLE 5 ELECTRICAL AND TRANSIENT CHARACTERISTICS ( VDD = 5V, TA = -25 ºC TO +85 ºC ) SYMBOL MIN TYP MAX UNIT Supply Voltage Supply Current M0 Input Logic High M0 Input Logic Low Input Voltage Logic High (all other inputs) Input Voltage Logic Low (all other inputs) Input Current: RESET/ logic high Input Current: RESET/ logic low Input Current: M0 logic high Input Current: M0 logic low Input Current: logic high (all other inputs) Input Current: logic low (all other inputs) Output Current: Sink (Phase & Inhibit outputs) Output Current: Source (Phase & Inhibit outputs) Output Current: Sink (SYNC/ output) Output Current: Sink (HOME/ output) Output Current: source (HOME/ output) Input Reference Voltage (Vref & Vrefh) Sense Comparators Offset Voltage VDD IDD VMH VML VIH VIL IIRH IIRL IMH IML IIH IIL IOPIL IOPIH IOSL IOHL IOHH Vrf Vos TDCYD Input Timing Resistpr TDCYU Input Timing Resistor THLD Input Timing Resistor TBLNK Input Timing Resistor XTLI Input Frequency FWD Input set-up time for STEP/ STEP/ Input Pulse Width RESET/ Input Pulse Width SYNC/ Output Pulse Width PWM period 8292-021811-5 UNIT CONDITION 4.5 4.0 2.0 10 -5 10 10 -5 2.5 - 5.0 5 5 50 5.5 500 0.6 0.8 30 40 50 50 4.5 200 V uA V V V V uA uA uA uA nA nA mA mA mA mA mA V uV Rd Ru Rh Rb 2 2 4 6 - - kΩ kΩ kΩ kΩ - fc tfd Tspw Trpw Tsypw Tpwm 0 - 8.0 0 - MHz nS uS uS uS uS - 5.0 0 8/fc 8/fc 16/fc 255/fc Outputs floating, Inputs high VIH = 2V VIL = 0.8V VIH = 5V VIL = 0V Leakage Current Leakege Current Vout = 0.4V Vout = 4.6V Vout = 0.4V Vout = 0.4V Vout = 4.6V Vrf = 2V Icoil Slow Decay Slow Decay Tdcyu Dual Mixed Decay Step up Slow Decay Tdcyd Dual or Single Mixed Decay Step down Tpwm Time Fig 3. SINGLE AND DUAL MIXED-DECAY MODES +5V +Vm 9 4 VSS Vs 24 VDD 1 2 3 4 uC 5 6 7 INH1/ M0 INH2/ M1 DCYM PHA RESET/ PHB STEP/ PHC FWD PHD 23 6 22 11 21 5 20 7 19 10 18 12 EN/ Cm 9 10MΩ A B O1 XTLO TBLNK D O2 12 11 13 3 L298 13 17 O3 Cb XTLI +5V Vr 2 C Rb 5MHz 10 INH2/ +5V LS8292 Cm INH1/ O4 14 Rd Vref TDCYD 16 SNS1 SNS2 GND Cd DGND SENSE1 AGND SENSE2 1 15 8 15 14 Rs Rs NOTE. Cm is chosen according to following relation: Cm = 2(Cl – Cp) – 10pF, where Cl = Crystal load capacitance and Cp = parasitic capacitance Fig 4. LS8292 DRIVING TWO-PHASE BIPOLAR MOTOR 8292-061413-6 +5V +Vm 28 1 2 3 4 uC 5 6 7 M0 INH1/ M1 PHA PHB DCYM 27 BOOT1 EN 25 IN1 24 IN2 L6201 L6202 L6203 VREF RESET/ Cm 9 10MΩ BOOT2 EN/ +Vm XTLO 15nF Vs INH2/ XTLI PHC +5V PHD 26 BOOT1 EN 23 IN1 22 IN2 L6201 L6202 L6203 VREF Ru 13 15nF O2 GND FWD 5MHz 10 O1 220nF STEP/ LS8293 Cm 15nF Vs VDD O1 15nF BOOT2 220nF TDCYU Cu GND O2 +5V +5V Rb TBLNK Rh 14 21 Cb THLD Ch +5V Rd Vr 17 Vrh 18 TDCYD Vref 20 Cd Vrefh SENSE2 SENSE1 DGND AGND 11 17 18 19 NOTE1. All functional options have been implemented in this application. If all options are not used, following components can be deleted: ~Rd, Ru, Cd and Cu: if no mixed-decay mode id selected. ~Rh and Ch: if holding torque is not selected. In this case Vrefh pin is tied to GND. NOTE2. Cm is chosen according to following relation: Cm = 2(Cl – Cp) – 10pF, where Cl = Crystal load capacitance and Cp = parasitic capacitance Fig.5. LS8293 APPLICATION FOR TWO PHASE MOTOR USING TWO SEPARATE DRIVERS 8292-021811-7 +5V +Vm D 24 D VDD 1 2 4 uC 5 6 7 M0 74HC08 M1 PHA INH1/ RESET/ STEP/ PHB FWD SENSE1 21 Q1 23 Q2 20 +Vm 15 D EN/ R LS8292 Cm Cm 9 10MΩ 74HC08 XTLO PHC 5MHz 10 INH2/ XTLI PHD +5V SENSE2 3 Vr 12 D 19 Q3 22 Q4 18 14 +5V DCYM R Rb TBLNK Vref 17 Cb TDCYD DGND 11 16 AGND 13 NOTE 1. This design can operate in the Slow-decay mode only. NOTE 2. Q1, Q2, Q3 and Q4 are power MOSFETS suitable for 5V gate drive. Typical part numbers: IRLZ44N and IRF3708 NOTE 3. For higher pre-drive capability, 74HC08 can be replaced with MIC4468 NOTE 4. Cm is chosen according to following relation: Cm = 2(Cl – Cp) – 10pF, where Cl = Crystal load capacitance and Cp = parasitic capacitance Fig 6. TYPICAL APPLICATION FOR FOUR PHASE UNIPOLAR MOTOR USING DISCRETE MOSFETS 8292-021811-8 Vm 2kΩ 2kΩ BD679 6A10 6A10 BD679 1N4148 PHA INH1/ 2N5551 1N4148 6A10 6A10 6A10 BD679 6A10 2N5551 BD679 SENSE1 R PHB Vm LS8292 2kΩ 2kΩ BD679 6A10 6A10 BD679 1N4148 1N4148 PHC INH2/ 2N5551 6A10 6A10 6A10 BD679 6A10 2N5551 BD679 SENSE2 R PHD Note. All inverters are 74HC04, all NAND gates are 74HC00 and all AND gates are 74HC08 Fig.7. DISCRETE COMPONENT DRIVER 8292-021811-9 0.1uF +20V Vcc PHA Vm Vb HO IN Vs IR2104 INH1/ LO SD/ COM SENSE1 0.1uF +20V Vcc PHB R Vb HO IN Vs IR2104 LS8292 LS8293 SD/ LO COM 0.1uF +20V Vcc Vm Vb HO PHC Vs IR2104 INH2/ LO COM SENSE2 0.1uF +20V Vcc R Vb HO PHD Vs IR2104 LO COM Notes: Vm ≤ 100V. All MOSFETs are IRF540N, all diodes are 1N4002 Fig.8. BIPOLAR DRIVER USING N-CHANNEL MOSFETS 8292-061512-10 Table 6 PWM Duty Cycle (%) Step Number Full 1/2 1/4 1/8 0 0 0 0 1/16 1/32 INH1/ INH2/ PHA PHB PHC PHD 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 70.7 67.2 63.4 59.6 55.6 51.4 47.1 42.8 38.3 33.7 29.0 24.3 19.5 14.7 9.8 4.9 0.0 4.9 9.8 14.7 19.5 24.3 29.0 33.7 38.3 42.8 47.1 51.4 55.6 59.6 63.4 67.2 70.7 74.1 77.3 80.3 83.1 85.8 88.2 90.4 92.4 94.2 95.7 97.0 98.1 98.9 99.5 99.9 100 99.9 99.5 98.9 98.1 97.0 95.7 94.2 92.4 90.4 88.2 70.7 74.1 77.3 80.3 83.1 85.8 88.2 90.4 92.4 94.2 95.7 97.0 98.1 98.9 99.5 99.9 100 99.9 99.5 98.9 98.1 97.0 95.7 94.2 92.4 90.4 88.2 85.8 83.1 80.3 77.3 74.1 70.7 67.2 63.4 59.6 55.6 51.4 47.1 42.8 38.3 33.7 29.0 24.3 19.5 14.7 9.8 4.9 0.0 4.9 9.8 14.7 19.5 24.4 29.0 33.7 38.3 42.8 47.1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 2 3 1 2 4 5 3 6 7 1 2 4 8 9 5 10 11 3 6 12 13 7 14 15 1 2 4 8 16 17 9 18 19 5 10 20 21 11 22 23 3 6 12 24 25 13 26 27 7 14 28 29 Continued on next page 8292-021811-11 Step Angle (º ) HOME 2.81 5.63 8.44 11.25 14.06 16.88 19.69 22.50 25.31 28.13 30.94 33.75 36.56 39.38 42.19 45.00 47.81 50.63 53.44 56.25 59.06 61.88 64.69 67.50 70.31 73.13 75.94 78.75 81.56 84.38 87.19 90.00 92.81 95.63 98.44 101.25 104.06 106.88 109.69 112.50 115.31 118.13 120.94 123.75 126.56 129.38 132.19 135.00 137.81 140.63 143.44 146.25 149.06 151.88 154.69 157.50 160.31 163.13 Step Number Full 1/2 1/4 1/8 1/16 15 30 31 2 4 8 16 32 33 17 34 35 9 18 36 37 19 38 39 5 10 20 40 41 21 42 43 11 22 44 45 23 46 47 3 6 12 24 48 49 25 50 51 13 26 52 53 27 54 55 7 14 28 56 57 29 58 PWM Duty Cycle (%) 1/32 INH1/ INH2/ PHA PHB PHC PHD 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 85.8 83.1 80.3 77.3 74.1 70.7 67.2 63.4 59.6 55.6 51.4 47.1 42.8 38.3 33.7 29.0 24.3 19.5 14.7 9.8 4.9 0.0 4.9 9.8 14.7 19.5 24.4 29.0 33.7 38.3 42.8 47.1 51.4 55.6 59.6 63.4 67.2 70.7 74.1 77.3 80.3 83.1 85.8 88.2 90.4 92.4 94.2 95.7 97.0 98.1 98.9 99.5 99.9 100 99.9 99.5 98.9 98.1 51.4 55.6 59.6 63.4 67.2 70.7 74.1 77.3 80.3 83.1 85.8 88.2 90.4 92.4 94.2 95.7 97.0 98.1 98.9 99.5 99.9 100 99.9 99.5 98.9 98.1 97.0 95.7 94.2 92.4 90.4 88.2 85.8 83.1 80.3 77.3 74.1 70.7 67.2 63.4 59.6 55.6 51.4 47.1 42.8 38.3 33.7 29.0 24.3 19.5 14.7 9.8 4.9 0.0 4.9 9.8 14.7 19.5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 Step Angle (º ) 165.94 168.75 171.56 174.38 177.19 180.00 182.81 185.63 188.44 191.25 194.06 196.88 199.69 202.50 205.31 208.13 210.94 213.75 216.56 219.38 222.19 225.00 227.81 230.63 233.44 236.25 239.06 241.88 244.69 247.50 250.31 253.13 255.94 258.75 261.56 264.38 267.19 270.00 272.81 275.63 278.44 281.25 284.06 286.88 289.69 292.50 295.31 298.13 300.95 303.75 306.56 309.38 312.19 315.00 317.81 320.63 323.44 326.25 Continued on next page 8292-021811-12 Step Number Full 1/2 1/4 1/8 PWM Duty Cycle (%) 1/16 59 15 30 60 61 31 62 63 0 0 0 0 0 1/32 INH1/ INH2/ PHA PHB PHC PHD 117 118 119 120 121 122 123 124 125 126 127 0 97.0 95.7 94.2 92.4 90.4 88.2 85.8 83.1 80.3 77.3 74.1 70.7 24.4 29.0 33.7 38.3 42.8 47.1 51.4 55.6 59.6 63.4 67.2 70.7 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Step Angle (º ) 329.06 331.88 334.69 337.50 340.31 343.13 345.95 348.75 351.56 354.38 357.19 HOME NOTE: In Table4 the PWM duty cycles are indicated for Fast Decay mode which causes INH1/ and INH2/ outputs to be chopped. In Slow Decay mode INH1/ and INH2/ outputs remain high while PHA, PHB, PHC and PHD outputs are chopped. 8292-021811-13