Agilent HMMC–3028 DC–12 GHz High Efficiency GaAs HBT MMIC Divide–by–8 Prescaler 1GC1-8008 Data Sheet Features • Wide Frequency Range: 0.2-12 GHz • High Input Power Sensitivity: On-chip pre- and post-amps -20 to +10 dBm (1–8 GHz) -15 to +10 dBm (8–10 GHz) -10 to +5 dBm (10–12 GHz) • Dual-mode Pout: (Chip Form) 0 dBm (0.5 Vp–p) @ 44 mA -6.0 dBm (0.25 Vp–p) @ 34 mA • Low Phase Noise: -153 dBc/Hz @ 100 kHz Offset • (+) or (-) Single Supply Bias Operation • Wide Bias Supply Range: 4.5 to 6.5 volt operating range • Differential I/0 with on-chip 50 Ω matching Description The HMMC-3028 GaAs HBT MMIC Prescaler offers dc to 12 GHz frequency translation for use in communications and EW systems incorporating highfrequency PLL oscillator circuits and signal-path down conversion applications. The prescaler provides a large input power sensitivity window and low phase noise. In addition to the features listed above the device offers an input disable contact pad to eliminate any self-oscillation condition. Chip Size: Chip Size Tolerance: Chip Thickness: Pad Dimensions: 1330 x 440 µm (52.4 x 17.3 mils) ± 10 µm (± 0.4 mils) 127 ± 15 µm (5.0 ± 0.6 mils) 70 x 70 µm (2.8 x 2.8 mils) Absolute Maximum Ratings1 (@ TA = 25°C, unless otherwise indicated) Symbol Parameters/Conditions Min. Max. Units VCC Bias supply voltage +7 volts VEE Bias supply voltage -7 VCC - VEE Bias supply delta 0 +7 volts VDisable Pre-amp disable voltage VEE VCC volts VLogic Logic threshold voltage VCC -1.5 VCC -1.2 volts Pin(CW) CW RF input power +10 dBm VRFin DC input voltage (@ RFin or RFin ports) VCC ±0.5 volts volts TBS2 Backside operating temperature -40 +85 °C Tst Storage temperature -65 +165 °C Tmax Maximum assembly temperature (60 s max.) 310 °C Notes 1. Operation in excess of any parameter limit (except TBS) may cause permanent damage to the device. 2. MTTF > 1 x 106 hours @ TBS ≤ 85°C. Operation in excess of maximum operating temperature (TBS) will degrade MTTF. dc Specifications/Physical Properties (TA = 25°C, VCC – VEE = 5.0 volts, unless otherwise listed) Symbol Parameters/Conditions Min. Typ. Max. Units VCC – VEE Operating bias supply difference1 4.5 5.0 6.5 volts |ICC| or |IEE| Bias supply current (HIGH Output Power Configuration2: VPwrSel = VEE) 37 44 51 mA Bias supply current (LOW Output Power Configuration: VPwrSel = open) 29 34 39 mA VRFin(q) VRFout(q) Quiescent dc voltage appearing at all RF ports VLogic Nominal ECL Logic Level (VLogic contact self-bias voltage, generated on-chip) VCC VCC -1.45 VCC -1.32 volts VCC -1.25 volts Notes 1. Prescaler will operate over full specified supply voltage range, VCC or VEE not to exceed limits specified in Absolute Maximum Ratings section. 2. High output power configuration: Pout = 0 dBm (Vout = 0.5 Vp-p). Low output power configuration: Pout = -6.0 dBm (Vout = 0.25 Vp-p) RF Specifications (TA = 25°C, Z0 = 50 Ω, VCC – VEE = 5.0 volts) (÷8) Symbol Parameters/Conditions Min. Typ. 12 14 ƒin(max) Maximum input frequency of operation ƒin(min) Minimum input frequency of (Pin = -10 dBm) operation1 ƒSelf-Osc. Output Self-Oscillation Frequency2 Pin @ dc, (Square-wave input) -15 > -25 +10 dBm @ ƒin = 500 MHz, (Sine-wave input) -15 > -20 +10 dBm ƒin = 1 to 8 GHz -15 > -20 +10 dBm ƒin = 8 to 10 GHz -10 > -15 +5 dBm ƒin = 10 to 12 GHz -5 > -10 -1 dBm 0.2 Max. Units GHz 0.5 1.7 GHz GHz RL Small-Signal Input/Output Return Loss (@ ƒin < 12 GHz) 15 dB S12 Small-Signal Reverse Isolation (@ ƒin < 12 GHz) 30 dB φN SSB Phase noise (@ Pin = 0 dBm, 100 kHz offset from a ƒout = 1.2 GHz Carrier) -153 dBc/Hz Jitter Input signal time variation @ zero–crossing (ƒin = 10 GHz, Pin = -10 dBm) 1 ps Tr or Tf Output edge speed (10% to 90% rise/fall time) 70 ps Notes 1. For sine-wave input signal. Prescaler will operate down to D.C. for square-wave input signal. Minimum divide frequency limited by input slew-rate. 2. Prescaler may exhibit this output signal under bias in the absence of an RF input signal. This condition may be eliminated by use of the Pre-amp Disable ( VDisable) feature, or the Differential Input de-biasing technique. 2 RF Specifications (Continued) (TA = 25°C, Z0 = 50 Ω, VCC – VEE = 5.0 volts) Symbol Parameters/Conditions High Output Power Operating Mode1 Min. Typ. Max. Pout @ ƒout < 1 GHz -2.0 0 dBM @ ƒout = 1.25 GHz -2.0 0 dBm @ ƒout = 1.5 GHz -2.25 -0.25 dBm @ ƒout < 1 GHz 0.39 0.5 volts @ ƒout = 1.25 GHz 0.39 0.5 volts @ ƒout = 1.5 GHz 0.38 0.48 volts ƒout power level appearing at RFin or RFin (@ ƒin = 10 GHz, unused RFout or RFout unterminated) -61 dBm ƒout power level appearing at RFin or RFin (@ ƒin = 10 GHz, both RFout & RFout terminated) -81 dBm Pfeedthru Power level of ƒin appearing at RFout or RFout (@ ƒin = 12 GHz, Pin= 0 dBm, referred to Pin (ƒin) -30 dBc H2 Second harmonic distortion output level (@ ƒout = 1.5 GHz, referred to Pout (ƒout)) -30 dBc |Vout(p–p)| PSpitback Units Low Output Power Operating Mode2 Pout |Vout(p–p)| PSpitback Pfeedthru H2 @ ƒout < 1 GHz -8.0 -6.0 dBm @ ƒout = 1.25 GHz -8.0 -6.0 dBm @ ƒout = 1.5 GHz -8.25 -6.25 dBm @ ƒout < 1 GHz 0.20 0.25 volts @ ƒout = 1.25 GHz 0.20 0.25 volts @ ƒout = 1.5 GHz 0.19 0.24 volts ƒout power level appearing at RFin or RFin (@ ƒin 10 GHz, unused RFout or RFout unterminated) -71 dBm ƒout power level appearing at RFin or RFin (@ ƒin = 10 GHz, both RFout & RFout terminated) -91 dBm Power level of ƒin appearing at RFout or RFout (@ ƒin = 12 GHz, Pin = 0 dBm, referred to Pin (ƒin)) -30 dBc Second harmonic distortion output level (@ ƒout = 1.5 GHz, referred to Pout (ƒout)) -35 dBc Notes 1. VPwrSel = VEE. 2. VPwrSel = Open Circuit. 3 Post Amplifier Stage Input Preamplifier Stage 2 Figure 1. Simplified Schematic Applications The HMMC-3028 is designed for use in high frequency communications, microwave instrumentation, and EW radar systems where low phase-noise PLL control circuitry or broad-band frequency translation is required. Operation The device is designed to operate when driven with either a single-ended or differential sinusoidal input signal over a 200 MHz to 12 GHz bandwidth. Below 200 MHz the prescaler input is “slew-rate” limited, requiring fast rising and falling edge speeds to properly divide. The device will operate at frequencies down to dc when driven with a square-wave. The device may be biased from either a single positive or single negative supply bias. The backside of the device is not dc connected to any dc bias point on the device. For positive supply operation VCC is nominally biased at any voltage in the +4.5 to +6.5 volt range with VEE (or VEE & VPwrSel) grounded. For negative bias operation VCC is typically grounded and a negative voltage between -4.5 to -6.5 volts is applied to VEE (or VEE & VPwrSel). 4 Several features are designed into this prescaler: 1. Dual-Output Power Feature Bonding both VEE and VPwrSel pads to either ground (positive bias mode) or the negative supply (negative bias mode), will deliver ~0 dBm [0.5 Vp–p] at the RF output port while drawing ~40 mA supply current. Eliminating the VPwrSel connection results in reduced output power and voltage swing, -6.0 dBm [0.25 Vp–p] but at a reduced current draw of ~30 mA resulting in less overall power dissipation. (NOTE: VEE must ALWAYS be bonded and VPwrSel must NEVER be biased to any potential other than VEE or open-circuited.) 2. VLogic ECL Contact Pad Under normal conditions no connection or external bias is required to this pad and it is self-biased to the on-chip ECL logic threshold voltage (VCC -1.35 V). The user can provide an external bias to this pad (1.5 to 1.2 volts less than VCC) to force the prescaler to operate at a system generated logic threshold voltage. 3. Input Disable Feature If an RF signal with sufficient signalto-noise ratio is present at the RF input, the prescaler will operate and provide a divided output equal to the input frequency divided by the divide modulus. Under certain “ideal” conditions where the input is well matched at the right input frequency, the device may “self-oscillate,” especially under small signal input powers or with only noise present at the input. This “self-oscillation” will produce an undesired output signal also known as a false trigger. By applying an external bias to the input disable contact pad (more positive than VCC -1.35 V), the input preamplifier stage is locked into either logic “high” or logic “low” preventing frequency division and any self-oscillation frequency which may be present. 4. Input dc Offset Another method used to prevent false triggers or self-oscillation conditions is to apply a 20 to 100 mV dc offset voltage between the RFin and RFin ports. This prevents noise or spurious low level signals from triggering the divider. Adding a 10 KΩ resistor between the unused RF input to a contact point at the VEE potential will result in an off- set of ≈25 mV between the RF inputs. Note however, that the input sensitivity will be reduced slightly due to the presence of this offset. Assembly Techniques Figure 3 shows the chip assembly diagram for single-ended I/O operation through 12 GHz for either positive or negative bias supply operation. In either case the supply contact to the chip must be capacitively bypassed to provide good input sensitivity and low input power feedthrough. Independent of the bias applied to the device, the backside of the chip should always be connected to both a good RF ground plane and a good thermal heat sinking region on the mounting surface. All RF ports are dc connected on-chip to the VCC contact through on-chip 50 Ω resistors. Under any bias conditions where VCC is not dc grounded, the RF ports should be ac coupled via series capacitors mounted on the thin-film substrate at each RF port. Only under bias conditions where VCC is dc grounded (as is typical for negative bias supply operation) may the RF ports be direct coupled to adjacent circuitry or in some cases, such as level shifting to subsequent stages. In the latter case the device backside may be “floated” and bias applied as the difference between VCC and VEE. 5 All bonds between the device and this bypass capacitor should be as short as possible to limit the inductance. For operation at frequencies below 1 GHz, a large value capacitor must be added to provide proper RF bypassing. Due to on-chip 50 Ω matching resistors at all four RF ports, no external termination is required on any unused RF port. However, improved “Spitback” performance (~20 dB) and input sensitivity can be achieved by terminating the unused RFout port to VCC through 50 Ω (positive supply) or to ground via a 50 Ω termination (negative supply operation). GaAs MMICs are ESD sensitive. ESD preventive measures must be employed in all aspects of storage, handling, and assembly. MMIC ESD precautions, handling considerations, die attach and bonding methods are critical factors in successful GaAs MMIC performance and reliability. Agilent application note #54, “GaAs MMIC ESD, Die Attach and Bonding Guidelines” provides basic information on these subjects. Optional dc Operating Values/Logic Levels (TA = 25°C) Function Symbol Logic Threshold1 Conditions Min (volts/mA) Typical (volts/mA) Max (volts/mA) VLogic VCC-1.5 VCC-1.35 VCC-1.2 Input Disable VDisable(High) [Disable] VLogic+0.25 VLogic VCC Input Disable VDisable(Low) [Enable] VEE VLogic VLogic-0.25 Input Disable IDisable VD > VEE+3 (VDisable-VEE -3)/500 Input Disable IDisable VD < VEE+3 0 (VDisable-VEE -3)/500 0 (VDisable-VEE -3)/500 0 Note: 1. Acceptable voltage range when applied from external source. Notes: • All dimensions in micrometers. • All Pad Dim: 70 x 70 µm (except where noted). • Tolerances: ± 10 µm • Chip Thickness: 127 ± 15 µm Figure 2. Pad locations and chip dimensions 6 Figure 3. Assembly diagrams 7 Figure 4. Typical input sensitivity window Figure 5. Typical supply current & VLogic vs. supply voltage Figure 6. Typical phase noise performance Figure 7. Typical output power vs. output frequency, ƒout (GHz) Figure 8. Typical “Spitback” power P(ƒout) appearing at RF input port 8 www.agilent.com www.agilent.com/find/emailupdates Get the latest information on the products and applications you select. For more information on Agilent Technologies’ products, applications or services, please contact your local Agilent office. The complete list is available at: www.agilent.com/find/contactus www.agilent.com/find/agilentdirect Quickly choose and use your test equipment solutions with confidence. www.agilent.com/find/open Agilent Open simplifies the process of connecting and programming test systems to help engineers design, validate and manufacture electronic products. Agilent offers open connectivity for a broad range of system-ready instruments, open industry software, PC-standard I/O and global support, which are combined to more easily integrate test system development. This data sheet contains a variety of typical and guaranteed performance data. The information supplied should not be interpreted as a complete list of circuit specifications. Customers considering the use of this, or other Agilent GaAs ICs, for their design should obtain the current production specifications from Agilent. In this data sheet the term typical refers to the 50th percentile performance. For additional information contact Agilent [email protected]. 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