OPA2822 OPA 282 2 SBOS188C – MARCH 2001 – REVISED MAY 2004 Dual, Wideband, Low-Noise Operational Amplifier FEATURES ● ● ● ● ● ● DESCRIPTION LOW INPUT NOISE VOLTAGE: 2.0nV/√Hz HIGH UNITY GAIN BANDWIDTH: 500MHz HIGH GAIN BANDWIDTH PRODUCT: 240MHz HIGH OUTPUT CURRENT: 90mA SINGLE +5V TO +12V OPERATION LOW SUPPLY CURRENT: 4.8mA/ch The OPA2822 offers very low 2.0nV/√Hz input noise in a wideband, unity-gain stable, voltage-feedback architecture. Intended for xDSL receiver applications, the OPA2822 also supports this low input noise with exceptionally low harmonic distortion, particularly in differential configurations. Adequate output current is provided to drive the potentially heavy load of a passive filter between this amplifier and the codec. Harmonic distortion for a 2VPP differential output operating from +5V to +12V supplies is ≤ –100dBc through 1MHz input frequencies. Operating on a low 4.8mA/ch supply current, the OPA2822 can satisfy all xDSL receiver requirements over a wide range of possible supply voltages—from a single +5V condition, to ±5V, up to a single +12V design. APPLICATIONS ● ● ● ● ● ● xDSL DIFFERENTIAL LINE RECEIVERS HIGH DYNAMIC RANGE ADC DRIVERS LOW NOISE PLL INTEGRATORS TRANSIMPEDANCE AMPLIFIERS PRECISION BASEBAND I/Q AMPLIFIERS ACTIVE FILTERS General-purpose applications on a single +5V supply will benefit from the high input and output voltage swing available on this reduced supply voltage. Low-cost precision integrators for PLLs will also benefit from the low voltage noise and offset voltage. Baseband I/Q receiver channels can achieve almost perfect channel match with noise and distortion to support signals through 5MHz with > 14-bit dynamic range. OPA2677 RO n:1 OPA2822 RELATED PRODUCTS xDSL Driver RO 500Ω FEATURES High Slew Rate 1kΩ SINGLES DUALS TRIPLES OPA690 OPA2690 OPA3690 R/R Input/Output OPA353 OPA2353 — 1.3nV Input Noise OPA846 OPA2686 — 1.5nV Input Noise — THS6062 — 500Ω OPA2822 500Ω 1kΩ xDSL Receiver OPA2822 500Ω Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2001-2004, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com PACKAGE/ORDERING INFORMATION(1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR OPA2822U SO-8 Surface-Mount D –40°C to +85°C OPA2822U OPA2822U Rails, 100 " " " " OPA2822U/2K5 Tape and Reel, 2500 MSOP-8 Surface-Mount DGK –40°C to +85°C D22 OPA2822E/250 Tape and Reel, 250 " " " " OPA2822E/2K5 Tape and Reel, 2500 " OPA2822E " ORDERING NUMBER TRANSPORT MEDIA, QUANTITY NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet. ABSOLUTE MAXIMUM RATINGS(1) Supply Voltage ................................................................................. ±6.5V Internal Power Dissipation ........................... See Thermal Characteristics Differential Input Voltage .................................................................. ±1.2V Input Voltage Range ............................................................................ ±VS Storage Temperature Range ......................................... –40°C to +125°C Lead Temperature (SO-8) ............................................................. +260°C Junction Temperature (TJ ) ........................................................... +150°C ESD Rating (Human Body Model) .................................................. 2000V (Machine Model) ........................................................... 200V NOTE: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. ELECTROSTATIC DISCHARGE SENSITIVITY Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Texas Instruments recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. PIN CONFIGURATION / MSOP PACKING MARKING Top View SO MSOP PACKAGE MARKING OPA2822 8 Out A 1 8 +VS –In A 2 7 Out B +In A 3 6 –In B –VS 4 5 +In B 6 5 D22 1 2 7 2 3 4 OPA2822 www.ti.com SBOS188C ELECTRICAL CHARACTERISTICS: VS = ±6V Boldface limits are tested at +25°C. RF = 402Ω, RL = 100Ω, and G = +2, (see Figure 1 for AC performance only), unless otherwise noted. OPA2822U, E TYP PARAMETER AC PERFORMANCE (see Figure 1) Small-Signal Bandwidth Gain-Bandwidth Product Bandwidth for 0.1dB Gain Flatness Peaking at a Gain of +1 Large-Signal Bandwidth Slew Rate Rise-and-Fall Time Settling Time to 0.02% 0.1% Harmonic Distortion 2nd-Harmonic 3rd-Harmonic Input Voltage Noise Input Current Noise Differential Gain Differential Phase Channel-to-Channel Crosstalk DC PERFORMANCE(4) Open-Loop Voltage Gain (AOL) Input Offset Voltage Average Offset Voltage Drift Input Bias Current Average Bias Current Drift (magnitude) Input Offset Current Average Offset Current Drift INPUT Common-Mode Input Range (CMIR)(5) Common-Mode Rejection Ratio (CMRR) Input Impedance Differential-Mode Common-Mode OUTPUT Voltage Output Swing Current Output, Sourcing Current Output, Sinking Short-Circuit Current Closed-Loop Output Impedance POWER SUPPLY Specified Operating Voltage Maximum Operating Voltage Range Max Quiescent Current Min Quiescent Current Power-Supply Rejection Ratio (–PSRR) THERMAL CHARACTERISTICS Specified Operating Range U, E Package Thermal Resistance, θJA U SO-8 E MSOP CONDITIONS +25°C G = +1, VO = 0.1VPP, RF = 0Ω G = +2, VO = 0.1VPP G = +10, VO = 0.1VPP G ≥ 20 G = +2, VO < 0.1VPP VO < 0.1VPP G = +2, VO = 2VPP G = +2, 4V Step G = +2, VO = 0.2V Step G = +2, VO = 2V Step G = +2, VO = 2V Step 400 200 24 240 16 5 27 170 1.5 35 32 G = +2, f = 1MHz, VO = 2VPP RL = 200Ω RL ≥ 500Ω RL = 200Ω RL ≥ 500Ω f > 10kHz f > 10kHz G = +2, PAL, VO = 1.4Vp, RL = 150 G = +2, PAL, VO = 1.4Vp, RL = 150 f = 1MHz, Input Referred –91 –95 –100 –105 2.0 1.6 0.02 0.03 –95 VO = 0V, RL = 100Ω VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V MIN/MAX OVER TEMPERATURE +25°C(1) 0°C to 70°C(2) –40°C to +85°C(2) 120 15 150 110 13 130 105 12 125 110 105 100 –88 –91 –95 –99 2.2 2.0 –87 –90 –92 –96 2.3 2.1 85 MIN/ TEST MAX LEVEL(3) MHz MHz MHz MHz MHz dB MHz V/µs ns ns ns typ min min min typ typ typ min typ typ typ C B B B C C C B C C C –86 –89 –91 –95 2.5 2.3 dBc dBc dBc dBc nV/√Hz pA/√Hz % deg dBc max max max max max max typ typ typ B B B B B B C C C 82 ±1.4 5 –19 50 ±600 5 80 ±1.5 5 –21 50 ±700 5 dB mV µV/°C µA nA/°C nA nA/°C min max max max max max max A A B A B A B ±4.4 82 ±4.4 80 V dB min min A A kΩ || pF MΩ || pF typ typ C C V V mA mA mA Ω min min min min typ typ A A A A C C V V mA mA dB typ max max min min C A A A A –40 to +85 °C typ C 125 150 °C/W °C/W typ typ C C 100 ±0.2 ±1.2 –9 –18 ±100 ±400 VCM = ±1V ±4.8 110 ±4.5 VCM = 0 VCM = 0 18 0.6 7 1 No Load 100Ω Load VO = 0, Linear Operation VO = 0, Linear Operation Output Shorted to Ground G = +2, f = 100kHz ±4.9 ±4.7 +150 –150 220 0.01 ±6 VS = ±6V, both channels VS = ±6V, both channels Input Referred UNITS 9.6 9.6 95 85 ±4.7 ±4.5 +90 –90 ±6.3 11.8 8.2 85 ±4.6 ±4.4 +85 –85 ±4.6 ±4.4 +80 –80 ±6.3 11.9 8.1 82 ±6.3 12.0 8.0 80 Junction-to-Ambient NOTES: (1) Junction temperature = ambient for +25°C tested specifications. (2) Junction temperature = ambient at low temperature limit: junction temperature = ambient +23°C at high temperature limit for over temperature tested specifications. (3) Test Levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive-out-of node. VCM is the input common-mode voltage. (5) Tested < 3dB below minimum CMRR specification at ± CMIR limits. OPA2822 SBOS188C www.ti.com 3 ELECTRICAL CHARACTERISTICS: VS = +5V Boldface limits are tested at +25°C. RF = 402Ω, RL = 100Ω to VS / 2, and G = +2, (see Figure 3 for AC performance only), unless otherwise noted. OPA2822U, E TYP +25°C(1) 0°C to 70°C(2) –40°C to +85°C(2) 105 13 130 102 11 110 100 10 105 90 2.7 85 3.2 80 3.3 –85 –87 –99 –103 2.1 1.5 –82 –83 –94 –98 2.3 1.9 –81 –82 –91 –95 2.4 2.0 90 ±0.3 ±1.3 81 –8 –16 ±100 ±400 VCM = +2.5V 1.2 3.8 110 1.5 3.5 85 VCM = +2.5V VCM = +2.5V 15 1 5 1.3 No Load RL = 100Ω to 2.5V No Load RL = 100Ω to 2.5V 3.9 3.7 1.3 1.4 +150 –150 200 0.01 CONDITIONS +25°C G = +1, VO = 0.1VPP, RF = 0Ω G = +2, VO = 0.1VPP G = +10, VO = 0.1VPP G > 20 VO < 0.1VPP G = +2, VO = 2VPP G = +2, 2V Step G = +2, VO = 0.2V Step G = +2, VO = 2V Step G = +2, VO = 2V Step 350 180 20 200 6 20 120 2.0 40 38 Input Voltage Noise Input Current Noise G = +2, f = 1MHz, VO = 2VPP RL = 200Ω to VS /2 RL = 500Ω to VS /2 RL = 100Ω to VS /2 RL = 1500Ω to VS /2 f > 1MHz f > 1MHz DC PERFORMANCE(4) Open-Loop Voltage Gain Input Offset Voltage Average Offset Voltage Drift Input Bias Current Average Bias Current Drift Input Offset Current Average Offset Current Drift VO = 0V, RL = 200Ω to 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V PARAMETER AC PERFORMANCE (see Figure 3) Small-Signal Bandwidth Gain-Bandwidth Product Peaking at a Gain of +1 Large-Signal Bandwidth Slew Rate Rise-and-Fall Time Settling Time to 0.02% 0.1% Harmonic Distortion 2nd-Harmonic 3rd-Harmonic INPUT Least Positive Input Voltage Most Positive Input Voltage Common-Mode Rejection Ratio (CMRR) Input Impedance Differential-Mode Common-Mode OUTPUT Most Positive Output Voltage Least Positive Output Voltage Current Output, Sourcing Current Output, Sinking Short-Circuit Current Closed-Loop Output Impedance POWER SUPPLY Specified Single-Supply Operating Voltage Maximum Single-Supply Operating Voltage Max Quiescent Current Min Quiescent Current Power-Supply Rejection Ratio THERMAL CHARACTERISTICS Specified Operating Range U, E Package Thermal Resistance, θJA U SO-8 E MSOP MIN/MAX OVER TEMPERATURE Output Shorted to Either Supply G = +1, f = 100kHz MHz MHz MHz MHz dB MHz V/µs ns ns ns typ min min min typ typ min max typ typ C B B B C C B B C C –80 –81 –90 –94 2.6 2.1 dBc dBc dBc dBc nV/√Hz pA/√Hz max max max max max max B B B B B B 78 ±1.5 5.5 –19 50 ±600 5 76 ±1.6 5.5 –20 50 ±700 5 dB mV µV/°C µA nA/°C nA nA/°C min max max max max max max A A B A B A B 1.6 3.4 82 1.65 3.35 80 V V dB min max min A A A kΩ || pF MΩ || pF typ typ C C V V V V mA mA mA Ω min min min min min min typ typ A A A A A A C C V V mA mA dB typ max max min typ C A A A C –40 to +85 °C typ C 125 150 °C/W °C/W typ typ C C 3.8 3.5 1.4 1.5 +90 –90 3.6 3.4 1.5 1.6 +85 –85 3.5 3.35 1.55 1.65 +80 –80 12.6 10 7.2 12.6 10.2 7.0 12.6 10.4 6.9 5 VS = +5V, both channels VS = +5V, both channels Input Referred MIN/ TEST MAX LEVEL(3) UNITS 8 8 90 Junction-to-Ambient NOTES: (1) Junction temperature = ambient for +25°C tested specifications. (2) Junction temperature = ambient at low temperature limit: junction temperature = ambient +23°C at high temperature limit for over temperature tested specifications. (3) Test Levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive-out-of node. VCM is the input common-mode voltage. 4 OPA2822 www.ti.com SBOS188C TYPICAL CHARACTERISTICS: VS = ±6V TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. NONINVERTING SMALL-SIGNAL FREQUENCY RESPONSE 3 6 G = +1 RF = 0Ω VO = 0.1VPP –3 G = +2 –6 –9 G = +5 –12 –15 G = +10 –18 –6 G = –5 –9 –12 G = –10 –15 See Figure 2 –24 0.5 1 10 100 500 0.5 1 10 Frequency (MHz) NONINVERTING LARGE-SIGNAL FREQUENCY RESPONSE INVERTING LARGE-SIGNAL FREQUENCY RESPONSE G = +2 6 VO = 0.1VPP 0 3 –3 Gain (dB) VO = 0.5VPP 0 VO = 1VPP –3 –6 VO = 2VPP 500 VO = 0.1VPP G = –1 RF = 604Ω 3 6 –9 VO = 0.5VPP –6 VO = 1VPP –9 –12 VO = 2VPP –15 –18 –12 –21 See Figure 1 0.5 1 See Figure 2 –24 10 100 0.5 500 1 10 NONINVERTING PULSE RESPONSE Large-Signal Right Scale 200 1.5 1.0 100 0.5 Small-Signal Left Scale 0 0 –100 –0.5 –200 –1.0 –300 –1.5 See Figure 1 –400 400 Small-Signal Output Voltage (100mv/div) G = +2 300 –2.0 Time (20ns/div) 2.0 G = –1 300 1.5 200 1.0 100 0.5 0 0 Small-Signal Left Scale –100 –0.5 –200 –1.0 Large-Signal Right Scale –300 –1.5 See Figure 2 –400 –2.0 Time (20ns/div) OPA2822 SBOS188C 500 INVERTING PULSE RESPONSE 2.0 Larege-Signal Output Voltage (500mv/div) 400 100 Frequency (MHz) Frequency (MHz) Small-Signal Output Voltage (100mv/div) 100 Frequency (MHz) 9 Gain (dB) –3 –21 See Figure 1 –24 –18 G = –2 –18 –21 –15 G = –1 0 Normalized Gain (dB) Normalized Gain (dB) 0 12 VO = 0.1VPP RF = 604Ω 3 Larege-Signal Output Voltage (500mv/div) 6 INVERTING SMALL-SIGNAL FREQUENCY RESPONSE www.ti.com 5 TYPICAL CHARACTERISTICS: VS = ±6V (Cont.) TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. HARMONIC DISTORTION vs LOAD RESISTANCE 1MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE –85 VO = 2VPP f = 1MHz VO = 2VPP RL = 200Ω Harmonic Distortion (dBc) Harmonic Distortion (dBc) –85 –90 2nd-Harmonic –95 –100 3rd-Harmonic See Figure 1 2nd-Harmonic –95 3rd-Harmonic –100 See Figure 1 –105 ±2.5 ±3.0 ±3.5 –105 100 –90 1k Load Resistance (Ω) –85 Harmonic Distortion (dBc) Harmonic Distortion (dBc) ±5.0 ±5.5 ±6.0 RL = 200Ω f = 1MHz VO = 2VPP RL = 200Ω –75 2nd-Harmonic –85 3rd-Harmonic –95 2nd-Harmonic –90 –95 3rd-Harmonic –100 See Figure 1 See Figure 1 –105 –105 1 0.1 10 1 10 Output Voltage Swing (VPP) Frequency (MHz) HARMONIC DISTORTION vs NONINVERTING GAIN HARMONIC DISTORTION vs INVERTING GAIN –70 –70 VO = 2VPP RL = 200Ω f = 1MHz –80 Harmonic Distortion (dBc) Harmonic Distortion (dBc) ±4.5 HARMONIC DISTORTION vs OUTPUT VOLTAGE HARMONIC DISTORTION vs FREQUENCY –65 2nd-Harmonic –90 3rd-Harmonic –100 VO = 2VPP RL = 200Ω RF = 604Ω f = 1MHz –80 2nd-Harmonic –90 3rd-Harmonic –100 See Figure 2 See Figure 1 –110 –110 1 10 1 Gain (V/V) 6 ±4.0 Supply Voltage (V) 10 Gain (V/V) OPA2822 www.ti.com SBOS188C TYPICAL CHARACTERISTICS: VS = ±6V (Cont.) TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. 2-TONE, 3rd-ORDER INTERMODULATION INTERCEPT INPUT VOLTAGE AND CURRENT NOISE DENSITY 60 10 Intercept Point (+dBm) Voltage Noise nV/√Hz Current Noise pA/√Hz 55 Voltage Noise 2nV/√Hz 45 40 PI 35 50Ω 1/2 OPA2822 102 50Ω 402Ω 103 104 105 106 1 107 10 20 Frequency (MHz) Frequency (Hz) CHANNEL-TO-CHANNEL CROSSTALK GAIN FLATNESS 0.50 Deviation from 6dB Gain (0.1dB/div) –40 Cross-Talk Input Referred (dB) PO 20 1 –50 50Ω 402Ω 30 25 1.6pA/√Hz Current Noise 50 Input Referred RL = 100Ω G = +2 –60 –70 –80 –90 –100 0.40 NG = 2 RNG = ∞ 0.30 NG = 2.5 RNG = 904Ω 0.20 0.10 G=2 Noise Gain Adjusted 0.00 –0.10 NG = 3.0 RNG = 452Ω –0.20 –0.30 NG = 3.5 RNG = 301Ω –0.40 –0.50 0.1 1 10 100 500 0 See Figure 12 50 Frequency (MHz) Normalized Gain to Capacitive Load (dB) RS (Ω) 100 10 For Maximally Flat Response, See Figure 12 10 100 200 9 6 CL = 10pF CL = 100pF 3 CL = 22pF VI 0 RS 1/2 OPA2822 –3 VO CL CL = 47pF 1kΩ 402Ω –6 1kΩ is optional. 402Ω –9 –12 1 1k 10 100 500 Frequency (MHz) Capacitive Load (pF) OPA2822 SBOS188C 150 FREQUENCY RESPONSE vs CAPACITIVE LOAD RECOMMENDED RS vs CAPACITIVE LOAD 1000 1 100 Frequency (MHz) www.ti.com 7 TYPICAL CHARACTERISTICS: VS = ±6V (Cont.) TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. OPEN-LOOP GAIN AND PHASE CMRR AND PSRR vs FREQUENCY CMRR +PSRR 100 100 –PSRR 80 60 40 –30 20 log(AOL) 80 –60 ∠ AOL 60 20 104 105 106 107 40 –120 20 –150 0 –180 –210 102 108 103 104 106 107 108 Frequency (Hz) OUTPUT VOLTAGE AND CURRENT LIMITATIONS CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY 6 1W Internal 5 Power Limit 4 Single-Channel RL = 100Ω 3 2 1 0 –1 –2 –3 –4 –5 –6 –200 –150 –100 –50 0 109 10 RL = 25Ω RL = 50Ω 1/2 OPA2822 1 ZO 402Ω 10 402Ω 0.1 0.01 1W Internal Power Limit Single-Channel 0.001 50 100 150 0.1 200 1 100 INVERTING OVERDRIVE RECOVERY NONINVERTING OVERDRIVE RECOVERY 8 8 4 RL = 100Ω G = +2 See Figure 1 2 Output Left Scale 1 0 0 –2 –1 –4 –2 Input Voltage 4 Input/Output Voltage 3 2 10 Frequency (MHz) IO (mA) 6 105 Frequency (Hz) Output Impedance (Ω) 103 Output Voltage –90 –20 0 VO (V) 0 RL = 100Ω 6 RF = 604Ω G = –1 4 Output 2 0 –2 –4 Input –6 Input Right Scale –8 –3 –6 –4 –8 Time (40ns/div) 8 See Figure 2 Time (40ns/div) OPA2822 www.ti.com SBOS188C Open-Loop Phase (30°/div) 120 Open-Loop Gain (dB) Common-Mode Rejection Ratio (dB) Power-Supply Rejection Ratio (dB) 120 TYPICAL CHARACTERISTICS: VS = ±6V (Cont.) TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. SETTLING TIME VIDEO DIFFERENTIAL GAIN/DIFFERENTIAL PHASE 0.25 RL = 100Ω VO = 2V step G = +2 0.25 Differential Phase (°) 0.15 0.10 0.05 0 –0.05 –0.10 Differential Gain (%) 0.20 –0.15 0.15 dP 0.10 0.05 –0.20 dG See Figure 1 0 –0.25 0 5 10 15 20 25 30 35 40 45 50 55 60 1 3 6 7 SUPPLY AND OUTPUT CURRENT vs TEMPERATURE 0 10x Input Offset Current –0.5 –5 Input Bias Current –1 –25 0 25 50 75 100 Output Current (25mA/div) Input Bias and Offset Current (µA) 5 0 12 Sourcing Output Current Left Scale 225 200 175 9 Supply Current (both channels) Right Scale 150 Sinking Output Current Left Scale 125 8 7 Current Limited Output –10 125 100 6 –50 –25 0 25 50 75 100 125 Ambient Temperature (°C) COMMON-MODE AND DIFFERENTIAL INPUT IMPEDANCE COMMON-MODE INPUT RANGE AND OUTPUT SWING vs SUPPLY VOLTAGE Input Impedance Magnitude 20Log (Ω) 6 Positive Input and Output 2 0 –2 Negative Input and Output –4 11 10 Ambient Temperature (°C) 4 8 250 Input Offset Voltage Voltage Range (V) 5 TYPICAL DC DRIFT OVER TEMPERATURE 0.5 –6 4 Video Loads 10 –50 2 Time (ns) 1 Input Offset Voltage (mV) 0.20 107 Common-Mode 106 105 Differential 104 103 102 ±2 ±3 ±4 ±5 ±6 103 105 106 107 108 Frequency (Hz) Supply Voltage (±V) OPA2822 SBOS188C 104 www.ti.com 9 Supply Current (1mA/div) Percent of Final Value (%) 0.30 TYPICAL CHARACTERISTICS: VS = ±6V TA = +25°C, Differential Gain = 2, RF = 604Ω, and RL = 400Ω, unless otherwise noted. DIFFERENITAL PERFORMANCE TEST CIRCUIT DIFFERENTIAL SMALL-SIGNAL FREQUENCY RESPONSE 6 +6V VO = 200mVPP 3 GD = +1 GD = +2 GD = 604Ω RG 1/2 OPA2822 RG VI Normalized Gain (dB) 0 604Ω RG RL 604Ω VO –3 GD = +5 –6 –9 GD = +10 –12 –15 –18 –21 –24 1/2 OPA2822 0.5 1 10 100 500 Frequency (MHz) –6V DIFFERENTIAL LARGE-SIGNAL FREQUENCY RESPONSE DIFFERENTIAL DISTORTION vs LOAD RESISTANCE 12 6 VO = 1VPP Gain (dB) 3 0 –3 VO = 2VPP –6 –9 VO = 5VPP –12 Harmonic Distortion (dBc) GD = 2 RL = 400Ω 9 –85 VO = 200mVPP VO = 4VPP GD = 2 f = 1MHz –90 3rd-Harmonic –95 2nd-Harmonic –100 –15 –18 –105 0.5 1 10 100 500 10 100 Frequency (MHz) DIFFERENTIAL DISTORTION vs FREQUENCY VO = 4VPP GD = 2 RL = 400Ω –75 DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE –95 3rd-Harmonic Harmonic Distortion (dBc) Harmonic Distortion (dBc) –65 –85 2nd-Harmonic –95 –105 f = 1MHz GD = 2 RL = 400Ω –100 3rd-Harmonic –105 2nd-Harmonic –110 –115 1 10 1 Frequency (MHz) 10 1k Load Resistance (Ω) 10 Differential Output Voltage Swing (VPP) OPA2822 www.ti.com SBOS188C TYPICAL CHARACTERISTICS: VS = +5V TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. NONINVERTING SMALL-SIGNAL FREQUENCY RESPONSE 6 VO = 0.1VPP 6 G = +1 RF = 0Ω 0 G = +2 –3 –6 G = +5 –9 –12 G = +10 –15 –3 –6 G = –5 –9 –12 G = –10 –15 –18 –18 –21 –21 See Figure 3 0.5 1 See Figure 4 –24 –24 10 100 500 0.5 1 10 Frequency (MHz) 1.0 0.1 0.5 Small-Signal Left Scale 0 0 –0.1 –0.5 –0.2 –1.0 –0.3 –1.5 See Figure 3 –0.4 Small-Signal Output Voltage (100mv/div) 0.2 1.5 Large-Signal Output Voltage (500mv/div) Small-Signal Output Voltage (100mv/div) Large-Signal Right Scale –2.0 0.4 2.0 0.3 1.5 0.2 1.0 0.1 0.5 0 0 Small-Signal Left Scale –0.1 –0.5 –0.2 –1.0 Large-Signal Right Scale –0.3 –2.0 Time (20ns/div) FREQUENCY RESPONSE vs CAPACITIVE LOAD RECOMMENDED RS vs CAPACITIVE LOAD Normalized Gain to Capacitive Load (dB) 1000 100 10 For Maximally Flat Response, See Figure 12 1 100 9 CL = 10pF 6 +5V 0 VI 0.01µF CL = 47pF 804Ω 804Ω –3 CL = 22pF CL = 100pF 3 1/2 OPA2822 RS VO CL 1kΩ 402Ω –6 1kΩ is optional. 402Ω –9 0.01µF –12 1 1000 10 100 500 Frequency (MHz) Capacitive Load (pF) OPA2822 SBOS188C –1.5 See Figure 4 –0.4 Time (20ns/div) 10 500 INVERTING PULSE RESPONSE 2.0 0.3 100 Frequency (MHz) NONINVERTING PULSE RESPONSE 0.4 Input Impedance Magnitude 20Log (Ω) G = –2 0 Normalized Gain (dB) Normalized Gain (dB) 3 G = –1 VO = 0.1VPP RF = 604Ω 3 Large-Signal Output Voltage (500mv/div) 9 INVERTING SMALL-SIGNAL FREQUENCY RESPONSE www.ti.com 11 TYPICAL CHARACTERISTICS: VS = +5V (Cont.) TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. HARMONIC DISTORTION vs LOAD RESISTANCE HARMONIC DISTORTION vs FREQUENCY –60 VO = 2VPP f = 1MHz –80 VO = 2VPP RL = 200Ω Harmonic Distortion (dBc) 2nd-Harmonic –85 –90 –95 3rd-Harmonic –100 –70 2nd-Harmonic –80 –90 3rd-Harmonic See Figure 3 See Figure 3 –105 –100 100 1 10 Load Resistance (Ω) Frequency (MHz) HARMONIC DISTORTION vs OUTPUT VOLTAGE 2-TONE, 3rd-ORDER INTERMODULATION INTERCEPT 50 RL = 200Ω f = 1MHz 2nd-Harmonic 45 Intercept Point (+dBm) Harmonic Distortion (dBc) –85 1k –90 –95 3rd-Harmonic –100 +5V 40 35 PI 0.1µF 57.6Ω 50Ω 1/2 OPA2822 PO 50Ω 402Ω 25 402Ω 0.1µF 20 –105 0.1 1 1 10 Frequency (MHz) TYPICAL DC DRIFT OVER TEMPERATURE SUPPLY AND OUTPUT CURRENT vs TEMPERATURE Input Offset Voltage 0 0 10x Input Offset Current –0.5 –5 Input Bias Current –1 –25 0 25 50 75 100 Output Current (25mA/div) 5 Input Bias and Offset Current (µA) 0.5 20 200 10 –50 10 Output Voltage Swing (VPP) 1 Input Offset Voltage (mV) 804Ω 30 See Figure 3 –10 125 12 11 Sourcing Output Current Left Scale 175 Supply Current (both channels) Right Scale 150 10 9 8 125 Sinking Output Current Left Scale 7 Current Limited Output 100 –50 –25 0 25 50 75 100 6 125 Ambient Temperature (°C) Ambient Temperature (°C) 12 804Ω Supply Current (1mA/div) Harmonic Distortion (dBc) –75 OPA2822 www.ti.com SBOS188C TYPICAL CHARACTERISTICS: VS = +5V TA = +25°C, Differential Gain = +2, RF = 604Ω, and RL = 400Ω, unless otherwise noted. DIFFERENITAL PERFORMANCE TEST CIRCUIT DIFFERENTIAL SMALL-SIGNAL FREQUENCY RESPONSE 6 +5V 0.01µF VI 0.01µF 1/2 OPA2822 RG 0 GD = 604Ω RG Normalized Gain (dB) +2.5V 604Ω RL 604Ω RG GD = +1 VO = 200mVPP RL = 400Ω 3 VO GD = +2 –3 –6 GD = +5 –9 –12 GD = +10 –15 –18 –21 –24 1/2 OPA2822 0.5 +2.5V 10 100 500 Frequency (MHz) DIFFERENTIAL LARGE-SIGNAL FREQUENCY RESPONSE DIFFERENTIAL DISTORTION vs LOAD RESISTANCE –85 12 VO = 4VPP GD = 2 f = 1MHz 6 Harmonic Distortion (dBc) VO = 200mVPP 9 VO = 1VPP 3 Gain (dB) 1 0 –3 VO = 2VPP –6 –9 VO = 5VPP –12 –90 3rd-Harmonic –95 2nd-Harmonic –100 –15 –105 –18 0.5 1 10 100 10 500 100 DIFFERENTIAL DISTORTION vs FREQUENCY DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE –55 –95 f = 1MHz VO = 2VPP –65 Harmonic Distortion (dBc) Harmonic Distortion (dBc) 1k Resistance (Ω) Frequency (MHz) –75 3rd-Harmonic –85 –95 2nd-Harmonic –105 –100 –105 2nd-Harmonic –110 3rd-Harmonic –115 –115 1 10 1 Frequency (MHz) OPA2822 SBOS188C 10 Output Voltage Swing (VPP) www.ti.com 13 APPLICATIONS INFORMATION WIDEBAND NONINVERTING OPERATION The OPA2822 provides a unique combination of features in a wideband dual, unity-gain stable, voltage-feedback amplifier to support the extremely high dynamic range requirements of emerging communications technologies. Combining low 2nV/√Hz input voltage noise with harmonic distortion performance that can exceed 100dBc SFDR through 2MHz, the OPA2822 provides the highest dynamic range input interface for emerging high speed 14-bit (and higher) converters. To achieve this level of performance, careful attention to circuit design and board layout is required. Figure 1 shows the gain of +2 configuration used as the basis for the Electrical Characteristics table and most of the Typical Characteristics at ±6V operation. While the characteristics are given using split ±6V supplies, most of the electrical and typical characteristics also apply to a single-supply +12V design where the input and output operating voltages are centered at the midpoint of the +12V supply. Operation at ±5V will very nearly match that shown for the ±6V operating point. Most of the reference curves were characterized using signal sources with 50Ω driving impedance, and with measurement equipment presenting a 50Ω load impedance. In Figure 1, the 50Ω shunt resistor at the VI terminal matches the source impedance of the test signal generator, while the 50Ω series resistor at the VO terminal provides a matching resistor for the measurement equipment load. Generally, data sheet voltage swing specifications are at the output pin (VO in Figure 1), while output power (dBm) specifications are at the matched 50Ω load. The total 100Ω load at the output, combined with the total 804Ω total feedback network load for the noninverting configuration of Figure 1, presents the OPA2822 with an effective output load of 89Ω. While this is a good load value for frequency response measurements, distortion will improve rapidly with lighter output loads. Keeping the same feedback network and increasing the load to 200Ω will result in a total load of 160Ω for the distortion performance reported in the Electrical Characteristics table. For higher gains, the feedback resistor (RF) was held at 402Ω and the gain resistor (RG) adjusted to develop the Typical Characteristics. Voltage-feedback op amps, unlike current-feedback designs, can use a wide range of resistor values to set their gains. A lownoise part like the OPA2822 will deliver low total output noise only if the resistor values are kept relatively low. For the circuit of Figure 1, the resistors contribute an input-referred voltage noise component of 1.8nV/√Hz, which is approaching the value of the amplifier’s intrinsic 2nV/√Hz. For a more complete description of the feedback network’s impact on noise, see the Setting Resistor Values to Minimize Noise section later in this data sheet. In general, the parallel combination of RF and RG should be < 300Ω to retain the low-noise performance of the OPA2822. However, setting these values too low can impair distortion performance due to output loading, as shown in the distortion versus load data in the Typical Characteristics. WIDEBAND INVERTING OPERATION Operating the OPA2822 as an inverting amplifier has several benefits and is particularly appropriate as part of the hybrid design in an xDSL receiver application. Figure 2 shows the inverting gain of –1 circuit used as the basis of the inverting mode Typical Characteristics. +5V +VS 0.1µF 0.1µF 50Ω Source RG 604Ω RS 309Ω 6.8µF + 1/2 OPA2822 VO VI 0.1µF +5V +VS 6.8µF + 6.8µF FIGURE 2. Inverting G = –1 Specification and Test Circuit. VI 1/2 OPA2822 VO 50Ω 50Ω Load RF 402Ω RG 402Ω 0.1µF + 6.8µF –VS –5V FIGURE 1. Noninverting G = +2 Specification and Test Circuit. 14 + –VS –5V 50Ω Source 50Ω 50Ω Load RF 604Ω RM 54.9Ω 0.1µF 50Ω In the inverting case, only the RF element of the feedback network appears as part of the total output load in parallel with the actual load. For the 100Ω load used in the Typical Characteristics, this gives an effective load of 86Ω in this inverting configuration. Gain resistor RG is set to achieve the desired inverting gain (in this case 604Ω for a gain of –1), while an additional input matching resistor (RM) can be used to set the total input impedance equal to the source if desired. In this case, RM = 54.9Ω in parallel with the 604Ω gain setting resistor yields a matched input impedance of 50Ω. RM is needed only when the input must be matched to a source impedance, as in the characterization testing done using the circuit of Figure 2. OPA2822 www.ti.com SBOS188C To take full advantage of the OPA2822’s excellent DC input accuracy, the total DC impedance seen at of each of the input terminals must be matched to get bias current cancellation. For the circuit of Figure 2, this requires the grounded 309Ω resistor on the noninverting input. The calculation for this resistor value assumes a DC-coupled 50Ω source impedance along with RG and RM. While this resistor will provide cancellation for the input bias current, it must be well decoupled (0.1µF in Figure 2) to filter the noise contribution of the resistor itself and of the amplifier’s input current noise. As the required RG resistor approaches 50Ω at higher gains, the bandwidth for the circuit in Figure 2 will far exceed the bandwidth at the same gain magnitude for the noninverting circuit of Figure 1. This occurs due to the lower noise gain for the circuit of Figure 2 when the 50Ω source impedance is included in the analysis. For example, at a signal gain of –12 (RG = 50Ω, RM = open, RF = 604Ω) the noise gain for the circuit of Figure 2 will be 1 + 604Ω/(50Ω + 50Ω) = 7, due to the addition of the 50Ω source in the noise gain equation. This will give considerably higher bandwidth than the noninverting gain of +12. SINGLE-SUPPLY NONINVERTING OPERATION The key requirement of broadband single-supply operation is to maintain input and output signal swings within the usable voltage range at both input and output. The circuit of Figure 3 establishes an input midpoint bias using a simple resistive divider from the +5V supply (two 804Ω resistors). These two resistors are selected to provide DC bias current cancellation because their parallel combination matches the DC impedance looking out of the inverting node, which equals RF. The gain setting resistor is not part of the DC impedance looking out of the inverting node, due to the blocking capacitor in series with it. The input signal is then AC-coupled into the midpoint voltage bias. The input impedance matching resistor (57.6Ω) is selected for testing to give a 50Ω input match (at high frequencies) when the parallel combination of the biasing divider network is included. The gain resistor (RG) is ACcoupled, giving a DC gain of +1. This centers the output also at the input midpoint bias voltage (VS/2). While this circuit is shown using a +5V supply, this same circuit may be applied for single-supply operation as high as +12V. SINGLE-SUPPLY INVERTING OPERATION For those single +5V Typical Characteristics that require inverting gain of –1 operation, the test circuit in Figure 4 was used. The OPA2822 can also support single +5V operation with its exceptional input and output voltage swing capability. While not a rail-to-rail input/output design, both inputs and outputs can swing to within 1.2V of either supply rail. For a single amplifier channel, this gives a very clean 2VPP output capability on a single +5V supply, or 4VPP output for a differential configuration using both channels together. Figure 3 shows the AC-coupled noninverting gain of +2 used as the basis of the Electrical Characteristics table and most of the Typical Characteristics for single +5V supply operation. +5V +VS 0.1µF RB 1.21kΩ VS/2 0.1µF 50Ω Source 1/2 RB 1.21kΩ OPA2822 RG 0.1µF 604Ω VO + 6.8µF RL 100Ω VS/2 RF 604Ω VI +5V +VS 0.1µF VI 57.6Ω RM 54.9Ω 0.1µF RB 804Ω VS/2 RB 804Ω 1/2 OPA2822 VO + 6.8µF FIGURE 4. AC-Coupled, G = –1, Single-Supply Operation: Specification and Test Circuit. RL 100Ω VS/2 RF 402Ω RG 402Ω 0.1µF FIGURE 3. AC-Coupled, G = +2, Single-Supply Operation: Specification and Test Circuit. As with the circuit of Figure 2, the feedback resistor (RF) has been increased to 604Ω to reduce the loading effect it has in parallel with the 100Ω actual load. The noninverting input is biased at VS/2 (2.5V in this case) using the two 1.21kΩ resistors for RB. The parallel combination of these two resistors (605Ω) provides input bias current cancellation by matching the DC impedance looking out of the inverting input node. The noninverting input bias is also well decoupled using the 0.1µF capacitor to both reduce both power-supply noise and the resistor and bias current noise at this input. OPA2822 SBOS188C www.ti.com 15 The gain resistor (RG) is set to equal the feedback resistor (RF) at 604Ω to achieve the desired gain of –1 from VI to VO. A DC blocking capacitor is included in series with RG to reduce the DC gain for the noninverting input bias and offset voltages to +1. This places the VS/2 bias voltage at the output pin and reduces the output DC offset error terms. The signal input impedance is matched to the 50Ω source using the additional RM resistor set to 54.9Ω. At higher frequencies, the parallel combination of RM and RG provides the input impedance match at 50Ω. This is principally used for test and characterization purposes—system applications do not necessarily require this input impedance match, particularly if the source device is physically near the OPA2822 and/or does not require a 50Ω input impedance match. At higher gains, the signal source impedance will start to materially impact the apparent noise gain (and hence, bandwidth) of the OPA2822. ADSL RECEIVE AMPLIFIER One of the principal applications for the OPA2822 is as a lowpower, low-noise receive amplifier in ADSL modem designs. Applications ranging from single +5V, ±5V, and up to single +12V supplies can be well supported by the OPA2822. For higher supplies, consider the dual, low-noise THS6062 ADSL receive amplifier that can support up to ±15V supplies. Figure 5 shows a typical ADSL receiver design where the OPA2822 is used as an inverting summing amplifier to provide both driver output signal cancellation and receive channel gain. In the circuit of Figure 5, the driver differential output voltage is shown as VD, while the receiver channel output is shown as VR. +5V 1/2 OPA2822 Driver RS The two sets of resistors, R1 and R2, are set to provide the desired gain from the transformer windings for the signal arriving on the line side of the transformer, and also to provide nominal cancellation for the driver output signal (VD) to the receiver output. Typically, the two RS resistors are set to provide impedance matching through the transformer. This is accomplished by setting RS = 0.5 • (RL/N2), where N is the turns ratio used for the line driver design. If RS is set in this fashion, and the actual twisted pair line shows the expected RL impedance value, the voltage swing produced at VD will be cut in half at the transformer input. In this case, setting R1 = 2 • R2 will achieve cancellation of the driver output signal at the output of the receiver. Essentially, the driver output voltage produces a current in R1 that is exactly matched by the current pulled out of R2 due to the attenuated and inverted version of the output signal at the transformer input. In actual practice, R1 and R2 are usually RC networks to achieve cancellation over the frequency varying line impedance. As the transformer turns ratio changes to support different line driver and supply voltage combinations, the impact of receiver amplifier noise changes. Typically, DSL systems incur a line referred noise contribution for the receiver that can be computed for the circuit of Figure 5. For example, targeting an overall gain of 1 from the line to the receiver output, and picking the input resistor R2, the remaining resistors will be set by the driver cancellation and gain requirements. With the resistor values set, a line referred noise contribution due to the OPA2822 can be computed. R1 will be set to 2x the value of R2, and the feedback resistor will be set to recover the gain loss through the transformer. Table I shows the total line referred noise floor (in dBm/Hz) using three different values for R2 over a range of transformer turns ratio (where the amplifier gain is adjusted at each turns ratio). TABLE I. Line Referred Noise dBm/Hz, Due to Receiver Op Amp. RF R2 R1 1:n RL VD Line VR R1 RS R2 RF 1/2 OPA2822 N R2 = 200 R2 = 500 R2 = 1000 1 1.5 2 2.5 3 3.5 4 4.5 5 –151.5 –149.1 –147.2 –145.6 –144.3 –143.2 –142.2 –141.3 –140.4 –150.2 –147.6 –145.6 –144.0 –142.7 –141.5 –140.5 –139.5 –138.7 –148.5 –145.8 –143.7 –142.1 –140.7 –139.5 –138.4 –137.5 –136.6 Table I shows that a lower transformer turns ratio results in reduced line referred noise, and that the resistor noise will start to degrade the noise at higher values—particularly in going from 500Ω to 1kΩ. In general, line referred noise floor due to the receiver channel will not be the limit to ADSL modem performance, if it is lower than –145dBm. –5V FIGURE 5. Example ADSL Receiver Amplifier. 16 OPA2822 www.ti.com SBOS188C ACTIVE FILTER APPLICATIONS As a low-noise, low-distortion, unity-gain stable, voltagefeedback amplifier, the OPA2822 provides an ideal building block for high-performance active filters. With two channels available, it can be used either as a cascaded 2-stage active filter or as a differential filter. Figure 6 shows a 6th-order bandpass filter cascaded with two 2nd-order Sallen-Key sections, with transmission zeroes along with a passive post filter made up of a high-pass and a low-pass section. The first amplifier provides a 2nd-order high-pass stage while the second amplifier provides the 2nd-order low-pass stage. Figure 7 shows the frequency response for this example filter. A differential active filter is shown in Figure 8. This circuit shows a single-supply, 2nd-order high-pass filter with the corner frequencies set to provide the required high-pass function for an ADSL CPE modem application. To use this circuit, the hybrid would be implemented as a passive summing circuit at the input to this filter. For +5V only ADSL designs, it is preferable to implement a portion of the filtering prior to the amplifier, thus limiting the amplitude of the uncancelled line driver signals. This type of receiver stage would typically then drive a low-pass filter prior to the codec setting the high-frequency cutoff of the ADC (Analog-toDigital Converter) input signal. Figure 9 shows the frequency response for the high-pass circuit of Figure 8. +VS +5V 365Ω 2.2µF 1/2 OPA2822 2kΩ 730Ω 1µF VS 2 VI VI 730Ω 2.2µF 1.0nF 158Ω 1.0nF 1/2 OPA2822 2.2µF 365Ω FIGURE 8. Single-Supply, 2nd-Order High-Pass Active Filter with Differential I/O. 180pF 2.1kΩ 1.3kΩ VO 2kΩ 2.2pF 140Ω 2.2µF 1/2 OPA2822 +5V 225Ω 18pF 150pF 12pF 1.8nF 1/2 OPA2822 300Ω VO 150Ω 143Ω 107Ω 66pF –5V FIGURE 6. 6th-Order Bandpass Filter. 10 3 0 0 –3 –6 Gain (dB) Gain (dB) –10 –20 –30 –9 –12 –15 –18 –40 –21 –24 –50 –27 –60 1.0E+04 1.0E+05 1.0E+06 1.0E+07 –30 1.0E+04 1.0E+08 Frequency (Hz) 1.0E+06 1.0E+07 Frequency (Hz) FIGURE 7. Frequency Response for the Filter in Figure 6. FIGURE 9. Frequency Response for the Filter in Figure 8. OPA2822 SBOS188C 1.0E+05 www.ti.com 17 HIGH DYNAMIC RANGE ADC DRIVER Numerous circuit approaches exist to provide the last stage of amplification before the ADC in high-performance applications. For very high dynamic range applications where the signal channel can be AC-coupled, the circuit shown in Figure 10 provides exceptional performance. Most very high performance ADCs > 12-bit performance require differential inputs to achieve the dynamic range. The circuit of Figure 10 converts a single-ended source to differential via a 1:2 turns ratio transformer, which then drives the inverting gain setting resistors (RG). These resistors are fixed at 100Ω to provide input matching to a 50Ω source on the transformer primary side. The gain can then be adjusted by setting the feedback resistor values. For best performance, this circuit operates with a ground centered output on ±5V supplies, although a +12V supply can also provide excellent results. Since most high-performance converters operate on a single +5V supply, the output is level shifted through an AC blocking capacitor to the common-mode input voltage (VCM) for the converter input, and then low-pass filtered prior to the input of the converter. This circuit is intended for inputs from 10kHz to 10MHz, so the output high-pass corner is set to 1.6kHz, while the low-pass cutoff is set to 20MHz. These are example cutoff frequencies; the actual filtering requirements would be set by the specific application. transformer) and then RF is set to get the desired overall gain. With these constraints (and 0Ω on the noninverting inputs), the noise figure equation simplifies considerably. 1 1 2 1 2 en + / n + (in nRS )2 2 2 α 4 NF = 10 log2 + + (1) α KTRS where RG = 1/2 n2RS n = Transformer Turns Ratio α = RF/RG en = Op Amp Input Voltage Noise in = Inverting Input Current Noise KT = 4E – 21J[T = 290°K] Gain (dB) = 20 log[nα] TABLE II. Noise Figure versus Gain with n = 2 Transformer. TOTAL GAIN (V/V) LOG GAIN (dB) REQUIRED AMPLIFIER GAIN (α) NOISE FIGURE (dB) 4 5 6 7 8 9 10 12.0 14.0 15.6 16.9 18.1 19.1 20.0 2 2.5 3 3.5 4 4.5 5 11.2 10.4 9.9 9.5 9.1 8.9 8.6 The 1:2 turns ratio transformer also provides an improvement in input referred noise figure. Equation 1 shows the Noise Figure (NF) calculation for this circuit, where RG has been constrained to provide an input match to RS (through the +5V +5V 1/2 OPA2822 RS = 50Ω RG 100Ω VI 0.1µF 80Ω VI 100pF RF 1kΩ 1:2 500Ω VO RG 100Ω VI 14-Bit ADC RF 1µF Noise Figure Defined Here VO VCM 1kΩ 0.1µF =2 RF 1/2 OPA2822 RG 80Ω VI 100pF –5V FIGURE 10. Single-Ended to Differential High Dynamic Range ADC Driver. 18 OPA2822 www.ti.com SBOS188C DESIGN-IN TOOLS ENI DEMONSTRATION BOARDS Two PC boards are available to assist in the initial evaluation of circuit performance using the OPA2822 in its two package styles. Both of these are available, free, as an unpopulated PC board delivered with descriptive documentation. The summary information for these boards is shown in Table I. Contact your sales representative or go to the TI web site (www.ti.com) to request these evaluation boards. RS PRODUCT PACKAGE OPA2822U OPA2822E SO-8 MSOP-8 DEMOPA268xU DEMOPA26xxE LITERATURE REQUEST NUMBER SBOU003 SBOU004 Computer simulation of circuit performance using SPICE is often a quick way to analyze the performance of the OPA2822 in its intended application. This is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can play a major role in circuit performance. A SPICE model for the OPA2822 is available through the TI web site (www.ti.com). These models do a good job of predicting small-signal AC and transient performance under a wide variety of operating conditions. They do not do as well in predicting the harmonic distortion characteristics. These models do not attempt to distinguish between the package types in their small-signal AC performance. OPERATING SUGGESTIONS SETTING RESISTOR VALUES TO MINIMIZE NOISE Getting the full advantage of the OPA2822’s low input noise requires careful attention to the external gain setting and DC biasing networks. The feedback resistor is part of the overall output load (which can begin to degrade distortion if set too low). With this in mind, a good starting point for design is to select the feedback resistor as low as possible (consistent with loading distortion concerns), then continue with the design, and set the other resistors as needed. To retain full performance, setting the feedback resistor in the range of 200Ω to 750Ω can provide a good start to the design. Figure 11 shows the full output noise analysis model for any op amp. The total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage terms. Equation 2 shows the general form of this output noise voltage expression using the terms shown in Figure 11. (E NI 2 ) + (IBN RS )2 + 4kTRS NG2 + (IBI RF )2 + 4kTRF NG 4kT RG RG IBI √ 4kTRF 4kT = 1.6E –20J at 290°K (2) Dividing this expression by the noise gain (NG = 1 = RF/RG) will give the total equivalent spot noise voltage referred to the noninverting input, as shown in Equation 3: I R 2 4kTRF EN = ENI 2 + (IBN RS )2 + 4kTRS + BI F + (3) NG NG Inserting high resistor values into Equation 3 can quickly dominate the total equivalent input referred voltage noise. A 250Ω source impedance on the noninverting input will add as much noise as the amplifier itself. If the noninverting input is a DC bias path (as in inverting or in some single-supply applications), it is critical to include a noise shunting capacitor with that resistor to limit the added noise impact of those resistors (see the example in Figure 2). FREQUENCY RESPONSE CONTROL Voltage-feedback op amps such as the OPA2822 exhibit decreasing closed-loop bandwidth as the signal gain is increased. In theory, this relationship is described by the Gain Bandwidth Product (GBP) shown in the Electrical Characteristics. Ideally, dividing GBP by the noninverting signal gain (also called the Noise Gain, NG) will predict the closedloop bandwidth. In practice, this principle holds true only when the phase margin approaches 90°, as it does in higher gain configurations. At low gains, most high-speed amplifiers will show a more complex response with lower phase margin and higher bandwidth than predicted by the GBP. The OPA2822 is compensated to give a slightly peaked frequency response at a gain of +2 (see the circuit in Figure 1). The 200MHz typical bandwidth at a gain of +2 far exceeds that predicted by dividing the GBP of 240MHz by a gain of 2. The bandwidth predicted by the GBP is more closely correct as the gain increases. As shown in the Typical Characteristics, at a gain of +10, the –3dB bandwidth of 24MHz matches that predicted by dividing the GBP by 10. OPA2822 SBOS188C RF √ 4kTRS FIGURE 11. Op Amp Noise Analysis Model. MACROMODELS AND APPLICATIONS SUPPORT EO = EO IBN ERS TABLE I. Demo Board Part Numbers. BOARD PART NUMBER 1/2 OPA2822 www.ti.com 19 Inverting operation offers some interesting opportunities to increase the available signal bandwidth. When the source impedance is matched by the gain resistor (Figure 10 for example), the signal gain is (1 + RF/RG) while the noise gain is (1 + RF/2RG). This reduces the noise gain almost by half, extending the signal bandwidth and increasing the loop gain. For instance, setting RF = 500Ω in Figure 10 will give a signal gain for the amplifier of 5V/V. However, including the 50Ω source impedance reflected through the 1:2 transformer will give an additional 100Ω source impedance for the noise gain analysis for each of the amplifiers. This reduces the noise gain to 1 + 500Ω/200Ω = 3.5V/V and results in an amplifier bandwidth of at least 240MHz/3.5 = 68MHz. The resistor across the two inputs, RNG, can be used to increase the noise gain while retaining the desired signal gain. This can be used either to improve flatness at low gains or to reduce the required value of RS in capacitive load driving applications. This circuit was used with RNG adjusted to produce the gain flatness curve in the Typical Characteristics. As shown in that curve, an RNG of 452Ω will give an NG of 3 giving exceptional frequency response flatness at a signal gain of +2. Equation 4 shows the calculation for RNG given a target noise gain (NG) and signal gain (G): RNG = RF + RSG NG − G (4) where RS = Total Source Impedance on the Noninverting Input [25Ω in Figure 12] One of the most demanding and yet very common load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an ADC, including additional external capacitance which may be recommended to improve ADC linearity. A high-speed, high open-loop gain amplifier like the OPA2822 can be very susceptible to decreased stability and closed-loop frequency response peaking when a capacitive load is placed directly on the output pin. When the amplifier’s open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness with low noise and distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but instead shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. G = Signal Gain [1 + (RF/RG)] NG = Noise Gain Target Using this technique to get initial frequency response flatness will significantly reduce the required series resistor value to get a flat response at the capacitive load. Using the best-case noise gain of 3 with a signal gain of 2 allows the required RS to be reduced, as shown in Figure 13. Here, the required RS versus Capacitive Load is replotted along with data from the Typical Characteristics. This demonstrates that the use of RNG = 452Ω across the inputs results in much lower required RS values to achieve a flat response. 100 NG = 2, RNG = ∞ RS (Ω) DRIVING CAPACITIVE LOADS 10 NG = 3, RNG = 452Ω The Typical Characteristics show the recommended RS versus capacitive load and the resulting frequency response at the load. For the OPA2822 operating at a gain of +2, the frequency response at the output pin is already slightly peaked without the capacitive load, requiring relatively high values of RS to flatten the response at the load. One way to reduce the required RS value is to use the noise gain adjustment circuit of Figure 12. 1 10 100 1000 Capacitive Load (pF) FIGURE 13. Required RS vs Noise Gain. DISTORTION PERFORMANCE 50Ω Source 50Ω RNG The OPA2822 is capable of delivering exceptionally low distortion through approximately 5MHz signal frequency. While principally intended to provide very low noise and distortion through the maximum ADSL frequency of 1.1MHz, the OPA2822 in a differential configuration can deliver lower than –85dBc distortions for a 4VPP swing through 5MHz. For applications requiring extremely low distortion through higher frequencies, consider higher slew rate amplifiers such as the OPA687 or OPA2681. 1/2 OPA2822 RF 402Ω RG 402Ω FIGURE 12. Noise Gain Tuning for Noninverting Circuit. 20 OPA2822 www.ti.com SBOS188C As the Typical Characteristics show, until the fundamental signal reaches very high frequencies or power levels, the limit to SFDR will be 2nd-harmonic distortion rather than the negligible 3rd-harmonic component. Focusing then on the second harmonic, increasing the load impedance improves distortion directly. However, operating differentially offers the most significant improvement in even-order distortion terms. For example, the Electrical Characteristics show that a single channel of the OPA2822, delivering 2VPP at 1MHz into a 200Ω load, will typically show a 2nd-harmonic product at –92dBc versus the 3rd-harmonic at –102dBc. Changing the configuration to a differential driver where each output still drives 2VPP results in a 4VPP total differential output into a 400Ω differential load, giving the same single-ended load of 200Ω for each amplifier. This configuration drops the 2nd-harmonic to –103dBc and the 3rd-harmonic to approximately –105dBc—an overall dynamic range improvement of more than 10dB. For general distortion analysis, remember that the total loading on the amplifier includes the feedback network; in the noninverting configuration, this is the sum of RF + RG, while in the inverting configuration this additional loading is simply RF. Increasing the output voltage swing increases the harmonic distortion directly. A 6dB increase in the output swing will generally increase the 2nd-harmonic 12dB and the 3rdharmonic 18dB. Increasing the signal gain will also generally increase both the 2nd- and 3rd-harmonics because the loop gain decreases at higher gains. Again, a 6dB increase in voltage gain will increase the 2nd-harmonic distortion by approximately 6dB. The distortion characteristic curves for the OPA2822 show little change in the 3rd-harmonic distortion versus gain. Finally, the overall distortion generally increases as the fundamental frequency increases due to the rolloff in the loop gain with frequency. Conversely, the distortion will improve going to lower frequencies, down to the dominant open-loop pole at approximately 50kHz. This will give essentially unmeasurable levels of harmonic distortion in the audio band. The OPA2822 exhibits an extremely low 3rd-order harmonic distortion. This also gives exceptionally good 2-tone 3rdorder intermodulation intercept as shown in the Typical Characteristics. This intercept curve is defined at the 50Ω load when driven through a 50Ω matching resistor to allow direct comparisons to RF MMIC devices. This network attenuates the voltage swing from the output pin to the load by 6dB. If the OPA2822 drives directly into the input of a highimpedance device, such as an ADC, this 6dB attenuation does not occur. Under these conditions, the intercept will improve by at least 6dBm. The intercept is used to predict the intermodulation spurs for two closely spaced frequencies. If the two test frequencies, f1 and f2, are specified in terms of average and delta frequency, fO = (f1 + f2)/2 and ∆F = |f2 – f1|, the two, 3rd-order, close-in spurious tones will appear at fO ± 3 • ∆F. The difference between two equal test-tone power levels and the spurious intermodulation power levels is given by ∆dBc = 2 • (IM3 – PO), where IM3 is the intercept taken from the Typical Specification and PO is the power level in dBm at the 50Ω load for either one of the two closely spaced test frequencies. For example, at 1MHz in a gain of +2 configuration, the OPA2822 exhibits an intercept of 57dBm at a matched 50Ω load. If the full envelope of the two frequencies needs to be 2VPP, each tone will be set to 4dBm. The 3rd-order intermodulation spurious tones will then be 2 • (57 – 4) = 106dBc below the test-tone power level (–102dBm). If this same 2VPP 2-tone envelope were delivered directly into the input of an ADC without the matching loss or loading of the 50Ω network, the intercept would increase to at least 63dBm. With the same signal and gain conditions but now driving directly into a light load, the spurious tones would then be at least 2 • (63 – 4) = 118dBc below the test-tone power levels. DC ACCURACY AND OFFSET CONTROL The OPA2822 can provide excellent DC signal accuracy due to its high open-loop gain, high common-mode rejection, high power-supply rejection, and low input offset voltage and bias current offset errors. To take full advantage of the low input offset voltage (±1.2mV maximum at 25°C), careful attention to input bias current cancellation is also required. The highspeed input stage for the OPA2822 has relatively high input bias current (8µA typical into the pins) but with a very close match between the two input currents, typically 100nA input offset current. The total output offset voltage may be reduced considerably by matching the source impedances looking out of the two inputs. For example, one way to add bias current cancellation to the circuit of Figure 1 would be to insert a 175Ω series resistor into the noninverting input from the 50Ω terminating resistor. If the 50Ω source resistor is DC coupled, this will increase the source impedance for the noninverting input bias current to 200Ω. Since this is now equal to the impedance looking out of the inverting input (RF || RG), the circuit will cancel the bias current effects, leaving only the offset current times the feedback resistor as a residual DC error term at the output. Using a 402Ω feedback resistor, the output DC error due to the input bias currents will now be less than 0.7µA • 402Ω = 0.28mV over the full temperature range. This is significantly lower than the contribution due to the input offset voltage. At a gain of +2, the maximum input offset voltage is 1.5mV, giving a total maximum output offset of (±3mV ± 0.28mV) = ±3.3mV over the –40°C to +85°C temperature range (for the circuit of Figure 1, including the additional 175Ω resistor at the noninverting input). THERMAL ANALYSIS The OPA2822 will not require heatsinking or airflow under most operating conditions. Maximum desired junction temperature will limit the maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed +150°C. Operating junction temperature (TJ) is given by TA + PDθJA. The total internal power dissipation (PD) is the sum of the quiescent power (PDO) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL will depend on the required OPA2822 SBOS188C www.ti.com 21 output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to half of either supply voltage (assuming equal bipolar supplies). Under this condition PDL = VS2/(4 • RL) where RL includes feedback network loading. Note that it is the power dissipated in the output stage and not in the load that determines internal power dissipation. As a worstcase example, compute the maximum TJ for the OPA2822E with both channels operating at AV = +2, RL = 100Ω, RF = 400Ω, ±VS = ±5V, and at the specified maximum TA = 85°C. PD = 10V • 11.4mA + 2 • (52)/(4 • (100 || 804)) = 255mW Maximum TJ = 85°C + 0.255W • 150°C/W = 123°C This calculation represents a worst-case combination of conditions to reach a maximum possible operating junction temperature. Under most operating conditions, the junction temperature will be far lower than the 123°C calculated here. The output current is limited in the OPA2822 to protect against damage under short-circuit conditions. This currentlimited output of approximately 220mA exceeds the rated typical output current of 150mA. The typical and minimum output current limits are set for linear operation while the maximum output shown in the Typical Characteristics is nonlinear limited performance. BOARD LAYOUT Achieving optimum performance with a high-frequency amplifier like the OPA2822 requires careful attention to board layout parasitics and external component types. Recommendations that will optimize performance include: a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability: on the noninverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. b) Minimize the distance (< 0.25") from the power-supply pins to high-frequency 0.1µF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the device pins and the decoupling capacitors. The primary power-supply connections (on pins 4 and 8) should always be decoupled with these capacitors. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequencies, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. 22 c) Careful selection and placement of external components will preserve the high-frequency performance of the OPA2822. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal film and carbon composition axially leaded resistors can also provide good high-frequency performance. Again, keep their leads and PC board trace length as short as possible. Never use wire-wound type resistors in a high-frequency application. Since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input termination resistors, should also be placed close to the package. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal film or surface-mount resistors have approximately 0.2pF in shunt with the resistor. For resistor values > 1.5kΩ, this parasitic capacitance can add a pole and/or zero below 500MHz that can effect circuit operation. Keep resistor values as low as possible consistent with parasitic load, distortion, and noise considerations. The 402Ω feedback used in the Typical Characteristics is a good starting point for design. d) Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plot of recommended RS versus capacitive load. If a long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary onboard, and in fact a higher impedance environment will improve distortion as shown in the distortion versus load plots. With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the OPA2822 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device; this total effective impedance should be set to match the trace impedance. Multiple destination devices are best handled as separate transmission lines, each with their own series and shunt terminations. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of RS vs Capacitive Load. This will not preserve signal integrity as OPA2822 www.ti.com SBOS188C well as a doubly-terminated line. If the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. +V CC External Pin e) Socketing a high-speed part like the OPA2822 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network, which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA2822 onto the board. INPUT AND ESD PROTECTION The OPA2822 is built using a very high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low due to these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Rating table. All device pins are protected with internal ESD protection diodes to the power supplies, as shown in Figure 14. –V CC FIGURE 14. Internl ESD Protection. These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (e.g. in systems with ±15V supply parts driving into the OPA2822), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible since high values degrade both noise performance and frequency response. OPA2822 SBOS188C Internal Circuitry www.ti.com 23 PACKAGE OPTION ADDENDUM www.ti.com 25-May-2004 PACKAGING INFORMATION ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY OPA2822E/250 ACTIVE VSSOP DGK 8 250 OPA2822E/2K5 ACTIVE VSSOP DGK 8 2500 OPA2822U ACTIVE SOIC D 8 100 OPA2822U/2K5 ACTIVE SOIC D 8 2500 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2004, Texas Instruments Incorporated