MOSEL V437432S24V

MOSEL VITELIC
PRELIMINARY
V437432S24V
3.3 VOLT 32M x 72 HIGH PERFORMANCE
PC133 UNBUFFERED SDRAM ECC
MODULE
Features
Description
■ 168 Pin Unbuffered ECC 33,554,432 x 72 bit
Oganization SDRAM Modules
■ Utilizes High Performance 32M x 8 SDRAM in
TSOPII-54 Packages
■ Fully PC Board Layout Compatible to INTEL’S
Rev 1.0 Module Specification
■ Single +3.3V (± 0.3V) Power Supply
■ Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
■ Auto Refresh (CBR) and Self Refresh
■ All Inputs, Outputs are LVTTL Compatible
■ 8192 Refresh Cycles every 64 ms
■ Serial Present Detect (SPD)
■ SDRAM Performance
The V437432S24V memory module is organized
33,554,432 x 72 bits in a 168 pin dual in line
memory module (DIMM). The 32M x 72 unbuffered
DIMM uses 9 Mosel-Vitelic 32M x 8 ECC SDRAM.
The x72 modules are ideal for use in high
performance computer systems where increased
memory density and fast access times are required.
Key Component Timing Parameters
-7PC
Units
tCK
Clock Frequency (max.)
143
MHz
tAC
Clock Access Time CAS Latency = 3
5.4
ns
tCK
Clock Frequency (max.)
133
MHz
tAC
Clock Access Time CAS Latency = 2
5.4
ns
■ Module Frequency vs AC Parameter
Frequency
V437432S24V
133 MHz (PC)
V437432S24V Rev. 1.0 January 2002
CL
(CAS Latency)
tRCD
tRP
tRC
Unit
2
2
2
8
CLK
1
MOSEL VITELIC
V437432S24V
Pin Configurations (Front Side/Back Side)
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VSS
I/O1
I/O2
I/O3
I/O4
VCC
I/O5
I/O6
I/O7
I/O8
I/O9
VSS
I/O10
I/O11
I/O12
I/O13
I/O14
VCC
I/O15
I/O16
CBO*
CB1*
VSS
NC
NC
VCC
WE
DQM0
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
DQM1
CS0
DU
VSS
A0
A2
A4
A6
A8
A10(AP)
BA1
VCC
VCC
CLK0
VSS
DU
CS2
DQM2
DQM3
DU
VCC
NC
NC
CB2*
CB3*
VSS
I/O17
I/O18
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
I/O19
I/O20
VCC
I/O21
NC
DU
CKE1
VSS
I/O22
I/O23
I/O24
VSS
I/O25
I/O26
I/O27
I/O28
VCC
I/O29
I/O30
I/O31
I/O32
VSS
CLK2
NC
WP
SDA
SCL
VCC
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
VSS
I/O33
I/O34
I/O35
I/O36
VCC
I/O37
I/O38
I/O39
I/O40
I/O41
VSS
I/O42
I/O43
I/O44
I/O45
I/O46
VCC
I/O47
I/O48
CB4*
CB5*
VSS
NC
NC
VCC
CAS
DQM4
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
DQM5
CS1
RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VCC
CLK1
A12
VSS
CKE0
CS3
DQM6
DQM7
DU
VCC
NC
NC
CB6*
CB7*
VSS
I/O49
I/O50
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
I/O51
I/O52
VCC
I/O53
NC
DU
NC
VSS
I/O54
I/O55
I/O56
VSS
I/O57
I/O58
I/O59
I/O60
VCC
I/O61
I/O62
I/O63
I/O64
VSS
CLK3
NC
SA0
SA1
SA2
VCC
Notes:
*
These pins are not used in this module.
Pin Names
A0–A12
Address Inputs
I/O1–I/O64
Data Inputs/Outputs
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
BA0, BA1
SDA
Serial Data OUT for Presence
Detect
SA0–A2
Serial Data IN for Presence
Detect
Read/Write Input
CB0–CB7
Check Bits (x72 Organization)
Bank Selects
NC
No Connection
CKE0, CKE1
Clock Enable
DU
Don’t Use
CS0–CS3
Chip Select
CLK0–CLK3
Clock Input
DQM0–DQM7
Data Mask
VCC
Power (+3.3 Volts)
VSS
Ground
SCL
Clock for Presence Detect
V437432S24V Rev. 1.0 January 2002
2
MOSEL VITELIC
V437432S24V
Module Part Number Information
V
4
3
74
32
S
2
4
V
X
T
G - XX
SPEED
75PC = PC133 CL3,2
75 = PC133 CL3
10PC = PC133 CL3,2
LEAD FINISH
G = GOLD
MOSEL VITELIC
MANUFACTURED
SDRAM
3.3V
COMPONENT
PACKAGE, T = TSOP
WIDTH
DEPTH
COMPONENT A=0.17u B=0.14u
REV LEVEL
168 PIN Unbuffered
DIMM X8 COMPONENT
LVTTL
REFRESH
RATE 8K
4 BANKS
Block Diagram
WE
CS0
CS
DQM WE
I/O1–I/O8
DQM0
I/O1–I/O8
D0
DQM4
I/O40–I/O33
10
CS
D1
DQM5
I/O48–I/O41
10
BC0–7
CS
DQM WE
I/O1–I/O8
CS
WE
DQM
I/O1–I/O8
CS
WE
DQM
I/O1–I/O8
CS
D4
10
DQM WE
I/O1–I/O8
DQM1
I/O9–I/O16
DQM WE
I/O1–I/O8
D5
10
DQM WE
I/O1–I/O8
CS
WE
DQM
I/O1–I/O8
CS
10
CS2
DQM2
I/O17–I/O24
D2
DQM6
I/O49–I/O56
10
CS
WE
DQM
I/O1–I/O8
DQM3
I/O25–I/O32
D3
DQM7
I/O57–I/O64
10
D7
10
E2PROM SPD (256 WORD X 8 BITS)
SCL0
SA2
SA1
SA0
CKE0
CKE: SDRAM D0-D7
RAS
RAS: SDRAM D0-D7
CAS
CAS: SDRAM D0-D7
WE
WE: SDRAM D0-D7
SDA
WP
47K
A(11:0)
BA0, BA1
CLOCK WIRING
CLOCK INPUT
LOAD
CLK0
CLK1
CLK2
CLK3
5 SDRAM
Termination
4 SDRAMS +3.3pF Cap
Termination
V437432S24V Rev. 1.0 January 2002
D6
10
VCC
VSS
3
A(11:0): SDRAM D0-D7
BA0, BA1: SDRAM D0-D7
D0-D7
C0-C17
D0-D7
MOSEL VITELIC
V437432S24V
Serial Presence Detect Information
written into the E2PROM device during module production using a serial presence detect protocol (I 2C
synchronous 2-wire bus)
A serial presence detect storage device –
– is assembled onto the module. Information about the module configuration, speed, etc. is
E2PROM
SPD-Table for 75 modules:
Hex Value
Byte Number
Function Described
SPD Entry Value
32Mx72
0
Number of SPD bytes
128
80
1
Total bytes in Serial PD
256
08
2
Memory Type
SDRAM
04
3
Number of Row Addresses (without BS bits)
13
0D
4
Number of Column Addresses (for x8 SDRAM)
10
0A
5
Number of DIMM Banks
1
01
6
Module Data Width
72
48
7
Module Data Width (continued)
0
00
8
Module Interface Levels
LVTTL
01
9
SDRAM Cycle Time at CL=3
7.5 ns
75
10
SDRAM Access Time from Clock at CL=3
5.4 ns
54
11
Dimm Config (Error Det/Corr.)
ECC
02
12
Refresh Rate/Type
Self-Refresh, 7.8µs
82
13
SDRAM width, Primary
x8
08
14
Error Checking SDRAM Data Width
n/a / x8
08
15
Minimum Clock Delay from Back to Back Random
Column Address
tccd = 1 CLK
01
16
Burst Length Supported
1, 2, 4, 8
0F
17
Number of SDRAM Banks
4
04
18
Supported CAS Latencies
CL = 2,3
06
19
CS Latencies
CS Latency = 0
01
20
WE Latencies
WL = 0
01
21
SDRAM DIMM Module Attributes
Non Buffered/Non Reg.
00
22
SDRAM Device Attributes: General
Vcc tol ± 10%
0E
23
Minimum Clock Cycle Time at CAS Latency = 2
7.5 ns
75
24
Maximum Data Access Time from Clock for CL = 2
5.4 ns
54
25
Minimum Clock Cycle Time at CL = 1
Not Supported
00
26
Maximum Data Access Time from Clock at CL = 1
Not Supported
00
27
Minimum Row Precharge Time
15 ns
0F
28
Minimum Row Active to Row Active Delay tRRD
14 ns
0E
29
Minimum RAS to CAS Delay tRCD
15 ns
0F
30
Minimum RAS Pulse Width tRAS
42 ns
2A
V437432S24V Rev. 1.0 January 2002
4
MOSEL VITELIC
V437432S24V
SPD-Table for 75 modules: (Continued)
Hex Value
Byte Number
Function Described
SPD Entry Value
32Mx72
256 MByte
40
31
Module Bank Density (Per Bank)
32
SDRAM Input Setup Time
1.5 ns
15
33
SDRAM Input Hold Time
0.8 ns
08
34
SDRAM Data Input Setup Time
1.5 ns
15
35
SDRAM Data Input Hold Time
0.8 ns
08
62-61
Superset Information (May be used in Future)
62
SPD Revision
63
Checksum for Bytes 0 - 62
64
Manufacturer’s JEDEC ID Code
65-71
72
00
Revision 2
02
0F
Mosel Vitelic
40
Manufacturer’s JEDEC ID Code (cont.)
00
Manufacturing Location
73-90
Module Part Number (ASCII)
91-92
PCB Identification Code
93
Assembly Manufacturing Date (Year)
94
Assembly Manufacturing Date (Week)
V437432S24V
95-98
Assembly Serial Number
99-125
Reserved
00
126
Intel Specification for Frequency
64
127
Reserved
AF
128+
Unused Storage Location
00
DC Characteristics
TA = 0°C to 70°C; VSS = 0 V; VDD, VDDQ = 3.3V ± 0.3V
Limit Values
Symbol
Parameter
Min.
Max.
Unit
VIH
Input High Voltage
2.0
VCC +0.3
V
V IL
Input Low Voltage
–0.5
0.8
V
V OH
Output High Voltage (IOUT = –4.0 mA)
2.4
—
V
V OL
Output Low Voltage (IOUT = 4.0 mA)
—
0.4
V
II(L)
Input Leakage Current, any input
(0 V < VIN < 3.6 V, all other inputs = 0V)
–10
10
µA
IO(L)
Output leakage current
(DQ is disabled, 0V < VOUT < V CC)
–10
10
µA
V437432S24V Rev. 1.0 January 2002
5
MOSEL VITELIC
V437432S24V
Capacitance
TA = 0°C to 70°C; VDD = 3.3V ± 0.3V, f = 1 MHz
Symbol
Parameter
Limit Values
Unit
CI1
Input Capacitance (A0 to A11, RAS, CAS, WE)
85
pF
CI2
Input Capacitance (CS0-CS3)
30
pF
CICL
Input Capacitance (CLK0-CLK3)
22
pF
CI3
Input Capacitance (CKE0, CKE1)
50
pF
CI4
Input Capacitance (DQM0-DQM7)
20
pF
CIO
Input/Output Capacitance (I/O1-I/064)
20
pF
CSC
Input Capacitance (SCL, SA0-2)
8
pF
CSD
Input/Output Capacitance
18
pF
Absolute Maximum Ratings
Parameter
Max.
Units
Voltage on VDD Supply Relative to V SS
-1 to 4.6
V
Voltage on Input Relative to VSS
-1 to 4.6
V
Operating Temperature
0 to +70
°C
-55 to 125
°C
7
W
Storage Temperature
Power Dissipation
V437432S24V Rev. 1.0 January 2002
6
MOSEL VITELIC
V437432S24V
Standby and Refresh Currents1
TA = 0°C to 70°C, VCC = 3.3V ± 0.3V
Symbol Parameter
Test Conditions
32M x 72
Unit
Note
ICC1
Operating Current
Burst length = 4, CL = 3
tRC> = tRC(min),
tCK> = tCK(min), IO = 0 mA
2 Bank Interleave Operation
2070
mA
1,2
ICC2P
Precharged Standby Current in Power
Down Mode
CKE< = VIL(max), tCK> = tCK(min)
18
mA
ICC2N
Precharged Standby Current in
Non-Power Down Mode
CKE> = VIH(min), tCK> = tCK(min), Input
changed once in 3 cycles
360
mA
ICC3P
Active Standby Current in Power
Down Mode
CKE< = VIL(max), tCK> = tCK(min)
90
mA
ICC3N
Active Standby Current in Non-Power
Down Mode
CKE> = VIH(min), tCK> = tCK(min), Input
changed one time
450
mA
CS =
High
ICC4
Burst Operating Current
tRC = Infinite, CL = 3,
tCK> = tCK(min), IO = 0 mA
2 Banks Activated
1530
mA
1, 2
ICC5
Auto Refresh Current
tRC>= tRC (min)
2160
mA
1,2
ICC6
Self Refresh Current
CKE = <0,2 V
Standard
27
mA
1,2
L-version
13.5
V437432S24V Rev. 1.0 January 2002
7
CS =
High
MOSEL VITELIC
V437432S24V
AC Characteristics 3,4
TA = 0° to 70°C; VSS = 0V; VCC = 3.3V ± 0.3V, tT = 1 ns
Limit Values
-75PC
#
Symbol
Parameter
Min.
Max.
Unit
Note
Clock and Clock Enable
1
2
3
tCK
fCK
tAC
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
7.5
7.5
System frequency
CAS Latency = 3
CAS Latency = 2
–
–
133
133
MHz
MHz
Clock Access Time
CAS Latency = 3
CAS Latency = 2
–
–
5.4
6
ns
ns
ns
ns
4,5
4
tCH
Clock High Pulse Width
2.5
–
ns
6
5
tCL
Clock Low Pulse Width
2.5
–
ns
6
6
tCS
Input Setup time
1.5
–
ns
7
7
tCH
Input Hold Time
0.8
–
ns
7
8
tCKSP
CKE Setup Time (Power down mode)
2.5
–
ns
8
9
tCKSR
CKE Setup Time (Self Refresh Exit)
8
–
ns
9
10
tT
Transition time (rise and fall)
1
–
ns
RAS to CAS delay
15
–
ns
Common Parameters
11
tRCD
12
tRC
Cycle Time
60
120k
ns
13
tRAS
Active Command Period
42
–
ns
14
tRP
Precharge Time
20
–
ns
15
tRRD
Bank to Bank Delay Time
16
–
ns
16
tCCD
CAS to CAS delay time (same bank)
1
–
CLK
Refresh Cycle
17
tSREX
Self Refresh Exit Time
10
–
ns
9
18
tREF
Refresh Period (8192 cycles)
64
–
ms
8
4
Read Cycle
19
tOH
Data Out Hold Time
3
–
ns
20
tLZ
Data Out to Low Impedance Time
0
–
ns
21
tHZ
Data Out to High Impedance Time
3
7.5
ns
22
tDQZ
DQM Data Out Disable Latency
2
–
CLK
10
Write Cycle
23
tDPL
Data input to Precharge (write recovery)
2
–
CLK
24
tDAL
Data In to Active/refresh
5
–
CLK
25
tDQW
DQM Write Mask Latency
0
–
CLK
V437432S24V Rev. 1.0 January 2002
8
11
MOSEL VITELIC
V437432S24V
Notes:
1. The specified values are valid when addresses are changed no more than once during t CK(min.) and when No
Operation commands are registered on every rising clock edge during t RC(min). Values are shown per module
bank.
2. The specified values are valid when data inputs (DQ’s) are stable during t RC(min.).
3. All AC characteristics are shown for device level.
An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must be given followed
by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin.
4. AC timing tests have VIL = 0.4V and V IH = 2.4V with the timing referenced to the 1.4V crossover point. The transition
time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit
shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with
a input signal of 1V / ns edge rate between 0.8V and 2.0V.
+ 1.4 V
tCH
2.4V
CLOCK
50 Ohm
0.4V
tCL
tSETUP
Z=50 Ohm
tT
I/O
tHOLD
50 pF
1.4V
INPUT
tAC
tAC
tLZ
I/O
tOH
50 pF
1.4V
OUTPUT
Measurement conditions for
tac and toh
tHZ
5. If clock rising time is longer than 1 ns, a time (tT/2 -0.5) ns has to be added to this parameter.
6. Rated at 1.5V
7. If tT is longer than 1 ns, a time (tT -1) ns has to be added to this parameter.
8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be
given to “wake-up” the device.
9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command
is registered.
10.
Referenced to the time which the output achieves the open circuit condition, not to output voltage levels.
11.
tDAL is equivalent to t DPL + tRP.
V437432S24V Rev. 1.0 January 2002
9
MOSEL VITELIC
V437432S24V
Package Diagram
L-DIM-168-30
SDRAM DIMM Module Package
All measurements in mm
133.37
127.35
17.80
35.00
(2.54 max)
10
11
40
41
84
3.0
1
42.18
1.27 ± 0.100
63.68
A
94
95
124
125
168
4.0
85
B
D
6.35
2.50
2.0
4.45
Detail B
2.26
RADIUS
1.27 + 0.10
Tolerances: ± (0.13) unless otherwise specified.
V437432S24V Rev. 1.0 January 2002
0.2 ± 0.15
2.0
3.175
Detail A
1.0 ± 0.05
1.27
3.125
3.125
6.35
10
Detail C
MOSEL VITELIC
V437432S24V
Label Information
Module Density
MOSEL VITELIC
Part Number
Criteria of PC100 or PC133
(refer to MVI datasheet)
DIMM manufacture date code
V437432S24VXXX-XX 256MB CLX
PC133U-XXX-542-A
XXXX-XXXXXXX
Assembly in Taiwan
PC133 U -XXX
UNBUFFERED DIMM
A
Gerber file Intel PC100 x8 Based
CL= 3 or 2 (CLK)
tRCD= 3 or 2 (CLK)
tRP= 3 or 2 (CLK)
V437432S24V Rev. 1.0 January 2002
54 2
CAS Latency
2=CL2
3=CL3
JEDEC SPD Revision 2
tAC = 5.4 ns
11
MOSEL VITELIC
V437432S24V
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© Copyright , MOSEL VITELIC Corp.
Printed in U.S.A.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
The information in this document is subject to change without
notice.
MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
V437432S24V Rev. 1.0 January 2002
12