MP6922A Dual, Fast-Turn–Off, Intelligent Rectifier The Future of Analog IC Technology DESCRIPTION FEATURES The MP6922A is a dual, fast-turn–off, intelligent rectifier for synchronous rectification in LLC resonant converters. The IC drives two N-channel MOSFETs and regulates their forward voltage drop to about 30mV and turns it off before the switching current goes negative. MP6922A has a light-load function to latch off the gate driver under light-load conditions, thus limiting the current to below 600μA. Works with Both Standard and Logic-Level MOSFETs Compatible with Energy Star’s 0.5W Standby Requirements VDD Range from 8V to 24V Fast Turn-Off Total Delay of 20ns Reverse-Current–Protection Function Maximum Switching Frequency of 300kHz <600μA Quiescent Current in Light-Load Mode Supports CCM, CrCM and DCM Operation Available in SOIC8E, SOIC8, and SOIC14 packages The MP6922A’s fast turn-off enables both continuous-conduction mode and discontinuous-conduction mode. An internal reverse-current protection function ensures safe MOSFET operation under high-frequency continuous-current conditions. APPLICATIONS MP6922A requires a minimal number of readilyavailable standard external components and is available in SOIC8E, SOIC8, and SOIC14 packages. All MPS parts are lead-free and adhere to the RoHS directive. For MPS green status, please visit MPS website under Products, Quality Assurance page. AC-DC Adapters LCDs & PDP TVs Telecom SMPS “MPS” and “The Future of Analog IC Technology” are registered trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION SOIC8 MP6922A Rev. 1.02 www.MonolithicPower.com 11/30/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 1 MP6922A—DUAL, FAST-TURN–OFF, INTELLIGENT RECTIFIER SOIC8E SOIC14 MP6922A Rev. 1.02 www.MonolithicPower.com 11/30/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 2 MP6922A—DUAL, FAST-TURN–OFF, INTELLIGENT RECTIFIER ORDERING INFORMATION Part Number MP6922AGSE* MP6922AGN** MP6922AGS*** Package SOIC8 SOIC8E SOIC14 Top Marking MP6922A MP6922A MP6922A *For Tape & Reel, add suffix –Z (e.g. MP6922AGSE–Z); **For Tape & Reel, add suffix –Z (e.g. MP6922AGN–Z); ***For Tape & Reel, add suffix –Z (e.g. MP6922AGS–Z); PACKAGE REFERENCE ABSOLUTE MAXIMUM RATINGS (1) Recommended Operation Conditions VDD to VS1,VS2, VSS ........................-0.3V to +26V PGND to VS1,VS2, VSS ...................-0.3V to +0.3V VG1 to VS1, VSS ................................. -0.3V to VDD VG2 to VS2, VSS ................................. -0.3V to VDD VD1 to VS1, VSS .............................-0.7V to +180V VD2 to VS2, VSS .............................-0.7V to +180V LL, EN to VS1,VS2, VSS ..................-0.3V to +6.5V Maximum Operating Frequency............ 300 kHz (2) Continuous Power Dissipation .. (TA = +25°C) SOIC8 ........................................................ 1.4W SOIC8E ...................................................... 2.5W SOIC14 ...................................................... 1.5W Junction Temperature ...............................150°C Lead Temperature (Solder).......................260°C Storage Temperature .............. -55°C to +150°C VDD to VS1,VS2, VSS............................... 8V to 24V Operating Junction Temp. (TJ). -40°C to +125°C Thermal Resistance (4) θJA (3) θJC SOIC8 ..................................... 90 ...... 45 ... °C/W SOIC8E ................................... 50 ...... 10 ... °C/W SOIC14 ................................... 86 ...... 38 ... °C/W Notes: 1) Exceeding these ratings may damage the device. 2) TA=+25℃. The maximum allowable power dissipation is a function of the maximum junction temperature TJ (MAX), the junction-to-ambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD (MAX) = (TJ (MAX)-TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7, 4-layer PCB. Without heatsink. MP6922A Rev. 1.02 www.MonolithicPower.com 11/30/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 3 MP6922A—DUAL, FAST-TURN–OFF, INTELLIGENT RECTIFIER ELECTRICAL CHARACTERISTICS VDD = 12V, -40°C ≤TJ≤ 125°C, unless otherwise noted. Parameter VDD Voltage Range Symbol Conditions VDD UVLO Threshold Operating Current ICC Shutdown Current Light-Load Mode Current Thermal Shutdown Thermal Shutdown hysteresis Rising Hysteresis CLOAD=5nF, FSW=100kHz CLOAD=10nF, FSW=100kHz VDD=20V, EN=0V Rising Hysteresis Rising Hysteresis Enable Shutdown Threshold Enable UVLO Threshold CLOAD=5nF τDon CLOAD=10nF Turn-on delay VG1,2 (High) Turn-Off Threshold (VS1,2VD1,2) Turn-Off Propagation Delay 24 27 2.3 15 τDon τMIN τOFF Typ 1.1 Internal Pull-up Current on EN CONTROL CIRCUITRY SECTION VS1,2 –VD1,2 Forward Voltage Vfwd Input Bias Current on VD1,2 pin Minimum ON-Time Minimum OFF-Time Light-Load–Enter Delay Light-Load–Enter Pulse Width Light-Load Turn-On Pulse Width Hysteresis Light-Load–Enter OFF Period Width Light-Load Exit-Pulse Width Threshold (VD1,2-VS1,2) Light-load Enter-Pulse Width Threshold (VG1,2-VS1,2) Reverse-Current–Protection Threshold Reverse-Current–Protection Latch Time GATE DRIVER SECTION VG1,2 (Low) Min 8 4.8 0.5 12 -20°C≤TJ≤125°C -40°C≤TJ<-20°C -20°C≤TJ≤125°C -40°C≤TJ<-20°C VD1,2 = 180V CLOAD = 5nF 6.0 1 18 Max 24 7.0 1.5 23 Units V V V mA 31 600 600 150 30 1.5 0.2 3 0.2 2.0 0.45 3.6 0.45 mA µA µA °C °C V V V V 10 16 µA 30 150 250 250 350 45 200 mV 300 1.5 µA µs µs µs µs RLL=100kΩ RLL=100kΩ τLL-H RLL=100kΩ 0.2 µs τLL-OFF RLL=100kΩ 50 µs -450 VLL-GS -300 260 ns τLL-Delay τLL VLL-DS 80 1 1.6 160 2.2 ns -140 1.0 mV V VRCP 2.5 3 3.5 V τRCP 80 150 230 µs 13 14.5 VDD-2.2 0.1 16 V V ILOAD=1mA VDD >16V VDD <16V VD1,2= VSS -30 mV 15 ns MP6922A Rev. 1.02 www.MonolithicPower.com 11/30/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 4 MP6922A—DUAL, FAST-TURN–OFF, INTELLIGENT RECTIFIER ELECTRICAL CHARACTERISTICS (continued) VDD = 12V, -40°C ≤TJ≤ 125°C, unless otherwise noted. Parameter Turn-Off Total Delay Pull-Down Impedance Pull-Down Current Symbol Conditions VSS, VD1,2= τDoff RGATE=0Ω VD1,2= VSS, RGATE=0Ω 3V <VG1,2<10V Min Typ Max Units CLOAD=5nF, 50 75 ns CLOAD=10nF, 50 75 ns 1 3 2 Ω A MP6922A Rev. 1.02 www.MonolithicPower.com 11/30/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 5 MP6922A—DUAL, FAST-TURN–OFF, INTELLIGENT RECTIFIER PIN FUNCTIONS Pin # (SOIC8) 1 Pin # (SOIC8E) 1 Pin # (SOIC14) 2 3 2 3 EN 4 6 7 8 6 7 8 9 12 13 VD2 VS2 VS1 VD1 VDD VG1 1,14 PGND - 3 4 5 6 7 8 EXPOSED PAD - 5,10 NC - - 4 LL 5 - 11 - RCP VSS 2 Name VG2 Description MOSFET 2 Gate Driver Output. Enable Pin. Enables the internal IC logic when the EN pin voltage exceeds the EN shutdown threshold; the gate driver remains latched until the EN voltage exceeds the EN UVLO threshold. MOSFET 2 Drain Voltage Sense. Source pin used as reference for VD2. Source pin used as reference for VD1. MOSFET 1 Drain Voltage Sense. Supply Voltage. MOSFET 1 Gate Driver Output. Power Ground. Power switch return. No Connection. Light-Load–Timing Set. Connect a resistor to set the light-load timing. Reverse Current Protection. Internal 5V reference. Common Source. Used as reference for both channels. MP6922A Rev. 1.02 www.MonolithicPower.com 11/30/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 6 MP6922A—DUAL, FAST-TURN–OFF, INTELLIGENT RECTIFIER TYPICAL CHARACTERISTICS 6.15 450 260 6.1 440 255 6.05 430 265 6 250 420 5.95 245 410 5.9 240 400 5.85 235 5.8 390 230 5.75 380 225 -50 -30 -10 10 30 50 70 90 110130150 5.7 -50 -30 -10 10 30 50 70 90 110 130150 370 -50 -30 -10 10 30 50 70 90 110130150 250 350 50 45 300 200 40 250 35 30 150 200 100 150 20 100 15 50 25 10 50 0 5 0 0 -50 0 50 100 150 -50 50 45 35 40 34 0 50 100 150 0 50 100 150 -50 0 50 100 150 35 30 33 25 20 32 15 10 31 5 0 -50 0 50 100 150 30 -50 MP6922A Rev. 1.02 www.MonolithicPower.com 11/30/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 7 MP6922A—DUAL, FAST-TURN–OFF, INTELLIGENT RECTIFIER TYPICAL PERFORMANCE CHARACTERISTICS (continued) VDD = 12V, unless otherwise noted. VDS1 20V/div. VDS2 20V/div. VDS1 20V/div. VGS1 5V/div. VGS2 5V/div. VGS1 5V/div. ISD1 5A/div. ISD2 2A/div. ISD1 5A/div. VDS2 20V/div. VDS1 20V/div. VGS2 5V/div. VGS1 5V/div. ISD2 5A/div. ISD1 5A/div. MP6922A Rev. 1.02 www.MonolithicPower.com 11/30/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 8 MP6922A—DUAL, FAST-TURN–OFF, INTELLIGENT RECTIFIER BLOCK DIAGRAM Figure 1: Functional Block Diagram MP6922A Rev. 1.02 www.MonolithicPower.com 11/30/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 9 MP6922A—DUAL, FAST-TURN–OFF, INTELLIGENT RECTIFIER OPERATION The MP6922A operates in discontinuousconduction mode (DCM), continuous-conduction mode (CCM), and critical conduction mode (CrCM) condition. Operating in either DCM or CrCM, the control circuitry controls the gate in forward mode; it turns the gate off when the MOSFET current is low. In CCM, the control circuitry turns off the gate during very fast transients. Blanking The control circuitry contains a blanking function that ensure that when the MOSFET turns ON/OFF, the MOSFET remains in that state for ~1μs, which determines the minimum ON-time. During the turn-on blanking period, the turn-off threshold is not totally blanked, but changes to ~+100mV (instead of +30mV). This ensures that the part can always turn OFF even during the turn-on blanking period (albeit slower, so avoid setting the synchronous period to less than 1μs at CCM condition in the LLC converter to eliminate shoot-through). VD Clamp The MP6922A uses a high-voltage JFET at its input because VD1,2 can go as high as 180V. Connect a small resistor between the VD1,2 pin and the external MOSFET drain to avoid excessive currents when VG goes below -0.7V. Under-Voltage Lockout (UVLO) When VDD goes below the UVLO threshold, the part enters sleep mode and a 10kΩ resistor pulls down VG. Enable Pin If EN is pulled low, the part enters sleep mode. Thermal Shutdown If the junction temperature of the IC exceeds 150°C, VG is pulled low and the part stops switching. The part resumes normal operation after the junction temperature has dropped to 120°C. Turn-On Phase VDS (VD–VSS) goes negative (<-500mV) when the switch current flows through the MOSFET’s body diode. If VDS is much lower than the turn-on threshold of the control circuitry (-30mV), then the MOSFET turns on after about 200ns turn-on delay (Figure 2). Triggering the turn-on threshold (-30mV) causes the circuit to add a blanking time (minimum ontime 1μs), during which the turn-off threshold changes from +30V to +100mV. This blanking time avoids erroneous triggering caused by ringing on the synchronous power switch. 0mV -30mV tDon VDS VGATE tDoff 2V Figure 2: Turn-On and Turn-Off delay Conducting Phase When the MOSFET turns ON, VDS (-ISD×RDS(ON)) rise relative to the switch current (ISD) drop. When VDS rises above the turn-on threshold (–30mV), the control circuitry stops pulling up the gate driver and the MOSFET driver voltage drops, which increases the MOSFET’s RDS(ON). This adjusts VDS (-ISD×RDS(ON)) to around -30mV even when the switch current ISD is fairly small, and can prevent the internal driver from triggering until the current through the MOSFET has dropped to near zero. Turn-Off Phase When VDS rises to trigger the turn-off threshold (30mV), the control circuitry pulls down the driver switch voltage after a 20ns turn-off delay (shown in Figure 2). Similarly, a 1.6μs blanking time occurs after the switch turns off, during which the MOSFET does not turn on to avoid erroneous triggering. Figure 3 shows the MP6922A operating under a heavy-load. The high current initially saturates the driver voltage. After VDS goes above –30mV, the driver voltage decreases to adjust the VDS to around –30mV. MP6922A Rev. 1.02 www.MonolithicPower.com 11/30/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 10 MP6922A—DUAL, FAST-TURN–OFF, INTELLIGENT RECTIFIER Figure 4 shows the MP6922A operating at lightload. The low current prevents the driver voltage from saturating but decreases when the synchronous power switch turns on and adjusts VDS. Vds 0mV -30mV After entering light-load mode, the MP6922A monitors the MOSFET’s body diode conducting period by sensing VDS (when VDS exceeds – 300mV (VLL-DS), MP6922A treats the the MOSFET’s body-diode conducting period as finished). If the MOSFET’s body diode conducting period exceeds 2.4μs (τLL+τLL-H), lightload mode ends and the MOSFET unlatches to restart the synchronous rectification. For the SOIC14 package. the MP6922A has an LL pin that allows τLL to be adjusted by an external resistor: Isd LL 2.2s Vgs Figure 3: Synchronous Rectification Operation at Heavy Load Vds 0mV -30mV RLL 100k Latch Off during Burst Operation The IC also monitors the synchronous MOSFET OFF period. If the OFF period exceeds the lightload–enter OFF period width (τLL-OFF), the MP6922A enters light-load mode and latches off the gate driver. The gate driver is unlatched when the drainsource voltage of the synchronous MOSFET VDS drops below –30mV. Isd Vgs Figure 4: Synchronous Rectification Operation at Light Load Light-Load Latch-Off Function The gate driver of MP6922A is latched to limit driver losses under light-load condition to improve light-load efficiency. Normal Operation Latch Off When the MOSFET’s switching-cycle conducting period falls below 2.2μs (τLL), the MP6922A enters light-load mode and latches off the MOSFET after a 160μs delay (light-load-enter delay, τLL-Delay) Reverse Current–Protection Function When the LLC system operates in CCM at a very high frequency, the synchronous current may reverse before the IC turns off the gate driver, which can lead to shoot-through (in centertapped outputs with full-wave rectification topologies). The MP6922A has a protection function to latch off the gate driver when the current reverses before the driver signal is pulled low. When the synchronous current reverses, the high spike can be observed between the MOSFET’s drain/source. The MP6922A monitors the voltage through the RCP pin using a voltage divider. When the voltage of RCP pin exceeds VRCP, MP6922A latches the driver signal of both channels for ~150μs (τRCP) to protect the synchronous MOSFET. At the end of τRCP, MP6922A restarts the synchronous rectification. MP6922A Rev. 1.02 www.MonolithicPower.com 11/30/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 11 MP6922A—DUAL, FAST-TURN–OFF, INTELLIGENT RECTIFIER TYPICAL APPLICATION CIRCUIT CN1 1 F1 2 SS-5-1A R2 2.21K R3 820K R4 0 C3 470pF 1 R5 3.57K 2 C5 AGND 100uF SS TIMER CT FSET BURST CS BO C6 100uF U1 R6 1M R7 10K BST HG SW N.C. Vcc LG GND PFC C7 16 100n 15 14 13 12 11 10 9 R8 1M 2 1 1 1 R12 10K 1 R13 1 R11 10K D3 C8 2.2uF AGND R14 1 M2 M1 CX1 120nF R16 1K R15 1 C9 100uF R17 51 4 L1 D4 5 PGND VG2 U6 2 CS 50uH C10 10nF 1 2 1 1 800uH 2 3 4 VG1 VDD T1 8 7 8 7 6 5 R18 100K Vs1 Vs2 R21 1K R19 10K R20 2K R23 10 M3 C13 2.2nF R26 10 D5 2 R25 10K 1 U3 2 C14 2.2nF M4 R27 10K R28 10 D6 VDD VD1 VS1 VS1 Vg1 5 6 7 8 8 C22 1nF C23 1nF R30 137K R29 10K PGND 2.2uF C15 PGND Vg1 9 PGND 10 11 12 13 14 Vg2 VS2 PGND RCP VG1 NC VG2 LL VD1 VDD VD2 VS1 U2 MP6922AGS VG2 EN VD2 VS2 MP6922AGN VG1 VS2 NC EN PGND 1 R24 10 1 7 6 5 4 3 PGND 2 C11 1nF R22 1K Vg2 C12 1nF PGND 1 2 3 4 C16 22nF U4 PC817A C17 10uF AGND U5 R31 3.3K PGND 2 R32 40.2K C19 C18 2200uF 1 C20 2200uF R34 1K 470pF PGND 10K R36 R35 38.3K R33 C21 0.1uF 1.8K 2 1 2 D1 10 D2 R10 10 2 R9 AGND 6 5 VD1 2 3 2 3 CR1 1 2 3 4 5 6 1 HR1000A EN VD1 VSS 4 4 1 2 LATCH Vcc 2 C2 0.47uF Burst CS 7 8 3 VD2 MP6922AGS E Burst 1 2 1 C1 1uF AGND R1 9.53K AGND C4 10nF AGND PGND 4 4 3 1 3 Vg1 VD1 VS1 Vg1 VDD VD1 VD2 Vg2 VD2 VS2 Vg2 VD2 1 2 2 1 2 3 4 Vcc VDD 1 2 CN2 Figure 5—Synchronous Rectification in LLC with MP6922A 12 MP6922A Rev. 1.02 www.MonolithicPower.com 11/30/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. MP6922A—DUAL, FAST-TURN–OFF, INTELLIGENT RECTIFIER PACKAGE INFORMATION SOIC8 0.189(4.80) 0.197(5.00) 0.050(1.27) 0.024(0.61) 8 5 0.063(1.60) 0.150(3.80) 0.157(4.00) PIN 1 ID 1 0.228(5.80) 0.244(6.20) 0.213(5.40) 4 TOP VIEW RECOMMENDED LAND PATTERN 0.053(1.35) 0.069(1.75) SEATING PLANE 0.004(0.10) 0.010(0.25) 0.013(0.33) 0.020(0.51) 0.0075(0.19) 0.0098(0.25) SEE DETAIL "A" 0.050(1.27) BSC SIDE VIEW FRONT VIEW 0.010(0.25) x 45o 0.020(0.50) GAUGE PLANE 0.010(0.25) BSC 0o-8o 0.016(0.41) 0.050(1.27) DETAIL "A" NOTE: 1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN BRACKET IS IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.004" INCHES MAX. 5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION AA. 6) DRAWING IS NOT TO SCALE. MP6922A Rev. 1.02 www.MonolithicPower.com 11/30/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 13 MP6922A—DUAL, FAST-TURN–OFF, INTELLIGENT RECTIFIER SOIC8E (EXPOSED PAD) MP6922A Rev. 1.02 www.MonolithicPower.com 11/30/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 14 MP6922A—DUAL, FAST-TURN–OFF, INTELLIGENT RECTIFIER SOIC14 0.338(8.55) 0.344(8.75) 0.024(0.61) 8 14 0.063 (1.60) 0.150 (3.80) 0.157 (4.00) PIN 1 ID 0.050(1.27) 0.228 (5.80) 0.244 (6.20) 0.213 (5.40) 7 1 TOP VIEW RECOMMENDED LAND PATTERN 0.053(1.35) 0.069(1.75) SEATING PLANE 0.050(1.27) BSC 0.013(0.33) 0.020(0.51) 0.004(0.10) 0.010(0.25) SEE DETAIL "A" SIDE VIEW FRONT VIEW 0.010(0.25) x 45o 0.020(0.50) GAUGE PLANE 0.010(0.25) BSC 0o-8o 0.016(0.41) 0.050(1.27) 0.0075(0.19) 0.0098(0.25) NOTE: 1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN BRACKET IS IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.004" INCHES MAX. 5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION AB. 6) DRAWING IS NOT TO SCALE. DETAIL "A" NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP6922A Rev. 1.02 www.MonolithicPower.com 11/30/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 15