DATA SHEET MOS INTEGRATED CIRCUIT µPD3729 5000 PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR The µPD3729 is a high-speed and high sensitive color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal and has the function of color separation. The µPD3729 has 3 rows of 5000 pixels, and it is a 2-output/color type CCD sensor with 2 rows/color of charge transfer register, which transfers the photo signal electrons of 5000 pixels separately in odd and even pixels. Therefore, it is suitable for 400 dpi/A3 high-speed color digital copiers and so on. FEATURES • Valid photocell : 5000 pixels × 3 • Photocell's pitch : 10 µm • Line spacing : 40 µm (4 lines) Red line-Green line, Green line-Blue line • Color filter : Primary colors (red, green and blue), pigment filter (with light resistance 107 lx•hour) • Resolution : 16 dot/mm (400 dpi) A3 (297 × 420 mm) size (shorter side) • Drive clock level : CMOS output under 5 V operation • Data rate : 30 MHz MAX. (15 MHz/1 output) • Output type : 2 outputs in phase/color • Power supply : +12 V • On-chip circuits : Reset feed-through level clamp circuits Voltage amplifiers ORDERING INFORMATION Part Number Package µPD3729D CCD linear image sensor 24-pin ceramic DIP (400 mil) The information in this document is subject to change without notice. Document No. S12883EJ1V0DS00(1st edition) Date published November 1998 N CP(K) Printed in Japan © 1998 µPD3729 BLOCK DIAGRAM φ 1L VOD 20 19 5 φ1 φ2 12 15 16 22 D134 ..... φ TG1 (Blue) D134 D129 ..... 14 13 φ TG2 (Green) D134 D129 ..... D129 S4999 S5000 (Blue) 11 φ TG3 (Red) Photocell (Green) S4999 S5000 S1 S2 ..... D128 D27 CCD analog shift register Transfer gate Transfer gate CCD analog shift register 2 Photocell (Red) S4999 S5000 ..... D128 CCD analog shift register Transfer gate D27 2 Photocell Transfer gate CCD analog shift register 23 VOUT4 1 (Green, even) VOUT5 (Red, odd) S1 S2 D128 ..... VOUT3 24 (Green, odd) VOUT6 (Red, even) 21 CCD analog shift register Transfer gate S1 S2 VOUT1 (Blue, odd) GND GND GND 4 D27 VOUT2 (Blue, even) φ CLB Transfer gate CCD analog shift register 3 6 9 10 φ RB φ1 φ2 µPD3729 PIN CONFIGURATION (Top View) CCD linear image sensor 24-pin ceramic DIP (400 mil) • µPD3729D 24 VOUT3 Output signal 3 (Green, odd) Output signal 6 (Red, even) VOUT6 2 23 VOUT1 Output signal 1 (Blue, odd) Output signal 5 (Red, odd) VOUT5 3 22 VOUT2 Output signal 2 (Blue, even) Ground GND 4 21 GND Output drain voltage VOD 5 20 φ CLB Reset feed-through level clamp clock Reset gate clock φ RB 6 19 φ 1L Last stage shift register clock 1 No connection NC 7 18 NC No connection No connection NC 8 17 NC No connection Shift register clock 1 φ1 9 16 φ2 Shift register clock 2 Shift register clock 2 φ2 10 15 φ1 Shift register clock 1 Transfer gate clock 3 (for Red) φ TG3 11 14 φ TG1 Transfer gate clock 1 (for Blue) 13 φ TG2 Transfer gate clock 2 (for Green) Ground GND Blue 5000 Green 5000 Red 5000 1 1 1 VOUT4 1 Output signal 4 (Green, even) 12 PHOTOCELL STRUCTURE DIAGRAM PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing) 10 µm 10 µ m 7 µm Ground Blue photocell array 3 µm 4 lines (40 µm) 10 µm Green photocell array Channel stopper 4 lines (40 µm) 10 µm Red photocell array Aluminum shield 3 µPD3729 ABSOLUTE MAXIMUM RATINGS (TA = +25 °C) Parameter Symbol Ratings Unit Output drain voltage VOD –0.3 to +15 V Shift register clock voltage Vφ1, Vφ1L, Vφ2 –0.3 to +15 V Reset gate clock voltage VφRB –0.3 to +15 V Reset feed-through level clamp clock voltage VφCLB –0.3 to +15 V Transfer gate clock voltage VφTG1 to VφTG3 –0.3 to +15 V Operating ambient temperature TA –25 to +70 °C Storage temperature Tstg –40 to +100 °C Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently. RECOMMENDED OPERATING CONDITIONS (TA = +25 °C) Parameter MIN. TYP. MAX. Unit Output drain voltage VOD 11.4 12.0 12.6 V Shift register clock high level Vφ1H, Vφ1LH, Vφ2H 4.5 5.0 5.5 V Shift register clock low level Vφ1L, Vφ1LL, Vφ2L –0.3 0 +0.5 V Reset gate clock high level VφRBH 4.5 5.0 5.5 V Reset gate clock low level VφRBL –0.3 0 +0.5 V Reset feed-through level clamp clock high level VφCLBH 4.5 5.0 5.5 V Reset feed-through level clamp clock low level VφCLBL –0.3 0 +0.5 V Transfer gate clock high level VφTG1H to VφTG3H 4.5 Vφ1HNote Vφ1HNote V Transfer gate clock low level VφTG1L to VφTG3L –0.3 0 +0.5 V Data rate 2fφRB – 2 30 MHz Note When Transfer gate clock high level (VφTG1H to VφTG3H) is higher than Shift register clock high level (Vφ1H), Image lag can increase. 4 Symbol µPD3729 ELECTRICAL CHARACTERISTICS TA = +25 °C, VOD = 12 V, fφRB = 1 MHz, data rate = 2 MHz, storage time = 10 ms, light source: 3200 K halogen lamp +C-500S (infrared cut filter, t = 1mm), input signal clock = 5 Vp-p Parameter Symbol Saturation voltage Test Conditions Vsat Saturation exposure MIN. TYP. MAX. Unit 1.5 2.0 – V Red SER 0.32 lx•s Green SEG 0.37 lx•s Blue SEB 0.29 lx•s Photo response non-uniformity 6 18 % 1.0 5.0 mV 0.5 5.0 mV 2.0 5.0 mV DSNU2 1.0 5.0 mV Power consumption PW 500 700 mW Output impedance ZO 0.3 0.5 kΩ Average dark signal Note 1 PRNU VOUT = 1 V ADS1 Light shielding ADS2 Dark signal non-uniformity Response Image lag Note 1 DSNU1 Light shielding Red RR 4.3 6.2 8.1 V/lx•s Green RG 3.8 5.4 7.0 V/lx•s Blue RB 4.7 6.8 8.9 V/lx•s 2.0 5.0 % 1.0 5.0 % 5.0 6.0 V Note 1 IL1 VOUT = 1 V IL2 Offset level Note 2 Output fall delay time VOS Note 3 4.0 td VOUT = 1 V 25 Register imbalance RI VOUT = 1 V 0 Total transfer efficiency TTE VOUT = 1 V, 95 ns 4.0 % 98 % Red 630 nm Green 540 nm Blue 460 nm data rate = 30 MHz Response peak Dynamic range Note 1 Reset feed-through noise Random noise Note 1 Note 2 DR11 Vsat /DSNU1 1000 times DR12 Vsat/DSNU2 2000 times DR21 Vsat /σ1 2000 times DR22 Vsat/σ2 4000 times RFTN Light shielding –500 +200 +500 mV σ1 Light shielding – 1.0 – mV – 0.5 – mV σ2 Notes 1. ADS1, DSNU1, IL1, DR11 and DR21 show the specification of VOUT1 and VOUT2. ADS2, DSNU2, IL2, DR12 and DR22 show the specification of VOUT3 to VOUT6. 2. Refer to TIMING CHART 2. 3. When the fall time of φ1L (t2’) is the TYP. value (refer to TIMING CHART 2). 5 µPD3729 INPUT PIN CAPACITANCE (TA = +25 °C, VOD = 12 V) Parameter Shift register clock pin capacitance 1 Shift register clock pin capacitance 2 Symbol Pin name Pin No. C φ1 C φ2 φ1 φ2 MIN. TYP. MAX. Unit 9 500 800 pF 15 500 800 pF 10 500 800 pF 16 500 800 pF Last stage shift register clock pin capacitance C φL φ1L 19 50 pF Reset gate clock pin capacitance CφRB φRB 6 50 pF Reset feed-through level clamp clock pin capacitance CφCLB φCLB 20 50 pF Transfer gate clock pin capacitance CφTG φTG1 14 70 pF φTG2 13 70 pF φTG3 11 70 pF Remark Pins 9 and 15 (φ1), 10 and 16 (φ2) are each connected inside of the device. 6 TIMING CHART 1 (for each color) φ TG1 to φ TG3 φ1 φ2 φ 1L φ RB φ CLB Note 5125 5127 5129 5131 5133 5135 5137 5132 5134 5136 5138 119 121 123 125 127 129 131 120 122 124 126 128 130 132 5126 5128 5130 7 9 11 13 15 17 19 21 23 25 27 29 8 10 12 14 16 18 20 22 24 26 28 30 1 3 5 Note 2 4 6 VOUT1, 3, 5 VOUT2, 4, 6 Valid photocell (5000 pixels) Invalid photocell (6 pixels) 7 Note Input the φRB and φCLB pulses continuously during this period, too. Invalid photocell (6 pixels) µPD3729 Optical black (96 pixels) µPD3729 TIMING CHART 2 (for each color) t1 t2 90 % φ1 10 % φ2 90 % 10 % 90 % φ 1L 10 % φ RB t5 t1' 90 % t4 t6 t2' t3 t10 t8 10 % 90 % φ CLB t9 t11 t7 10 % td VOUT1 to VOUT6 RFTN VOS 10 % φTG1 to φTG3, φ1, φ2 TIMING CHART t13 t12 t14 90 % φ TG1 to φ TG3 10 % t15 90 % φ1 φ2 8 t16 µPD3729 Symbol MIN. TYP. MAX. Unit t1, t2 0 50 ns t1’, t2’ 0 5 ns t3 20 50 ns t4 20 100 t5, t6 0 20 ns t7 20 150 ns t8, t9 0 20 ns t10 –10Note 1 +50 t11 –5Note 2 +50 ns t12 5000 10000 ns t13, t14 0 50 ns t15, t16 900 1000 ns – ns – ns Notes 1. MIN. of t10 shows that the φRB and φCLB overlap each other. 90 % φ RB t10 φ CLB 90 % 2. MIN. of t11 shows that the φ1L and φCLB overlap each other. 90 % φ 1L t11 φ CLB φ1, φ2 cross points φ1L, φ2 cross points φ1 φ2 2 V or more φ2 90 % 2 V or more 2 V or more 0.5 V or more φ 1L Remark Adjust cross points (φ1, φ2) and (φ1L, φ2) with input resistance of each pin. 9 µPD3729 DEFINITIONS OF CHARACTERISTIC ITEMS 1. Saturation voltage: Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure: SE Product of intensity of illumination (IX) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity: PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula. ∆x × 100 x PRNU (%) = ∆x : maximum of xj − x 5000 Σx x= j j=1 5000 xj : Output voltage of valid pixel number j VOUT Register Dark DC level 4. x ∆x Average dark signal: ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula. 5000 Σd ADS (mV) = j j=1 5000 dj : Dark signal of valid pixel number j 10 µPD3729 5. Dark signal non-uniformity: DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV) : maximum of dj − ADS j = 1 to 5000 dj : Dark signal of valid pixel number j VOUT ADS Register Dark DC level DSNU 6. Output impedance: ZO Impedance of the output pins viewed from outside. 7. Response: R Output voltage divided by exposure (Ix•s). Note that the response varies with a light source (spectral characteristic). 8. Image lag: IL The rate between the last output voltage and the next one after read out the data of a line. φTG ON Light OFF VOUT V1 VOUT V1 IL (%) = VOUT ×100 11 µPD3729 9. Register imbalance: RI The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels. n 2 2 n ∑ (V2j – 1 – V2j) j= 1 RI (%) = × 100 n 1 n ∑ Vj j= 1 n : Number of valid pixels Vj : Output voltage of each pixel 10. Random noise: σ Random noise σ is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding). 100 σ (mV) = Σ (V – V) i 2 i=1 100 , V= 1 100 ΣV i 100 i=1 Vi: A valid pixel output signal among all of the valid pixels for each color VOUT V1 line 1 V2 line 2 … … V100 line 100 This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling). 12 µPD3729 STANDARD CHARACTERISTIC CURVES DARK OUTPUT TEMPERATURE CHARACTERISTIC 8 STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25 °C) 2 Relative Output Voltage 2 1 0.5 1 0.2 0.25 0.1 0 10 20 30 40 0.1 50 1 Operating Ambient Temperature TA(°C) 5 10 Storage Time (ms) TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter) (TA = +25 °C) 100 B 80 R Response Ratio (%) Relative Output Voltage 4 60 G 40 20 G B 0 400 500 600 700 800 Wavelength (nm) 13 µPD3729 APPLICATION CIRCUIT EXAMPLE +5 V +12 V 10 Ω + + µ PD3729 10 µ F/16 V 0.1 µ F 1 B4 2 B6 3 B5 4 5 φ RB 47 Ω 6 7 8 φ1 φ2 φ TG VOUT4 VOUT3 VOUT6 VOUT1 VOUT5 VOUT2 GND GND 24 B3 23 + B1 22 0.1 µ F 10 µ F/16 V B2 21 φ CLB 20 47 Ω φ RB φ 1L 19 47 Ω NC NC NC NC VOD 18 17 2Ω 9 φ1 φ2 16 2Ω 2Ω 10 φ2 φ1 15 2Ω 2Ω 11 φ TG3 φ TG1 14 2Ω φ TG2 13 2Ω GND 12 Remark The inverters shown in the above application circuit example are the 74AC04. B1 to B6 EQUIVALENT CIRCUIT +12 V 47 µ F/25 V + 0.1 µ F 4.7 kΩ 110 Ω CCD VOUT 47 Ω 2SC945 2SA1005 1 kΩ 14 +5 V 0.1 µ F 47 µ F/25 V φ CLB φ 1L µPD3729 PACKAGE DRAWING CCD LINEAR IMAGE SENSOR 24-PIN CERAMIC DIP (400mil) (Unit : mm) 10.03±0.15 68.0±0.4 1 10.6±0.6 9.4±0.7 2 The 1st valid pixel 10.16 1.27±0.05 0.46±0.05 27.94 2.54 (4.33) 3 (2.33) 3.50±0.5 0.97±0.3 2.0±0.3 3.30±0.32 4 0.25±0.05 Name Dimensions Refractive index Glass cap 67.0 × 8.5 × 1.0 1.5 1 The 1st valid pixel 2 The 1st valid pixel 3 The surface of the chip 4 The bottom of the package The edge of the package The center of the pin1 The top of the glass cap (Reference) The surface of the chip 24D-1CCD-PKG1-1 15 µPD3729 RECOMMENDED SOLDERING CONDITIONS When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. For more details, refer to our document "Semiconductor Device Mounting Technology Manual"(C10535E). Type of Through-hole Device µPD3729D: CCD linear image sensor 24-pin ceramic DIP (400 mil) Process Partial heating method 16 Conditions Pin temperature: 300 °C or below, Heat time: 3 seconds or less (per pin) µPD3729 [MEMO] 17 µPD3729 [MEMO] 18 µPD3729 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee outpin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 19 µPD3729 [MEMO] The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5