DATA SHEET MOS INTEGRATED CIRCUIT µ PD3777 5400 PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR The µ PD3777 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal and has the function of color separation. The µ PD3777 has 3 rows of 5400 pixels, and each row has a double-sided readout type of charge transfer register. And it has reset feed-through level clamp circuits, a clamp pulse generation circuit and voltage amplifiers. Therefore, it is suitable for 600 dpi/A4 color image scanners, color facsimiles and so on. FEATURES • Valid photocell : 5400 pixels × 3 • Photocell’s pitch : 5.25 µ m 2 • Photocell size : 5.25 × 5.25 µ m • Line spacing : 42 µ m (8 lines) Red line - Green line, Green line - Blue line • Color filter : Primary colors (red, green and blue), pigment filter (with light resistance 10 lx•hour) • Resolution : 24 dot/mm A4 (210 × 297 mm) size (shorter side) 7 600 dpi US letter (8.5” × 11”) size (shorter side) : • Drive clock level : CMOS output under 5 V operation • Data rate : 4 MHz MAX. • Power supply : +12 V • On-chip circuits : Reset feed-through level clamp circuits : Clamp pulse generation circuit : Voltage amplifiers ORDERING INFORMATION Part Number Package µ PD3777CY CCD linear image sensor 22-pin plastic DIP (10.16 mm (400)) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S14583EJ1V0DS00 (1st edition) Date Published December 1999 NS CP (K) Printed in Japan © 1999 2 BLOCK DIAGRAM VOD φ 2L GND GND φ1 19 17 2 11 14 CCD analog shift register 13 φ TG1 (Blue) 12 φ TG2 (Green) 10 φ TG3 (Red) D67 D66 D65 S5400 Photocell (Blue) S5399 S2 ........ S1 21 D64 VOUT1 (Blue) D14 Transfer gate Transfer gate CCD analog shift register D67 D66 D65 S5400 Photocell (Green) S5399 S2 ........ S1 22 D64 VOUT2 (Green) D14 Transfer gate Transfer gate CCD analog shift register CCD analog shift register D67 D66 D65 S5400 Photocell (Red) S5399 ........ S2 1 S1 VOUT3 (Red) D64 Transfer gate D14 Data Sheet S14583EJ1V0DS00 CCD analog shift register Transfer gate Clamp pulse generator CCD analog shift register 4 9 φ RB φ 1L φ2 µ PD3777 3 µ PD3777 PIN CONFIGURATION (Top View) CCD linear image sensor 22-pin plastic DIP (10.16 mm (400)) • µ PD3777CY 22 VOUT2 Output signal 2 (Green) Ground GND 2 21 VOUT1 Output signal 1 (Blue) Reset gate clock φ RB 3 20 NC No connection Last stage shift register clock 1 φ1L 4 19 VOD Output drain voltage No connection NC 5 18 NC No connection No connection NC 6 17 φ 2L Last stage shift register clock 2 No connection NC 7 16 NC No connection No connection NC 8 15 NC No connection Shift register clock 2 φ2 9 14 φ1 Shift register clock 1 Transfer gate clock 3 (for Red) φ TG3 10 13 φ TG1 Transfer gate clock 1 (for Blue) Ground GND 11 12 φ TG2 Transfer gate clock 2 (for Green) Blue 5400 Green 5400 5400 Red PHOTOCELL STRUCTURE DIAGRAM 1 1 1 VOUT3 1 Output signal 3 (Red) PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing) 5.25 µ m 5.25 µ m 2.75 µ m Blue photocell array 2.5 µ m 8 lines (42 µm) 5.25 µ m Green photocell array Channel stopper 8 lines (42 µm) 5.25 µ m Red photocell array Aluminum shield Data Sheet S14583EJ1V0DS00 3 µ PD3777 ABSOLUTE MAXIMUM RATINGS (TA = +25 °C) Parameter Symbol Ratings Unit Output drain voltage VOD −0.3 to +15 V Shift register clock voltage Vφ 1, Vφ 2, Vφ 1L, Vφ 2L −0.3 to +8 V Reset gate clock voltage Vφ RB −0.3 to +8 V Transfer gate clock voltage Vφ TG1 to Vφ TG3 −0.3 to +8 V Operating ambient temperature TA −25 to +60 °C Storage temperature Tstg −40 to +70 °C Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently. RECOMMENDED OPERATING CONDITIONS (TA = +25 °C) MIN. TYP. MAX. Unit Output drain voltage Parameter VOD Symbol 11.4 12.0 12.6 V Shift register clock high level Vφ 1H, Vφ 2H, Vφ 1LH, Vφ 2LH 4.5 5.0 5.5 V Shift register clock low level Vφ 1L, Vφ 2L, Vφ 1LL, Vφ 2LL −0.3 0 +0.5 V Reset gate clock high level Vφ RBH 4.5 5.0 5.5 V Reset gate clock low level Vφ RBL −0.3 0 +0.5 V Note Vφ 1H Note Vφ 1H V Transfer gate clock high level Vφ TG1H to Vφ TG3H 4.5 Transfer gate clock low level Vφ TG1L to Vφ TG3L −0.3 0 +0.5 V Data rate fφ RB − 1.0 4.0 MHz Note When Transfer gate clock high level (Vφ TG1H to Vφ TG3H) is higher than Shift register clock high level (Vφ 1H), Image lag can increase. 4 Data Sheet S14583EJ1V0DS00 µ PD3777 ELECTRICAL CHARACTERISTICS TA = +25 °C, VOD = 12 V, data rate (fφ RB) = 1 MHz, storage time = 5.5 ms, input signal clock = 5 Vp-p, light source : 3200 K halogen lamp + C−500S (infrared cut filter, t = 1 mm) + HA−50 (heat absorbing filter, t = 3 mm) Parameter Symbol Saturation voltage Test Conditions Vsat Saturation exposure MIN. TYP. MAX. Unit 2.0 2.5 − V Red SER 0.420 lx•s Green SEG 0.429 lx•s Blue SEB 0.739 lx•s Photo response non-uniformity PRNU VOUT = 1.0 V Average dark signal ADS Light shielding Dark signal non-uniformity DSNU Light shielding 1.5 5.0 mV Power consumption PW 360 540 mW Output impedance ZO 0.5 1 kΩ Response % 0.2 2.0 mV RR 4.15 5.94 7.72 V/lx•s Green RG 4.07 5.82 7.57 V/lx•s Blue RB 2.36 3.38 4.39 V/lx•s 2.0 7.0 % 5.5 7.0 V IL Note 1 Output fall delay time 20 Red Image lag Offset level 6 VOUT = 1.0 V VOS Note 2 4.0 td VOUT = 1.0 V 50 ns Total transfer efficiency TTE VOUT = 1.0 V, data rate = 4 MHz 92 98 % Register imbalance RI VOUT = 1.0 V 0 1.0 Response peak Random noise % Red 630 nm Green 540 nm Blue 460 nm Dynamic range Reset feed-through noise 4.0 Note 1 DR1 Vsat/DSNU 1666 times DR2 Vsat/σ 2500 times RFTN Light shielding −1000 −300 +500 mV σ Light shielding − 1.0 − mV Notes 1. Refer to TIMING CHART 2. 2. When each fall time of φ 1L and φ 2L (t2’, t1’) is the TYP. value (refer to TIMING CHART 2). Data Sheet S14583EJ1V0DS00 5 µ PD3777 INPUT PIN CAPACITANCE (TA = +25 °C, VOD = 12 V) Parameter 6 Symbol Pin name Pin No. MIN. TYP. MAX. Unit Shift register clock pin capacitance 1 Cφ 1 φ1 14 650 pF Shift register clock pin capacitance 2 Cφ 2 φ2 9 650 pF Last stage shift register clock pin capacitance Cφ L φ 1L 4 10 pF φ 2L 17 10 pF Reset gate clock pin capacitance Cφ RB φ RB 3 10 pF Transfer gate clock pin capacitance Cφ TG φ TG1 13 60 pF φ TG2 12 60 pF φ TG3 10 60 pF Data Sheet S14583EJ1V0DS00 TIMING CHART 1 (for each color) 8 7 6 5 4 3 2 φ1 1 φ TG1 to φ TG3 φ2 φ 1L φ 2L 61 62 63 64 65 66 5463 5464 5465 5466 5467 5468 5469 Note 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Data Sheet S14583EJ1V0DS00 φ RB Note VOUT1 to VOUT3 Optical black (49 pixels) Valid photocell (5400 pixels) Invalid photocell (2 pixels) Invalid photocell (3 pixels) Note Input the φ RB pulse continuously during this period, too. µ PD3777 7 8 TIMING CHART 2 (for each color) t2 t1' t2' 90 % φ1 10 % 90 % φ2 10 % 90 % φ 1L Data Sheet S14583EJ1V0DS00 10 % 90 % φ 2L 10 % t5 φ RB t1 t3 t6 t4 90 % 10 % + td td RFTN VOUT _ VOS 10 % RFTN 10 % µ PD3777 µ PD3777 φ TG1 to φ TG3, φ 1, φ 2 TIMING CHART t8 t9 t7 90 % φ TG1 to φ TG3 10 % t10 t11 90 % φ1 φ2 Symbol MIN. TYP. MAX. Unit t1, t2 0 50 − ns t1’, t2’ 0 5 − ns t3 20 150 − ns t4 130 300 − ns t5, t6 t7 t8, t9 t10, t11 0 50 − ns 3000 10000 − ns 0 50 − ns 900 1000 − ns φ 1, φ 2 cross points φ1 2 V or more 2 V or more φ2 φ 1L, φ 2 cross points φ2 2 V or more φ 1L 0.5 V or more φ 1, φ 2L cross points φ1 2 V or more φ 2L 0.5 V or more Remark Adjust cross points (φ 1, φ 2), (φ 1L, φ 2) and (φ 1, φ 2L) with input resistance of each pin. Data Sheet S14583EJ1V0DS00 9 µ PD3777 DEFINITIONS OF CHARACTERISTIC ITEMS 1. Saturation voltage : Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure : SE Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity : PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula. PRNU (%) = ∆x × 100 x ∆x : maximum of xj − x 5400 Σx x= j j=1 5400 xj : Output voltage of valid pixel number j VOUT Register Dark DC level x ∆x 4. Average dark signal : ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula. 5400 Σd ADS (mV) = j j=1 5400 dj : Dark signal of valid pixel number j 10 Data Sheet S14583EJ1V0DS00 µ PD3777 5. Dark signal non-uniformity : DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV) : maximum of dj − ADS j = 1 to 5400 dj : Dark signal of valid pixel number j VOUT ADS Register Dark DC level DSNU 6. Output impedance : ZO Impedance of the output pins viewed from outside. 7. Response : R Output voltage divided by exposure (lx•s). Note that the response varies with a light source (spectral characteristic). 8. Image lag : IL The rate between the last output voltage and the next one after read out the data of a line. φ TG Light ON OFF VOUT V1 VOUT IL (%) = V1 VOUT × 100 9. Register imbalance : RI The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels. n 2 2 n ∑ (V2j – 1 – V2j) j=1 RI (%) = n 1 n ∑ Vj × 100 j=1 n : Number of valid pixels Vj : Output voltage of each pixel Data Sheet S14583EJ1V0DS00 11 µ PD3777 10. Random noise : σ Random noise σ is defined as the standard deviation of a valid pixel output signal with 100 times (= 100 lines) data sampling at dark (light shielding). 100 Σ (V – V) 2 i σ (mV) = i=1 100 , V= 1 100 ΣV i 100 i = 1 Vi : A valid pixel output signal among all of the valid pixels for each color VOUT V1 line 1 V2 line 2 … … V100 line 100 This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling). 12 Data Sheet S14583EJ1V0DS00 µ PD3777 STANDARD CHARACTERISTIC CURVES (Nominal) DARK OUTPUT TEMPERATURE CHARACTERISTIC STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25 °C) 8 2 Relative Output Voltage 2 1 0.5 1 0.2 0.25 0.1 0 10 20 30 40 0.1 50 Operating Ambient Temperature TA(°C) 1 5 10 Storage Time (ms) TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter and heat absorbing filter) (TA = +25 °C) 100 R G B 80 Response Ratio (%) Relative Output Voltage 4 60 40 G 20 B 0 400 500 600 700 800 Wavelength (nm) Data Sheet S14583EJ1V0DS00 13 µ PD3777 APPLICATION CIRCUIT EXAMPLE +12 V +5 V 10 Ω + + µ PD3777 10 µ F/16 V 0.1 µ F 1 B3 2 φ RB 47 Ω 3 150 Ω 4 0.1 µ F 47 µ F/25 V VOUT3 VOUT2 GND VOUT1 φ RB NC φ 1L VOD NC NC NC φ 2L NC NC NC NC φ2 φ1 22 21 7 4.7 Ω 9 10 Ω 10 11 + 0.1 µ F 10 µ F/16 V 19 18 17 150 Ω 16 15 8 φ2 B1 20 5 6 +5 V B2 φ TG3 φ TG1 φ TG2 GND 14 4.7 Ω 13 10 Ω 12 10 Ω φ1 φ TG Remark The inverters shown in the above application circuit example are the 74HC04 (data rate < 2 MHz) or the 74AC04 (data rate: 2 to 4 MHz). B1 to B3 EQUIVALENT CIRCUIT 12 V + 100 Ω CCD VOUT 47 µ F/25 V 100 Ω 2SC945 2 kΩ 14 Data Sheet S14583EJ1V0DS00 µ PD3777 PACKAGE DRAWING CCD LINEAR IMAGE SENSOR 22-PIN PLASTIC DIP (10.16 mm (400)) (Unit : mm) 1bit 2.0 9.25±0.3 0.5±0.3 37.5 44.0±0.3 10.16 (1.79) 2.55±0.2 1 1.02±0.15 (5.42) 2.54 4.21±0.5 0.46±0.1 0 ∼ 10° 0.05 0.25± 4.39±0.4 25.4 Name Plastic cap Dimensions 42.9 × 8.35 × 0.7 1 The bottom of the package Refractive index 2 1.5 The surface of the chip 2 The thickness of the cap over the chip 22C-1CCD-PKG6-1 Data Sheet S14583EJ1V0DS00 15 µ PD3777 RECOMMENDED SOLDERING CONDITIONS When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. For more details, refer to our document “Semiconductor Device Mounting Technology Manual” (C10535E). Type of Through-hole Device µ PD3777CY : CCD linear image sensor 22-pin plastic DIP (10.16 mm (400)) Process Partial heating method Conditions Pin temperature : 300 °C or below, Heat time : 3 seconds or less (per pin) Caution During assembly care should be taken to prevent solder or flux from contacting the plastic cap. The optical characteristics could be degraded by such contact. 16 Data Sheet S14583EJ1V0DS00 µ PD3777 [MEMO] Data Sheet S14583EJ1V0DS00 17 µ PD3777 NOTES ON CLEANING THE PLASTIC CAP 1 CLEANING THE PLASTIC CAP Care should be taken when cleaning the surface to prevent scratches. The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below. Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is recommended that a clean surface or cloth be used. 2 RECOMMENDED SOLVENTS The following are the recommended solvents for cleaning the CCD plastic cap. Use of solvents other than these could result in optical or physical degradation in the plastic cap. Please consult your sales office when considering an alternative solvent. Solvents 18 Symbol Ethyl Alcohol EtOH Methyl Alcohol MeOH Isopropyl Alcohol IPA N-methyl Pyrrolidone NMP Data Sheet S14583EJ1V0DS00 µ PD3777 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S14583EJ1V0DS00 19 µ PD3777 [MEMO] • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98. 8