DATA SHEET MOS INTEGRATED CIRCUIT µPD3739 5000 PIXELS CCD LINEAR IMAGE SENSOR The µPD3739 is a CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal. The µPD3739 is a 2-output type CCD sensor with 2 rows of high-speed charge transfer register, which transfers the photo signal electrons of 5000 pixels separately in odd and even pixels. It is developed as the higher sensitivity version of the previous device, the µPD35H71A. It is suitable for 400 dpi/A3 high-speed digital copiers, OCRs and high-end business facsimiles. FEATURES • Valid photocell : 5000 pixels • Photocell’s pitch : 7 µm • High sensitivity : 9.0 V/lx·s TYP. (Light source: Daylight color fluorescent lamp) • Low image lag : 1 % MAX. • Peak response wavelength : 550 nm (green) • Resolution : 16 dot/mm (400 dpi) A3 (297 × 420 mm) size (shorter side) • Data rate : 40 MHz MAX. (20 MHz/1 output) • Output type : 2 outputs out of phase (2 outputs in phase also supported) • Power supply : +12 V • Drive clock level : CMOS output under 5 V operation • On-chip circuit : Automatic φR level adjuster • Pin assign : Functional compatible with the µPD35H71A ORDERING INFORMATION Part Number Package µPD3739D CCD linear image sensor 22-pin ceramic DIP (CERDIP) (400 mil) The information in this document is subject to change without notice. Document No. S12744EJ1V0DS00 (1st edition) Date Published September 1997 N Printed in Japan © 1997 µPD3739 COMPARISON CHART µPD3739 µPD35H71A Pin 1 GND DGND Pin 2 NC TEST Pin 4 NC VDD Pin 11 NC VSUB Pin 21 NC AGND Pin 22 NC DGND 1000 ± 20 % Unspecified Data rate MIN. (MHz) 0.5 Unspecified ELECTRICAL Saturation exposure TYP. (Ix⋅s) 0.17 0.29 CHARACTERISTICS Photo response non-uniformity (%) 4 10 ±5 ±10 0.3 1.0 MIN. TYP. 0 4 –3 –1, +3 MAX. 6 +6 Power consumption MAX. (mW) 400 Unspecified Response (V/Ix⋅s) 7.2 9.0 10.8 4.15 5.2 6.25 3.5 3.0 250 350 500 400 500 800 Item PIN CONFIGURATION RECOMMENDED OPERATING CONDITIONS Capacitance of reset gate clock pin external capacitor (pF) TYP. MAX. Average dark signal TYP. (mV) Dark signal non-uniformity (mV) MIN. TYP. MAX. Offset level TYP. (V) Shift register clock pin capacitance (pF) Note MIN. TYP. MAX. Dynamic range TYP. DR1 375 500 (times) DR2 2143 Undefined Reset feed-through noise (mV) MIN. TYP. MAX. 0 400 600 Unspecified 250 500 0.7 Undefined Random noise TYP. (mV) TIMING CHART In phase outputs operating timing is added Out of phase outputs operation only DEFINITIONS OF Photo response non-uniformity Absolute value Minus and plus value CHARACTERISTICS ITEMS Dark signal non-uniformity Absolute value Minus and plus value Random noise Standard deviation of signal level distribution by scan RECOMMENDED SOLDERING CONDITIONS Wave soldering is deleted Undefined — Note Due to the changing of measurement conditions, and pin capacitance of each devices is almost the same. (µPD3739: Power supply = 12 V, µPD35H71A: Power supply = 0 V) 2 BLOCK DIAGRAM VOUT2 GND VOD φ R2 φ 1L2 φ 22 φ 12 1 19 18 17 14 13 CCD analog shift register 20 D34 D33 S5000 Photocell S4999 S2 ...... S1 D9 Automatic φ R level adjuster D32 Transfer gate 12 φ TG Transfer gate VOUT1 3 CCD analog shift register 5 6 9 10 φ R1 φ 2L1 φ21 φ11 µPD3739 3 µPD3739 PIN CONFIGURATION (Top View) CCD linear image sensor 22-pin ceramic DIP (CERDIP) (400 mil) Ground 1 GND NC 22 No connection No connection 2 NC NC 21 No connection Output signal 1 3 VOUT1 VOUT2 20 Output signal 2 No connection 4 NC VOD 19 Output drain voltage Reset gate clock 1 5 φ R1 φR2 18 Reset gate clock 2 Last stage shift register clock 2 6 φ 2L1 φ 1L2 17 Last stage shift register clock 1 No connection 7 NC NC 16 No connection No connection 8 NC NC 15 No connection Shift register clock 2 9 φ 21 φ 22 14 Shift register clock 2 Shift register clock 1 10 φ 11 φ 12 13 Shift register clock 1 No connection 11 NC φ TG 12 Transfer gate clock PHOTOCELL STRUCTURE DIAGRAM 2 µm 7 µm 5 µm Aluminum shield 4 Channel stopper µPD3739 ABSOLUTE MAXIMUM RATINGS (TA = +25 ˚C) Parameter Symbol Ratings Unit Output drain voltage VOD –0.3 to +15 V Shift register clock voltage V φ1 , V φ 2 –0.3 to +15 V Reset gate clock voltage VφR1, VφR2 –0.3 to +15 V Transfer gate clock voltage VφTG –0.3 to +15 V Operating ambient temperature TA –25 to +55 ˚C Storage temperature Tstg –40 to +100 ˚C Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently. RECOMMENDED OPERATING CONDITIONS (TA = –25 to +55 ˚C) Parameter Symbol Conditions MIN. TYP. MAX. Unit Output drain voltage VOD 11.4 12.0 12.6 V Shift register clock high level Vφ1H, Vφ2H 4.5 5.0 5.5 V Shift register clock low level Vφ1L, Vφ2L –0.3 0 +0.5 V Reset gate clock high level VφR1H, VφR2H Note 4.5 5.0 5.5 V Reset gate clock low level VφR1L, VφR2L Note –0.3 0 +0.5 V Capacitance of reset gate clock pin external capacitor CEXTφR Non-polar type 800 1000 1200 pF Transfer gate clock high level VφTGH 4.5 5.0 5.5 V Transfer gate clock low level VφTGL –0.3 0 +0.5 V Data rate 2fφR1, 2fφR2 0.5 2 40 MHz Note Input the reset gate clocks 1 and 2 (φR1, φR2) to pins 5 and 18, respectively, via an input resistor and a capacitor. Use of a capacitor is indispensable. Refer to APPLICATION CIRCUIT EXAMPLE for the connection method. The reset gate clock high level and low level at the IC pins (after passing through the external capacitor) varies according to the IC, due to the on-chip automatic φR level adjuster. The recommended operating conditions of reset gate clocks 1, 2 (φR1, φR2) in the table above are for signals applied to the external capacitor. Remark φ1 in the above tables represents φ11, φ12 and φ1L2. φ2 represents φ21, φ22 and φ2L1. 5 µPD3739 ELECTRICAL CHARACTERISTICS TA = +25 ˚C, VOD = 12 V, fφ1 = 1 MHz, data rate = 2 MHz, storage time = 10 ms light source: 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm), input signal clock = 5 Vp-p Parameter Symbol Test Conditions MIN. TYP. MAX. Unit 1.0 1.5 V 0.17 lx•s Saturation voltage Vsat Saturation exposure SE Daylight color fluorescent lamp Photo response non-uniformity PRNU VOUT = 500 mV 4 10 % Average dark signal ADS Light shielding 0.3 3.0 mV Dark signal non-uniformity DSNU Light shielding 4.0 6.0 mV Power consumption PW 200 400 mW Output impedance ZO 0.2 0.5 kΩ Response RF 9.0 10.8 V/Ix·s Daylight color fluorescent lamp 0 7.2 Response peak wavelength Image lag Offset level 550 IL Note 1 Output fall delay time VOUT = 1 V VOS Note 2 2.0 td VOUT = 1 V Register imbalance RI VOUT = 500 mV 0 Total transfer efficiency TTE VOUT = 500 mV, data rate = 40 MHz 92 Dynamic range DR1 nm 0.3 1.0 % 3.5 5.0 V 20 ns 4.0 % 98 % Vsat/DSNU 375 times DR2 Vsat/σ 2143 times Reset feed-through noise Note 1 RFTN Light shielding 0 400 600 mV Random noise σ Light shielding — 0.7 — mV Notes 1. Refer to TIMING CHART 2, 5. 2. Typical value when the respective fall times of φ1L2 and φ2L1 are t11’, t41’ and t2’, t32’ (refer to TIMING CHART 2, 5). Note that VOUT1 and VOUT2 are the outputs of the two steps of emitter-follower shown in APPLICATION CIRCUIT EXAMPLE. 6 µPD3739 INPUT PIN CAPACITANCE (TA = +25 °C, VOD = 12 V) Parameter Shift register clock pin capacitance 1 Shift register clock pin capacitance 2 Last stage shift register clock pin capacitance Reset gate clock pin capacitance Transfer gate clock pin capacitance Symbol Pin name C φ1 C φ2 C φL C φR CφTG Pin No. MIN. TYP. MAX. Unit φ11 10 250 350 500 pF φ12 13 250 350 500 pF φ21 9 250 350 500 pF φ22 14 250 350 500 pF φ1L2 17 40 50 100 pF φ2L1 6 40 50 100 pF φR1 5 8 10 15 pF φR2 18 8 10 15 pF φTG 12 100 150 200 pF 7 φ TG φ 11 φ 21 φ 2L1 5037 5035 5033 5031 5029 35 33 31 29 27 11 9 7 5 VOUT1 3 1 φ R1 φ 12 φ 22 φ 1L2 φ R2 5038 5036 5034 5032 5030 Valid photocell (5000 pixels) Optical black (22 pixels) Invalid photocell (2 pixels) Invalid photocell (2 pixels) µPD3739 Note Input the φR1 and φR2 pulses continuously during this period, too. 36 34 32 30 28 12 10 8 6 VOUT2 4 Note 2 8 TIMING CHART 1 (Out of phase operation) TIMING CHART 2 (Out of phase operation) t7 t1 φ 11 50 % 90 % 10 % φ 21 50 % 90 % 10 % t1’ 90 % 10 % φ 2L1 t2’ 50 % t5 t6 t7’ t4 90 % 10 % φ R1 t2 50 % t3 td VOUT1 RFTN VOS 10 % t12 t17 t11 φ 12 90 % 10 % 50 % φ 22 90 % 10 % 50 % φ 1L2 t11’ 50 % t17’ t15 φ R2 50 % t16 t12’ 90 % 10 % t14 90 % 10 % t13 td RFTN VOS 10 % 9 µPD3739 VOUT2 µPD3739 TIMING CHART 3 (Out of phase operation) t21 t22 90 % φ TG 50 % 10 % t24 φ 11, φ 12, φ1L2 t23 t25 50 % φ 21,φ 22, φ 2L1 φ11, φ21 cross points φ12, φ22 cross points φ 11 φ 21 φ 12 2 V or more 2 V or more φ11, φ2L1 cross points 2 V or more φ1L2, φ22 cross points φ 22 φ 11 φ 2L1 2 V or more φ 22 2 V or more 2 V or more φ 1L2 0.5 V or more 0.5 V or more Remark Adjust cross points of (φ11, φ21), (φ12, φ22), (φ11, φ2L1) and (φ1L2, φ22) with input resistance of each pin. Symbol MIN. TYP. t1, t2, t11, t12 0 50 ns t1’, t2’, t11’, t12’ 0 5 ns t3, t13 15 50 ns t4, t14 5 20 ns t5, t6, t15, t16 0 20 ns t7, t7’, t17, t17’ 25 — ns t21, t22 0 50 ns 1000 2000 10 100 t23 t24, t25 10 MAX. 5000 Unit ns ns TIMING CHART 4 (In phase operation) φ TG φ 11 φ 21 φ 2L1 5031 5033 5035 5037 5034 5036 5038 35 36 5032 33 34 5029 31 11 12 32 9 10 29 7 8 30 5 6 27 3 4 28 1 VOUT1 2 φ R1 φ 12 φ 22 φ 1L2 φ R2 VOUT2 11 Note Input the φR1 and φR2 pulses continuously during this period, too. Valid photocell (5000 pixels) Invalid photocell (2 pixels) Invalid photocell (2 pixels) µPD3739 Optical black (22 pixels) 5030 Note 12 TIMING CHART 5 (In phase operation) t37 φ 11 50 % φ 21 50 % t31 90 % 10 % 90 % 10 % t32’ φ 2L1 φ R1 t32 t35 t36 t34 90 % 10 % t31’ 50 % 90 % 10 % 50 % t37’ t33 td VOUT1 RFTN VOS 10 % t47 t42 φ 12 50 % 90 % 10 % φ 22 50 % 90 % 10 % t41’ φ 1L2 t45 φ R2 t46 t44 90 % 10 % t42’ 50 % 90 % 10 % 50 % t41 t47’ t43 td VOUT2 RFTN VOS µPD3739 10 % µPD3739 TIMING CHART 6 (In phase operation) t51 t52 90 % 50 % 10 % φ TG t54 φ 11 t53 t55 50 % φ 21, φ 2L1 φ 12, φ 1L2 50 % φ 22 φ11, φ21 cross points φ12, φ22 cross points φ 11 φ12 φ 21 2 V or more 2 V or more φ11, φ2L1 cross points 2 V or more φ1L2, φ22 cross points φ 22 φ 11 φ 2L1 2 V or more φ22 2 V or more 2 V or more φ 1L2 0.5 V or more 0.5 V or more Remark Adjust cross points of (φ11, φ21), (φ12, φ22), (φ11, φ2L1) and (φ1L2, φ22) with input resistance of each pin. Symbol MIN. TYP. t31, t32, t41, t42 0 50 ns t31’, t32’, t41’, t42’ 0 5 ns t33, t43 15 50 ns t34, t44 5 20 ns t35, t36, t45, t46 0 20 ns t37, t37’, t47, t47’ 25 — ns t51, t52 0 50 ns 1000 2000 10 100 t53 t54, t55 MAX. 5000 Unit ns ns 13 µPD3739 DEFINITIONS OF CHARACTERISTIC ITEMS 1. Saturation voltage: Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure: SE Product of intensity of illumination (IX) and storage time(s) when saturation of output voltage occurs. 3. Photo response non-uniformity: PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula. PRNU (%) = ∆x × 100 x ∆x : maximum of xj − x 5000 2700 ∑ Σxxj j j j=1 =1 xx == 5000 2700 xj : Output voltage of valid pixel number j VOUT x Register Dark DC level 4. ∆x Average dark signal: ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula. 5000 ∑ dj 2700 Σd ADS (mV) = j=1 j j=1 ADS (mV) = 5000 2700 dj : Dark signal of valid pixel number j 14 µPD3739 5. Dark signal non-uniformity: DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV): maximum of | dj – ADS | j = 1 to 5000 dj: Dark signal of valid pixel number j VOUT ADS Register Dark DC level DSNU 6. Output impedance: ZO Impedance of the output pins viewed from outside. 7. Response: R Output voltage divided by exposure (Ix•s). Note that the response varies with a light source (spectral characteristic). 8. Image lag: IL The rate between the last output voltage and the next one after read out the data of a line. φ TG Light OFF ON VOUT V1 VOUT V1 IL (%) = VOUT ×100 15 µPD3739 9. Register imbalance: RI The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels. n 2 2 n ∑ (V2j – 1 – V2j) j= 1 RI (%) = × 100 n 1 n ∑ Vj j= 1 n : Number of valid pixels Vj : Output voltage of each pixel 10. Random noise: σ Random noise σ is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding). 100 ∑ (Vi – V) 2 σ (mV) = i=1 , V= 100 1 100 100 ∑ Vi i=1 Vi : A valid pixel output signal among all of the valid pixels VOUT V1 V2 V100 line 1 line 2 line 100 This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling). 16 µPD3739 STANDARD CHARACTERISTIC CURVES (TA = +25 ˚C) DARK OUTPUT TEMPERATURE CHARACTERISTIC STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC 2 8 4 Relative Output Voltage Relative Output Voltage 1 2 1 0.5 0.2 0.25 0.1 0.1 0 10 20 30 40 1 50 5 10 Storage Time (ms) Operating Ambient Temperature TA (˚C) SPECTRAL RESPONSE CHARACTERISTIC 100 Response Ratio (%) 80 60 40 20 0 400 600 800 1000 1200 Wavelength (nm) 17 µPD3739 APPLICATION CIRCUIT EXAMPLE (Out of phase operation) +12 V 10 Ω + µ PD3739 +5 V 1 2 + 10 µ F/16 V 0.1 µ F 3 B1 4 φ R1 φ2 200 Ω 1000 pF 47 Ω GND NC NC NC VOUT2 VOUT1 22 21 5 φ R1 φ R2 18 6 φ 2L1 φ 1L2 17 8 NC NC NC 0.1 µ F 10 µ F/16 V B2 19 VOD NC + 20 NC 7 1000 pF 200 Ω 47 Ω φ R2 φ1 16 15 2Ω 9 φ 21 φ 22 14 2Ω 2Ω 10 φ 11 φ 12 13 2Ω φ TG 12 2Ω NC 11 +5 V 0.1 µ F 47µF/25 V φTG Remarks 1. The µPD3739 can be operated leaving pin 2 (NC) unconnected, and connecting pin 4 (NC) and pin 11 (NC) to a +12 V power supply (when replaces the µPD35H71A). 2. It is recommended that pins 6 (φ2L1) and 17 (φ1L2) each is separately driven a driver other than that of pins 10, 13 (φ11, φ12) and pins 9, 14 (φ21, φ22). 3. The inverters shown in the above application circuit example are the 74AC04. B1, B2 EQUIVALENT CIRCUIT 47 µ F/25V 4.7 kΩ 110 Ω CCD VOUT 47 Ω +12 V 2SC945 2SA1005 1 kΩ 18 + µPD3739 PACKAGE DRAWING CCD LINEAR IMAGE SENSOR 22PIN CERAMIC DIP(CERDIP)(400mil) (Unit : mm) 1bit 9.65 ± 0.3 1.60±0.25 4.0 ± 0.3 42.2 ± 0.25 48.6 ± 0.5 0.46 ± 0.06 4.33±0.5 4.68±0.5 2.54 1.02 ± 0.15 (5.27) (1.95) 10.16 2.38 ±0.3 0 to 10° .05 0.25±0 25.4 Name Dimensions Refractive index Glass cap 47.5×9.25×0.7 1.5 22D-1CCD-PKG8 19 µPD3739 RECOMMENDED SOLDERING CONDITIONS When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL” (C10535E). Type of Through-hole Device µPD3739D: CCD linear image sensor 22-pin ceramic DIP (CERDIP) (400 mil) Process Partial heating method 20 Conditions Pin temperature: 260 ˚C or below, Heat time: 10 seconds or less (per pin). µPD3739 [MEMO] 21 µPD3739 [MEMO] 22 µPD3739 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 23 µPD3739 [MEMO] The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. 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To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 2