DP8473 Floppy Disk Controller PLUS-2 TM General Description Features This controller is a full featured floppy disk controller that is software compatible with the mPD765A, but also includes many additional hardware and software enhancements. These enhancements include additional logic specifically required for an IBMÉ PC, PC-XTÉ, PC-ATÉ, or PS/2É design. This controller incorporates a precision analog data separator, that includes a self trimming delay line and VCO. Up to three external filters are switched automatically depending on the data rate selected. This provides optimal performance at the standard PC data rates of 250/300 kb/s, and 500 kb/s. It also enables optimum performance at 1 Mb/s (MFM). These features combine to provide the lowest possible PLL bandwidth, with the greatest lock range, and hence the widest window margin. This controller includes write precompensation circuitry. A shift register is used to provide a fixed 125 ns early-late precompensation for all tracks at 500k/300k/250 kb/s (83 ns for 1 MB/s), or a precompensation value that scales with (Continued) Y Y Y Y Y Y Fully mPD765A and IBM-BIOS compatible Integrates all PCXTÉ, PCATÉ, and most PS/2É Logic Ð On chip 24 MHz Crystal Oscillator Ð DMA enable logic Ð IBM compatible address decode of A0 – A2 Ð 12 mA mP bus interface buffers Ð 48 mA floppy drive interface buffers Ð Data rate and drive control registers Precision analog data separator Ð Self-calibrating PLL and delay line Ð Automatically chooses one of three filters Ð Intelligent read algorithm Two pin programmable precompensation modes Other enhancements Ð up to 1 Mb/s data rate Ð Implied seek up to 4000 tracks Ð IBM or ISO formatting Low power CMOS, with power down mode Connection Diagrams Dual-In-Line Package Plastic Leaded Chip Carrier TL/F/9384 – 1 Top View Order Number DP8473V See NS Package Number V52A TL/F/9384 – 2 Top View TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. PLUS-2TM is a trademark of National Semiconductor Corporation. IBMÉ, PCXTÉ, PCATÉ and PS/2É are registered trademarks of International Business Machines Corporation. C1995 National Semiconductor Corporation TL/F/9384 Order Number DP8473N See NS Package Number N48A RRD-B30M105/Printed in U. S. A. DP8473 Floppy Disk Controller PLUS-2 July 1990 General Description (Continued) This device is available in a 52 pin Plastic Chip Carrier, and in a 48 pin Dual-In-Line package. the data rate, 83 ns/125 ns/208 ns/ 250 ns for data rates of 1.0M/500k/300k/250 kb/s respectively. Specifically to support the PC-AT and PC-XT design, the Floppy Disk Controller PLUS-2 includes address decode for the A0 – A2 address lines, the motor/drive select register, data rate register for selecting 250/300/500 kb/s, Disk Changed status, dual speed spindle motor control, low write current and DMA/interrupt sharing logic. The controller also supports direct connection to the mP bus via internal 12 mA buffers. The controller also can be connected directly to the disk drive via internal open drain high drive outputs, and Schmitt inputs. In addition to this logic the DP8473 includes many features to ease design of higher performance drives and future controller upgrades. These include 1.0 Mb/s data rate, extended track range to 4096, Implied seeking, working Scan Commands, motor control timing, both standard IBM formats as well as Sony 3.5× (ISO) formats, and other enhancements. Table of Contents General Description Pin Description Functional Description Register Description Result Phase Register Description Processor Software Interface Command Description Table Command Descriptions DC and AC Characteristics Block Diagram TL/F/9384 – 3 Note 1: The MTR2, MTR3, DR2, and DR3 are not available on the 48 pin DIP (DP8473N, J) versions. Note 2: See Figure 4 for filter description. Note 3: Total transistor count is 29,700 (approx). FIGURE 1. DP8473 Functional Block Diagram 2 Pin Descriptions DP8473 PCC DP8473 DIP 19–21 17–19 Address lines from the microprocessor. This determines which registers the microprocessor is accessing as shown in Table IV in the Register Description Section. Don’t care during DMA transfers. CS 18 16 Active low input to enable the RD and WR inputs. Not required during DMA transfers. This should be held high during DMA transfers. DAK 32 30 Active low input to acknowledge the DMA request and enable the RD and WR inputs. This signal is enabled when D3 of the Drive Control Register is set. DIR 4 2 This output determines the direction of the head movement (low e step in, high e step out). When in the write or read modes, this output will be high. This is a high drive open drain output. DRQ 31 29 Active high output to signal the DMA controller that a data transfer is needed. This signal is enabled when D3 of the Drive Control Register is set. DRV TYP 47 43 This is an input used by the controller to enable the 300 kb/s mode. This enables the use of floppy drives with either dual or single speed spindle motors. For dual speed spindle motors, this pin is tied low. When low, and 300 kb/s data rate is selected in the data rate register, the PLL actually uses 250 kb/s. This pin is tied high for single speed spindle motor drives (standard AT drive). When this pin is high and 300 kb/s is selected 300 kb/s is used. (See also RPM/LC pin). DR0 6 4 This is an active low drive select line for drive 0 that is controlled by the Drive Control register bits D0, D1. The Drive Select bit is ANDed with the Motor Enable of the same number. This is a high drive open drain output. Symbol A0, A1, A2 Function DR1 5 3 This is an active low drive select similar to DR0 line except for drive 1. DR2 45 Ð This is the same as DR0 except for drive 2. DR3 43 Ð This is the same as DR0 except for drive 3. DSKCHG/RG 35 33 This latched Schmitt input signal is inverted and routed to D7 of the data bus and is read when address xx7H is enabled. DSKCHG is a disk drive output that indicates when the drive door has been opened. When the RG bit in the Mode Command is set, this pin functions as a Read Gate signal that when low forces the data separator to lock to the crystal, and when high it locks to data for diagnostic purposes. D0 – D4 22-26 20–24 Bi-directional data lines to the microprocessor. These are the lower 5 bits and have buffered 12 mA outputs. D5 – D7 28–30 26–28 Bi-directional data lines to the microprocessor. These upper 3 bits have buffered 12 mA outputs. FGND250 42 40 This pin connects the PLL filter for 250k(MFM)/125k(FM) b/s or 300k(MFM)/150k(FM) b/s to ground. This is a low impedance open drain output. FGND500 41 39 This pin connects the PLL filter for 500k(MFM)/250k(FM) b/s to ground. This is a low impedance open drain output. FILTER 40 38 This pin is the output of the charge pump and the input to the VCO. One or more filters are attached between this pin and the GNDA, FGND250 and FGND500 pins. GNDA 39 37 This pin is the analog ground for the data separator, including all primary and secondary PLLs and delay lines. GNDB 27 25 This pin is the digital ground for the 12 mA microprocessor interface buffers. This includes D0 – D7, INT, and DRQ. GNDC 36 34 This pin is the digital ground for the controller’s digital logic, including all internal registers, micro-engine, etc. GNDD 2 48 This pin is the digital ground for the disk interface output drivers. HD SEL 9 7 This output determines which disk drive head is active. Low e Head 1, Open (high) e Head 0. This is a high drive open drain output. INDEX 11 9 This active low Schmitt input signals the beginning of a track. INT 34 32 Active high output to signal that an operation requires the attention of the microprocessor. The action required depends on the current function of the controller. This signal is enabled when D3 of the Drive Control Register is set. 3 Pin Descriptions (Continued) DP8473 PCC DP8473 DIP MTR0 8 6 This is an active low motor enable line for drive 0, which is controlled by the Drive Control register. This is a high drive open drain output. MTR1 7 5 This is an active low motor enable line for drive 1. Similar to MTR0. Symbol Function MTR2 1 Ð This is an active low motor enable line for drive 2. Similar to MTR0. MTR3 52 Ð This is an active low motor enable line for drive 3. Similar to MTR0. OSC1 38 36 One side of an external 24 MHz crystal is attached here. This pin is tied low if an external clock is used. OSC2/CLOCK 37 35 One side of the external 24 MHz crystal is attached here. If a crystal is not used, a TTL or CMOS compatible clock is connected to this pin. PUMP/PREN 46 42 When the PU bit is set in Mode Command this pin is an output that indicates when the charge pump is making a correction. Otherwise this pin is an input that sets the precomp mode as shown in Table VI. If pin is configured as PUMP, PREN is assumed high. RD 17 15 Active low input to signal a read from the controller to the microprocessor . RDATA 44 41 The active low raw data read from the disk is connected here. This is a Schmitt input. RESET 15 13 Active high input that resets the controller to the idle state, and resets all the output lines to the disk drive to their disabled state. The Drive Control register is reset to 00. The Data Rate register is set to 250 kb/s. The Specify command registers are not affected. The Mode Command registers are set to the default values. Reset should be held active during power up. To prevent glitches activating the reset sequence, a small capacitor (1000 pF) should be attached to this pin. RPM/LC 51 47 This high drive open drain output pin has two functions based on the selection of the DRVTYP pin. 1. When using a dual speed spindle motor floppy drive (DRVTYP pin low), this output is used to select the spindle motor speed, either 300 RPM or 360 RPM. In this mode this output goes low when 250/300 kb/data rate is chosen in the data rate register, and high when 500 kb/s is chosen. 2. When using a single speed spindle motor floppy drive (DRVTYP pin high), this pin indicates when to reduce the write current to the drive. This output is high for high density media (when 500 kb/s is chosen). SETCUR 48 44 An external resistor connected from this pin to analog ground programs the amount of charge pump current that drives the external filters. The PLL Filter Design section shows how to determine the values. STEP 50 46 This active low open drain high drive output will produce a pulse at a software programmable rate to move the head during a seek operation. TC 33 31 Active high input to indicate the termination of a DMA transfer. This signal is enabled when the DMA Acknowledge pin is active. TRK0 10 8 This active low Schmitt input tells the controller that the head is at track zero of the selected disk drive. WDATA 3 1 This is the active low open drain write precompensated serial data to be written onto the selected disk drive. This is a high drive open drain output. WGATE 49 45 This active low open drain high drive output enables the write circuitry of the selected disk drive. This output has been designed to prevent glitches during power up and power down. This prevents writing to the disk when power is cycled. WR 16 14 Active low input to signal a write from the microprocessor to the controller. WRT PRT 12 10 This active low Schmitt input indicates that the disk is write protected. Any command that writes to that disk drive is inhibited when a disk is write protected. VCC 14 12 This pin is the 5V supply for the digital circuitry. VCCA 13 11 This pin is the 5V supply for the analog data separator circuitry. 4 Typical Application TL/F/9384 – 4 Recommended Plastic Chip Carrier Socket: AMP P/N 821551-1 or equivalent. FIGURE 2. DP8473 Typical Application Functional Description This section describes the basic architectural features of the DP8473, and many of the enhancements provided. Refer to Figure 1. DATA SEPARATOR The internal data separator consists of an analog PLL and its associated circuitry. The PLL synchronizes the raw data signal read from the disk drive. The synchronized signal is used to separate the encoded clock and data pulses. The data pulses are de-serialized into bytes and then sent to the mP by the controller. The main PLL consists of four main components, a phase comparator, a filter, a voltage controlled oscillator (VCO), and a programmable divider. The phase comparator detects the difference between the phase of the divider’s output and the phase of the raw data being read from the disk. This phase difference is converted to a current which either charges or discharges one of the three external filters. The resulting voltage on the filter changes the frequency of the VCO and the divider output to reduce the phase difference between the input data and the divider’s output. The PLL is ‘‘locked’’ when the frequency of the divider is exactly the same as the average frequency of the data read from the disk. A block diagram of the data separator is shown in Figure 3. 765A COMPATIBLE MICRO-ENGINE The core of the DP8473 is a mPD765A compatible microcoded engine. This engine consists of a sequencer, program ROM, and disk/misc registers. This core is clocked by either a 4 MHz, 4.8 MHz or 8 MHz clock selected in the Data Rate Register. Upon this core is added all the glue logic used to implement a PC-XT or AT, or PS/2 floppy controller, as well as the data separator and write precompensation logic. The controller consists of a microcoded engine that controls the entire operation of the chip including coordination of data transfer with the CPU, controlling the drive controls, and actually performing the algorithms associated with reading and writing data to/from the disk. This includes the read algorithm for the data separator. Like the mPD765A, this controller takes commands and returns data and status through the Data Register in a byte serial fashion. Handshake for command/status I/O is provided via the Main Status Register. All of the mPD765A commands are supported, as are many other enhanced commands. 5 Functional Description (Continued) TL/F/9384 – 5 FIGURE 3. Block Diagram of DP8473’s Data Separator TL/F/9384 – 8 TL/F/9384–6 a) Single Data Rate TL/F/9384 – 7 b) 250/500 kb/s Filter c) 250/500 kb/s and 1 Mb/s Note: For all filter configurations, 250kb/s and 300 kb/s share the same filter. FIGURE 4. Typical Configuration for Loop Filters for the DP8473 Showing Component Labels Figure 4 shows several possible filter configurations. For a filter to cover all data rates (Figure 4c ), the DP8473 has a 1 Mb/s filter always connected and other capacitor filter components for the other data rates are switched in parallel to this filter. The actual loop filter for 500 kb/s is the parallel combination of the two capacitors, C2C and C2B, attached to the FGND500 pin and to ground. The 250/300 kb/s filter is the parallel combination of the capacitors, C2C and C2A, attached to the FGND250, and ground. If 1 Mb/s need not be supported then the filter configuration of Figure 4b can be used. This configuration allows more optimal performance for both 500k and 250/300 kb/s. Figure 4a is a simple filter configuration primarily for a single data rate (or multiple data rates with a performance compromise). Table II shows some typical filter values. Other filter configurations and values are possible, these result in good general performance. While the controller and data separator support both FM and MFM encoding, the filter switch circuitry only supports To ensure optimal performance, the data separator incorporates several additional circuits. The quarter period delay line is used to determine the center of each bit cell. A secondary PLL is used to automatically calibrate the quarter period delay line. The secondary PLL also calibrates the center frequency of the VCO. To eliminate the logic associated with controlling multiple data rates the DP8473 supports the connection of three filters to the chip via the FGND250, and FGND500 pins (filter ground switches). The controller chooses which filter components to use based on the value loaded in the Data Rate Register. If 500 k(MFM) is being used then the FGND500 is enabled (FGND250 is disabled). If 250 k(MFM) or 300 k(MFM) is being used the FGND250 pin is enabled, and FGND500 is disabled. For 1 Mb/s (MFM) both FGND pins are disabled. Note for FM encoding: Sometimes, after a reset, the DP8473 will consistently return an error in the Result Phase after an FM read command. If this occurs, simply reset the DP8473 and retry the operation. This may have to be done more than once, as many as five times. Resetting and repeating will prevent soft errors being reported prematurely. This technique is used by MS-DOS. 6 Functional Description (Continued) the IBM standard MFM data rates. To provide both FM and MFM filters external logic may be necessary. The controller takes best advantage of the internal data separator by implementing a sophisticated ID search algorithm. This algorithm, shown in Figure 5, enhances the PLL’s lock characteristics by forcing the PLL to relock to the crystal any time the data separator attempts to lock to a non-preamble pattern. This algorithm ensures that the PLL is not thrown way out of lock by write splices or bad data fields. TABLE III. Data Rates (MFM) versus VCO Divide-By Factor C2 R2 C1 R1 (MFM b/s) Filter Values when Using All 3 Data Rates 1.0M 500k 250/300k C2C e 0.012 mF C2B e 0.015 mF C2A e 0.033 mF 560X 510 pF 5.6 kX Filter Values when Using 250/300 and 500 kb/s 500k 250/300k C2B e 0.027 mF C2A e 0.047 mF 560X 560X 1000 pF 5.6 kX C2 e 0.012 mF C2 e 0.027 mF C2 e 0.047 mF 560X 560X 560X 510 pF 1000 pF 2000 pF 4 8 16 16 PLL FILTER DESIGN This section provides information to enable design of the data separator’s external filter and charge pump set resistor. This discussion is for a single data rate filter, and can be easily extrapolated to the other filters of Figure 4. Table II shows some typical filter component values, but if a custom filter is desired, the following parameters must be considered: R1: Charge pump current setting resistor. The current set by this resistor is multiplied by the charge pump gain, KP which is E 2.5. Thus the charge pump current is: IPUMP e (2.5) 1.2V/R1. R1 should be set to between 3 –12 kX. This resistor determines the gain of the phase detector, which is KD e IPUMP/2q. Filter Using Only One Data Rate 1.0M 500k 300/250k N 1 Mb/s 500 kb/s 300 kb/s 250 kb/s PLL DIAGNOSTIC MODES In addition, the DP8473 has two diagnostic modes to enable filter optimization, 1) enabling the Charge Pump output signal onto the PUMP/PREN pin, and 2) providing external control of the Read Gate signal to the data separator. Both modes are enabled in the last byte of the Mode Command. The Pump output signal indicates when the charge pump is making a phase correction, and hence whether the loop is locked or not. The Read Gate function, when enabled, allows the designer to manually force the data separator to lock to the incoming data or back to the reference clock. This enables easy verification of the lock characteristics of the PLL, by monitoring the FILTER pin, and the Pump signal. TABLE II. Typical Filter Values for the Various Data Rates (Assuming g 6% Capture Range) Data Rate Data Rate 5.6 kX 5.6 kX 5.6 kX (These values are preliminary and thus are subject to change.) TL/F/9384 – 9 FIGURE 5. Read Algorithm-State Diagram for Data 7 Functional Description (Continued) C2: Filter capacitor in series with R2. With pump current this determines loop bandwidth. R2: C1: Filter resistor. Determines the PLL damping factor. This filter capacitor improves the performance of the PLL by providing additional filtering of bit jitter and noise. low 125 ns precomp is used for all data rates except 1 Mb/s which uses 83 ns. When PREN is tied high, the precompensation-value scales with data rate at 250 kb/s its 250 ns, for 300 kb/s its 208 ns, at 500 kb/s its 125 ns, and at 1.0 Mb/s its 83 ns. These values are shown in Table VI. PC-AT AND PC-XT LOGIC BLOCKS This section describes the major functional blocks of the PC logic that have been integrated on the controller. Refer back to Figure 1, the block diagram. DMA Enable Logic: This is gating logic that disables the DMA lines and the Interrupt output, under the control of the DMA Enable bit in the Drive control register. When the DMA Enable bit is 0 then the INT, and DRQ are held TRI-STATE, and DAK is disabled. Drive Output Buffers/Input Receivers: The drive interface output pins can drive 150X g 10% termination resistors. This enables connection to a standard floppy drive. All drive interface inputs are TTL compatible schmitt trigger inputs with typically 250 mV of hysteresis. The only functional differences between the 52 pin PLCC and the 48 pin DIP version are that the MTR2 and 3, and DR2 and 3 pins have been removed in order to accommodate the 48 pin package. KVCO: The ratio of the change in the frequency of the VCO output due to a voltage change at the VCO input. KVCO & 25 Mrad/s/V. The VCO is followed by a divider to achieve the desired frequency for each data rate. VCO center frequency is 4 MHz for data rates of 1 Mb/s, 500 kb/s, and 250 kb/s (MFM), and is 4.8 MHz for 300 kb/s (MFM). KPLL: This is the gain of the internal PLL circuitry, and is the product of VREF c KVCO c KP. This value is specified in the Phase Locked Loop Characteristics table. 0 n: This is the bandwidth of the PLL, and is given by, KPLL 0n e 2qC2N R1 where N is the number of VCO cycles between two phase comparisons. The value of N for the various data rates are shown in Table III. The damping factor is set to 0.7 to 1.2 and is given by, 0 g: ge Bus Interface-Address Decode: The address decode circuit allows software access to the controller, Drive Control Register, and Data Rate Register (see Table IV for the memory map) using the same address map as is used in the XT, AT, or PS/2. The decoding is provided for A0 – A2, so only a single address decoder connected to the chip select is needed to complete the decode. The bus interface logic includes the 8-bit data bus and DRQ/INT signals. The output drive for these pins is 12 mA. 0nR2C2 2 The trade off, when choosing filter components is between acquisition time while the PLL is locking and jitter immunity while reading data. To select the proper components for a standard floppy disk application the following procedure can be used: 1. Choose FM or MFM, and data rate. Determine N from Table III. Determine preamble length (MFM e 12). The PLL should lock within (/2 the preamble time. 2. Determine loop bandwidth (0n) required, and set the charge pump resistor R1. 3. Calculate C2 using: KPLL C2 e 2qR1N0n2 4. Choose R2 using: 2g R2 e 0nC2 6. Select C1 to be about (/20th of C2. The above procedure will yield adequate loop performance. If optimum loop performance is required, or if the nature of the loop performance is very critical, then some additional consideration must be given to choosing 0n and the damping factor. (For a detailed description on how to choose 0n and g, see: AN-505 Floppy Disk Data Separator Design Guide for the DP8473). TABLE IV. Address Memory Map for DP8473 A2 A1 A0 R/W Register 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 1 X X W X R R/W X W R None (Bus TRI-STATE) None (Bus TRI-STATE) Drive Control Register None (Bus TRI-STATE) Main Status Register Data Register None (Bus TRI-STATE) Data Rate Register Disk Changed Bit* *When this location is accessed only bit D7 is driving, all others are held TRI-STATE. Drive Control Register: This 8-bit write only register controls the drive selects, motor enables, DMA enable, and Reset. See Register Description. Reset Logic: The reset input pin is active high, and directly feeds the Drive Control Register and the Data Rate Register. After a hardware reset the Drive Control Register is reset to all zeros, and the Data Rate Register is set to 250 kb/s data rate. The controller is held reset until the software sets the Drive Control reset bit, after which the controller may be initialized. A software reset to the controller core can be issued by resetting then setting this bit. A software reset does not reset the Drive Control Register, or the Data Rate Register. WRITE PRECOMPENSATION The DP8473 incorporates a single fixed 3-bit shift register. This shift register outputs are tapped and multiplexed onto the write data output. The taps are selected by a standard precompensation algorithm. This precompensation value can be selected from the PUMP/PREN pin. When this pin is 8 Functional Description (Continued) Crystals: Data Rate Register and Clock Logic: This is a two bit register that controls the data rate that the controller uses. See Register Description. This register feeds logic that selects the data rates by programming a prescaler that divides the crystal or clock input by either 3, 5, or 6. This causes either 4 MHz, 4.8 MHz and 8 MHz to be input as the master clock for the controller core. If the Drive Type pin is high and a 300 kb/s data rate is chosen, 4.8 MHz is used to generate 300 kb/s, but when the DRVTYP pin is low and 300 kb/s is selected, 4 MHz is used, and the actual data rate is 250 kb/s. See Table VI. Low Power Mode Logic: This logic is an enhancement over the standard XT, AT, PS/2 design. In the Low Power Mode the crystal oscillator, controller and all linear circuitry are turned off. When the oscillator is turned off the controller will typically draw about 1 mA. The internal circuitry is disabled while the oscillator is off because the internal circuitry is driven from this clock. The oscillator will turn back on automatically after it detects a read or a write to the Main Status or Data Registers. It may take a few milli-seconds for the oscillator to stabilize and the mP will be prevented from trying to access the Data Register during this time through the normal Main Status Register protocol. (The Request for Master bit in the Main Status Register will be inactive.) There are two ways to go into the low power mode. One is to command the controller to switch to low power immediately. The other method is to set the controller to automatically go into the low power mode 500 ms after the beginning of the idle state (based on a 500 kb/s (MFM) data rate). This would be invisible to the software. The low power mode is programmed through the Mode Command. The Data Rate Register and the Drive Control Register are unaffected by the power down mode. They will remain active. It is up to the user to ensure that the Motor and Drive select signal are turned off. NEL-54024-2 NEL-C2800N SaRonix: SRX 3164 Register Description This section describes the register bits for all the registers that are directly accessible to the mP. Table IV (previous page) shows the memory map for these registers. Note that in the PC some of the registers are partially decoded, this is not the case here. All registers occupy only their documented addresses. MAIN STATUS REGISTER (Read Only) The read only Main Status Register indicates the current status of the disk controller. The Main Status Register is always available to be read. One of its functions is to control the flow of data to and from the Data Register. The Main Status Register indicates when the disk controller is ready to send or receive data. It should be read before each byte is transferred to or from the Data Register except during a DMA transfer. No delay is required when reading this register after a data transfer. D7 Request for Master: Indicates that the Data Register is ready to send or receive data from the mP. This bit is cleared immediately after a byte transfer and will become set again as soon as the disk controller is ready for the next byte. D6 Data Direction: Indicates whether the controller is expecting a byte to be written to (0) or read from (1) the Data Register. D5 Non-DMA Execution: Bit is set only during the Execution Phase of a command if it is in the non-DMA mode. In other words, if this bit is set, the multiple byte data transfer (in the Execution Phase) must be monitored by the mP either through interrupts, or software polling as described in the Processor Software Interface section. D4 Command in Progress: Bit is set after the first byte of the Command Phase is written. Bit is cleared after the last byte of the Result Phase is read. If there is no result phase in a command, the bit is cleared after the last byte of the Command Phase is written. D3 Drive 3 Seeking: Set after the last byte of the Command Phase of a Seek or Recalibrate command is issued for drive 3. Cleared after reading the first byte in the Result Phase of the Sense Interrupt Command for this drive. D2 Drive 2 Seeking: Same as above for drive 2. TABLE V. Truth Table for Drive Control Register D7 D6 D5 D4 D1 D0 X X X 1 X X 1 X X 1 X X 1 X X X 0 0 1 1 0 1 0 1 Function Drive 0 Selected (DR0 Drive 1 Selected (DR1 Drive 2 Selected (DR2 Drive 3 Selected (DR3 e e e e NEL Frequency Controls: 0) 0) 0) 0) Crystal Oscillator: The DP8473 is clocked by a single 24 MHz signal. An on-chip oscillator is provided, to enable the attachment of a crystal, or a clock. If a crystal is used, a 24 MHz fundamental mode, parallel resonant crystal should be used. This crystal should be specified to have less than 40X series resistance, and shunt capacitance of less than 7 pF. Low profile and surface mount crystals should be avoided due to their high start-up resistance, which could prohibit the circuit from oscillating. If an external oscillator circuit is used, it must have a duty cycle of at least 40–60%, and minimum input levels of 2.4V and 0.4V. The controller should be configured so that the clock is input into the OSC2 pin, and OSC1 is tied to ground. D1 Drive 1 Seeking: Same as above for drive 1. D0 Drive 0 Seeking: Same as above for drive 0. DATA REGISTER (Read/Write) This is the location through which all commands, data and status flow between the CPU and the DP8473. During the Command Phase the mP loads the controller’s commands into this register based on the Status Register Request for Master and Data Direction bits. The Result Phase transfers the Status Registers and header information to the mP in the same fashion. 9 Register Description (Continued) TABLE VI. Data Rate and Precompensation Programming Values D1 D0** DRVTYP Pin Data Rate MFM (kb/s) Normal Precomp* (ns) Alternate Precomp* (ns) FGND Pin Enabled RPM/LC Pin Level 0 0 X 500 125 125 FGND500 High 0 0 1 1 0 1 250 300 125 208 250 208 FGND250 FGND250 Low Low 1 1 0 0 0 1 250 250 125 125 250 250 FGND250 FGND250 Low Low 1 1 1 1 0 1 1000 1000 83 83 83 83 None None High Low *Normal values when PUMP/PREN pin set low; Alternate values when PUMP/PREN pin set high. **D0 and D1 are Data Rate Control Bits. DISK CHANGED REGISTER (Read Only) D7 Disk Changed: This bit is the latched complement of the Disk Changed input pin. If the DSKCHG input is low this bit is high. D6 – D0: These bits are reserved for use by the hard disk controller, thus during a read of this register, these bits are TRI-STATE. DRIVE CONTROL REGISTER (Write Only) D7 Motor Enable 3: This controls the Motor for drive 3, MTR3. When 0 the output is high, when 1 the output is low. (Note this signal is not output to a pin on 48 pin DIP version.) D6 Motor Enable 2: Same function as D7 except for drive 2’s motor. (Note this signal is not brought out to a pin on DIP.) D5 Motor Enable 1: This bit controls the Motor for drive 1’s motor. When this bit is 0 the MTR1 output is high. D4 Motor Enable 0: Same as D5 except for drive 0’s motor. D3 DMA Enable: When set to a 1 this enables the DRQ, DAK, INT pins. A zero disables these signals. D2 Reset Controller: This bit when set to a 0 resets the controller, and when a 1 enables normal operation. It does not affect the Drive Control or Data Rate Registers which are reset only by a hardware reset. D1 – D0 Drive Select: These two pins are encoded for the four drive selects, and are gated with the motor enable lines, so that only one drive is selected when it’s Motor Enable is active. (See Table V.) Result Phase Status Registers The Result Phase of a command contains bytes that hold status information. The format of these bytes are described below. Do not confuse these register bytes with the Main Status Register which is a read only register that is always available. The Result Phase status registers are read from the Data Register only during the Result Phase. STATUS REGISTER 0 (ST0) D7–D6 Interrupt Code: 00 e Normal Termination of Command. 01 e Abnormal Termination of Command. Execution of Command was started, but was not successfully completed. 10 e Invalid Command Issue. Command Issued was not recognized as a valid command. 11 e Ready changed state during the polling mode. DATA RATE REGISTER (Write Only) D7 – D2: Not used. D1, D0 Data Rate Select: These bits set the data rate and the write precompensation values for the disk controller. After a hardware reset these bits are set to 10 (250 kb/s). They are encoded as shown in Table VI. 10 Result Phase Status Registers (Continued) D0 Missing Address Mark: If bit 0 of ST2 is clear then the disk controller cannot detect any Address Field Address Mark after two disk revolutions. If bit 0 of ST2 is set then the disk controller cannot detect the Data Field Address Mark. D5 Seek End: Seek or Recalibrate Command completed by the Controller. (Used during Sense Interrupt command.) D4 Equipment Check: After a Recalibrate Command, Track 0 signal failed to occur. (Used during Sense Interrupt command.) D3 Not Used: 0 D2 Head Address (at end of Execution Phase). D1, D0 Drive Select (at end of Execution Phase). 00 e Drive 0 selected. 01 e Drive 1 selected. STATUS REGISTER 2 (ST2) D7 Not Used: 0 D6 Control Mark: Controller tried to read a sector which contained a deleted data address mark during execution of Read Data or Scan commands. Or, if a Read Deleted Data command was executed, a regular address mark was detected. D5 CRC Error in Data Field: Controller detected a CRC error in the Data Field. Bit 5 of ST1 is also set. D4 Wrong Track: Only set if desired sector not found, and the track number recorded on any sector of the current track is different from that stored in the Track Register. D3 Scan Equal Hit: ‘‘Equal’’ condition satisfied during any Scan Command. D2 Scan Not Satisfied: Controller cannot find a sector on the track which meets the desired condition during Scan Command. D1 Bad Track: Only set if the desired sector is not found, and the track number recorded on any sector on the track is different from that stored in the Track Register and the recorded track number is FF. D0 Missing Address Mark in Data Field: Controller cannot find the Data Field Address Mark during Read/Scan command. Bit 0 of ST1 is also set. 10 e Drive 2 selected. 11 e Drive 3 selected. STATUS REGISTER 1 (ST1) D7 End of Track: Controller transferred the last byte of the last sector without the TC pin becoming active. The last sector is the End Of Track sector number programmed in the Command Phase. D6 Not Used: 0 D5 CRC Error: If this bit is set and bit 5 of ST2 is clear, then there was a CRC error in the Address Field of the correct sector. If bit 5 of ST2 is set, then there was a CRC error in the Data Field. D4 Over Run: Controller was not serviced by the mP soon enough during a data transfer in the Execution Phase. TABLE VII. Maximum Time Allowed to Service an Interrupt or Acknowledge a DMA Request in Execution Phase Data Rate Time to Service 125 250 500 1000 62.0 ms 30.0 ms 14.0 ms 6.0 ms STATUS REGISTER 3 (ST3) D7 Not Used: 0 D6 Write Protect Status D5 Not Used: 1 D4 Track 0 Status D3 Not Used: 0 D2 Head Select Status D1, D0 Drive Selected: 00 e Drive 0 selected. 01 e Drive 1 selected. 10 e Drive 2 selected. 11 e Drive 3 selected. Time from rising edge of DRQ or INT to trailing edge of DAK or RD or WR. D3 Not Used: 0 D2 No Data: Three possible problems: 1) Controller cannot find the sector specified in the Command Phase during the execution of a Read, Write, or Scan command. An address mark was found however so it is not a blank disk. 2) Controller cannot read any Address Fields without a CRC error during Read ID command. 3) Controller cannot find starting sector during execution of Read A Track command. D1 Not Writable: Write Protect pin is active when a Write or Format command is issued. 11 Result Phase Status Registers (Continued) TABLE VIII. Summary of FDC Registers Bits Register 7 6 5 4 3 2 1 0 DCR (W) MTR3 Enable MTR2 Enable MTR1 Enable MTR0 Enable DMA Enable Software Reset Drive Select 1 Drive Select 0 MSR (R) Request for Master Data Direction Non-DMA Execution Command in Progress Drive 3 Seeking Drive 2 Seeking Drive 1 Seeking Drive 0 Seeking Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 X X X X X X Data Rate Bit 1 Data Rate Bit 0 DSKCHG Pin Inverse Z Z Z Z Z Z Z ST0 Interrupt Code Interrupt Code Seek End No Track 0 0 Head Addr DRV 1 (Exec.) DRV 0 (Exec.) ST1 End of Track 0 CRC Error Data Overrun 0 No Data WRT PRT Missing Address Mark 0 Control Mark CRC Error in Data Fld Wrong Track Scan Equal Hit Scan Not Satisfied Bad Track Missing Address Mark in Data Fld 0 Write Protect Status 1 Track 0 Status 0 Head Select Status DRV 1 (Exec.) DRV 0 (Exec.) DR (R/W) DRR (W) DKR (R) ST2 ST3 X e Don’t Care Z e TRI-STATE Processor Software Interface cuted properly and other pertinent information. The bytes are read in the order specified in the Command Description Table. A new command may be initiated by writing the Command Phase bytes after the last bytes required from the Result Phase have been read. If the next command requires selecting a different drive or changing the data rate the Drive Control and Data Rate Registers should be updated. If the command is the last command, then the software should deselect the drive. (Note as a general rule the operation of the controller core is independent of how the mP updates the Drive Control and Data Rate Registers. The software must ensure that manipulation of these registers is coordinated with the controller operation.) Bytes are transferred to and from the disk controller in different ways for the different phases in a command. COMMAND SEQUENCE The disk controller can perform various disk transfer, and head movement commands. Most commands involve three separate phases. Command Phase: The mP writes a series of bytes to the Data Register. These bytes indicate the command desired and the particular parameters required for the command. All the bytes must be written in the order specified in the Command Description Table. The Execution Phase starts immediately after the last byte in the Command Phase is written. Prior to performing the Command Phase, the Drive Control and Data Rate Registers should be set. Execution Phase: The disk controller performs the desired command. Some commands require the mP to read or write data to or from the Data Register during this time. Reading data from a disk is an example of this. Result Phase: The mP reads a series of bytes from the data register. These bytes indicate whether the command exe- During the Command Phase and the Result Phase, bytes are transferred to and from the Data Register. The Main Status Register is monitored by the software to determine when a data transfer can take place. Bit 6 of the Main Status Register must be clear and bit 7 must be set before a byte can be written to the Data Register during the Command Phase. Bits 6 and 7 of the Main Status Register must 12 Processor Software Interface (Continued) both be set before a byte can be read from the Data Register during the Result Phase. If there is information to be transferred during the Execution Phase, there are three methods that can be used. The DMA mode is used if the system has a DMA controller. This allows the mP to do other things during the Execution Phase data transfer. If DMA is not used, an interrupt can be issued for each byte transferred during the Execution Phase. If interrupts are not used, the Main Status Register can be polled to indicate when a byte transfer is required. INTERRUPT MODE If the non-DMA mode is selected, an interrupt will be generated in the Execution Phase when each byte is ready to be transferred. The Main Status Register should be read to verify that the interrupt is for a data transfer. Bits 5 and 7 of the Main Status Register will be set. The interrupt will be cleared when the byte is transferred to or from the Data Register. The mP should transfer the byte within the time allotted by Table VII. If the byte is not transferred within the time allotted, an Overrun Error will be indicated in the Result Phase when the command terminates at the end of the current sector. An interrupt will also be generated after the last byte is transferred. This indicates the beginning of the Result Phase. Bits 7 and 6 of the Main Status Register will be set and bit 5 will be clear. This interrupt will be cleared by reading the first byte in the Result Phase. DMA MODE If the DMA mode is selected, a DMA request will be generated in the Execution Phase when each byte is ready to be transferred. To enable DMA operations during the Execution Phase, the DMA mode bit in the Specify Command must be enabled, and the DMA signals must be enabled in the Drive Control Register. The DMA controller should respond to the DMA request with a DMA acknowledge and a read or write strobe. The DMA request will be cleared by the active edge of the DMA acknowledge. After the last byte is transferred, an interrupt is generated, indicating the beginning of the Result Phase. During DMA operations the Chip Select input must be held high. TC is asserted to terminate an operation. Due to the internal gating TC is only recognized when the DAK input is low. SOFTWARE POLLING If the non-DMA mode is selected and interrupts are not suitable, the mP can poll the Main Status Register during the Execution Phase to determine when a byte is ready to be transferred. In the non-DMA mode, bit 7 of the Main Status Register reflects the state of the interrupt pin. Otherwise, the data transfer is similar to the Interrupt Mode described above. Command Description Table READ DATA Command Phase READ ID Command Phase MT MFM SK 0 0 IPS X X X X 1 1 0 HD DR1 DR0 Track Number FORMAT A TRACK Command Phase 0 MFM 0 0 1 X X X X X 0 1 0 HD DR1 DR0 0 MFM 0 0 1 X X X X X 1 Number of Bytes per Sector Result Phase Drive Head Number Status Register 0 Sector Number Status Register 1 Format Gap Number of Bytes per Sector Status Register 2 Data Pattern End of Track Sector Number Track Number Intersector Gap Length Head Number Status Register 0 Data Length Sector Number Status Register 1 Bytes/Sector Status Register 2 Note 1 0 Result Phase Number of Sectors per Track Result Phase Track Number Status Register 0 Head Number Status Register 1 Sector Number Status Register 2 Bytes/Sector Track Number Head Number Sector Number Bytes/Sector 13 1 HD DR1 DR0 Command Description Table (Continued) READ DELETED DATA WRITE DATA Command Phase Command Phase MT MFM SK 0 1 IPS X X X X 1 0 0 HD DR1 DR0 0 0 0 IPS X X X X 1 0 1 HD DR1 DR0 MT MFM SK 1 0 IPS X X X X 0 0 Track Number Track Number Drive Head Number Drive Head Number Sector Number Sector Number Sector Number Number of Bytes per Sector Number of Bytes per Sector Number of Bytes per Sector End of Track Sector Number End of Track Sector Number End of Track Sector Number Intersector Gap Length Intersector Gap Length Intersector Gap Length Data Length Data Length X Sector Step Size Result Phase Result Phase Status Register 0 Status Register 0 Status Register 0 Status Register 1 Status Register 1 Status Register 1 Status Register 2 Status Register 2 Status Register 2 Track Number Track Number Track Number Head Number Head Number Head Number Sector Number Sector Number Sector Number Bytes/Sector Bytes/Sector Bytes/Sector MFM SK X WRITE DELETED DATA Command Phase 0 0 X X 0 1 0 HD DR1 DR0 MT MFM 0 0 1 IPS X X X X SCAN LOW OR EQUAL Command Phase 0 0 1 HD DR1 DR0 MT MFM SK 1 1 IPS X X X X 0 0 Track Number Track Number Track Number Drive Head Number Drive Head Number Sector Number Sector Number Sector Number Number of Bytes per Sector Number of Bytes per Sector Number of Bytes per Sector End of Track Sector Number End of Track Sector Number End of Track Sector Number Intersector Gap Length Intersector Gap Length Intersector Gap Length Data Length Data Length Result Phase Sector Step Size Result Phase Status Register 0 Status Register 0 Status Register 0 Status Register 1 Status Register 1 Status Register 1 Status Register 2 Status Register 2 Status Register 2 Track Number Track Number Track Number Head Number Head Number Head Number Sector Number Sector Number Sector Number Bytes/Sector Bytes/Sector Bytes/Sector 14 1 HD DR1 DR0 Drive Head Number Result Phase 1 HD DR1 DR0 Track Number READ A TRACK Command Phase 0 Command Phase MT MFM Drive Head Number Result Phase IPS SCAN EQUAL Command Description Table (Continued) SCAN HIGH OR EQUAL SENSE DRIVE STATUS Command Phase Command Phase MT MFM SK 1 1 IPS X X X X 1 0 1 HD DR1 DR0 Track Number 0 0 0 0 0 X X X X X Note 1: The IPS bit is only enabled if the IPS bit in the mode command is set. Otherwise this bit is a don’t care. 1 0 0 HD DR1 DR0 Note 3: These commands are additional enhanced commands. Result Phase Drive Head Number Status Register 3 Note: Mnemonic Definitions Sector Number X e DON’T CARE SPECIFY Command Phase Number of Bytes per Sector End of Track Sector Number 0 Intersector Gap Length 0 0 MFM e Data Encoding Scheme 0 0 Step Rate Time (N1) Sector Step Size 0 1 1 Motor Off Time (N2) Motor On Time (N3) Result Phase Note 2: Shaded byte only written or read if the extended track range mode is enabled in the Mode Command (ET) e 1. DMA MSN PTN e Most Significant Nibble Present Track Number MT e Multi-Track IPS e Implied Seek (In individual commands this bit is a don’t care unless the IPS bit in the mode command is set.) Status Register 0 SK e Skip Sector Status Register 1 HD e Head Number DRn e Drive to Select (encoded) Status Register 2 TMR e Motor/Head Timer Mode Track Number IAF e Index Address Field Head Number LW PR e Low Power Mode Sector Number ETR e Extended Track Range WLD e Wildcard in Scan Bytes/Sector RG e Enables the Read Gate Input on the DSKCHG pin for the Data Separator. SEEK Command Phase 0 0 X X 0 0 1 1 X X X X 1 1 DR1 DR0 New Track Number MSB of Track PU e Enables Charge Pump PUMP signal to be output on the PUMP/PREN pin. MODE Command Phase 0 0 0 0 Note 2 0 0 0 TMR IAF IPS 0 0 0 0 1 0 LW PR 1 ETR 0 0 0 0 0 0 1 0 WLD 0 0 0 0 0 1 0 Head Settle 0 RG 0 PU 0 0 1 Note 3 SET TRACK Command Phase RECALIBRATE Command Phase 0 0 0 0 0 0 0 0 0 0 1 0 1 1 DR1 DR0 0 R/W 1 0 0 0 0 1 1 0 MSB DR1 DR0 New Track Number Result Phase Value Note 3 INVALID COMMAND Command Phase SENSE INTERRUPT Command Phase 0 0 0 0 1 0 0 0 Result Phase Invalid Op Codes Result Phase Status Register 0 Status Register 0 Present Track Number (PTN) MSN PTN 0 0 0 0 Note 2 15 MSB e Selects whether the most significant or least significant byte of the track is read. 1 e MSB. R/W e Selects whether the track is written or read (Read e 0, Write e 1). Command Description found, bit 2 of ST1 (No Data) is set and an abnormal termination is indicated. In addition to this, if any Address Field track number is FF, bit 1 of ST2 (Bad Track) is set or if any Address Field track number is different from that specified in the Command Phase, bit 4 of ST2 (Wrong Track) is set. After finding the correct sector, the controller reads that Data Field. If a Deleted Data Mark is found and the SK bit is set, the sector is not read, bit 6 of ST2 (Control Mark) is set, and the next sector is searched for. If a deleted data mark is found and the SK bit is not set, the sector is read, bit 6 of ST2 (Control Mark) is set, and the read terminates with a normal termination. If a CRC error is detected in the Data Field, bit 5 is set in both ST1 and ST2 (CRC Error) and an abnormal termination is indicated. If no problems occur in the read command, the read will continue from one sector to the next in logical order (not physical order) until either TC is set or an error occurs. If a disk has not been inserted into the disk drive, there are many opportunities for the controller to appear to hang up. It does this if it is waiting for a certain number of disk revolutions for something. If this occurs, the controller can be forced to abort the command by writing a byte to the Data register. This will place the controller into the Result Phase. READ DATA The Read Data op-code is written to the data register followed by 8 bytes as specified in the Command Description Table. After the last byte is written, the controller starts looking for the correct sector header. Once the sector is found the controller sends the data to the mP. After one sector is finished, the Sector Number is incremented by one and this new sector is searched for. If MT (Multi-Track) is set, both sides of one track can be read. Starting on side zero, the sectors are read until the sector number specified by End of Track Sector Number is reached. Then, side one is read starting with sector number one. In DMA mode the Read Data command continues to read until the TC pin is set. This means that the DMA controller should be programmed to transfer the correct number of bytes. TC could be controlled by the mP and be asserted when enough bytes are received. An alternative to these methods of stopping the Read Data command is to program the End of Track Sector Number to be the last sector number that needs to be read. The controller will stop reading the disk with an error indicating that it tried to access a sector number beyond the end of the track. The Number of Data Bytes per Sector parameter is defined in Table IX. If this is set to zero then the Data Length parameter determines the number of bytes that the controller transfers to the mP. If the data length specified is smaller than 128 the controller still reads the entire 128 byte sector and checks the CRC, though only the number of bytes specified by the Data Length parameter are transferred to the mP. Data Length should not be set to zero. If the Number of Bytes per Sector parameter is not zero, the Data Length parameter has no meaning and should be set to FF (hex). If the Implied Seek Mode is enabled by both the Mode command and the IPS bit in this command, a Seek will be performed to the track number specified in the Command Phase. The controller will also wait the Head Settle time if the implied seek is enabled. After all these conditions are met, the controller searches for the specified sector by comparing the track number, head number, sector number, and number bytes/sector given in the Command Phase with the appropriate bytes read off the disk in the Address Fields. If the correct sector is found, but there is a CRC error in the Address Field, bit 5 of ST1 (CRC Error) is set and an abnormal termination is indicated. If the correct sector is not TABLE IX. Sector Size Selection Bytes/Sector Code Number of Bytes in Data Field 0 1 2 3 4 5 6 128 256 512 1024 2048 4096 8192 An interrupt will be generated when the Execution Phase of the Read Data command terminates. The values that will be read back in the Result Phase are shown in Table X. If an error occurs, the result bytes will indicate the sector being read when the error occurred. READ DELETED DATA This command is the same as the Read Data command except for its treatment of a Deleted Data Mark. If a Deleted TABLE X. Result Phase Termination Values with No Error MT 0 0 0 0 1 1 1 1 HD 0 0 1 1 0 0 1 1 Last Sector k EOT e EOT k EOT e EOT k EOT e EOT k EOT e EOT ID Information at Result Phase Track Head Sector B/S NC Ta1 NC Ta1 NC NC NC Ta1 NC NC NC NC NC 1 NC 0 Sa1 1 Sa1 1 Sa1 1 Sa1 1 NC NC NC NC NC NC NC NC EOT e End of Track Sector Number from Command Phase NC e No Change in Value S e Sector Number last operated on by controller T e Track Number programmed in Command Phase 16 Command Description (Continued) for each sector formatted during the Execution Phase. In other words, as the controller formats each sector, it will request four bytes through either DMA requests or interrupts. This allows for non-sequential sector interleaving. Some typical values for the programmable GAP size are shown in Table XI. The Format Command terminates when the index hole is detected a second time, at which point an interrupt is generated. Only the first three status bytes in the Result Phase are significant. Data Mark is read, the sector is read normally. If a Regular Data Mark is found and the SK bit is set, the sector is not read, bit 6 of ST2 (Control Mark) is set, and the next sector is searched for. If a Regular Data Mark is found and the SK bit is not set, the sector is read, bit 6 of ST2 (Control Mark) is set, and the read terminates with a normal termination. WRITE DATA The Write Data command is very similar to the Read Data command except that data is transferred from the mP to the disk rather than the other way around. If the controller detects the Write Protect signal, bit 1 of ST1 (Not Writable) is set and an abnormal termination is indicated. TABLE XI. Gap Length for Various Sector Sizes and Disk Types Format Table for Sector Size and Data Rate WRITE DELETED DATA This command is the same as the Write Data Command except a Deleted Data Mark is written at the beginning of the Data Field instead of the normal Data Mark. Sector Size Sector Code EOT Sector Gap Format Gap decimal hex hex hex hex FM 125 kb/s 128 128 256 512 1024 2048 00 00 01 02 03 04 12 10 08 04 02 01 07 10 18 46 C8 C8 09 19 30 87 FF FF MFM 250 kb/s 256 256 512 512 1024 2048 4096 01 01 02 02 03 04 05 12 10 08 09 04 02 01 0A 20 2A 1B 80 C8 C8 0C 32 50 50 F0 FF FF FM 250 kb/s 128 256 512 1024 2048 4096 00 01 02 03 04 05 1A 0F 08 04 02 01 07 0E 1B 47 C8 C8 1B 2A 3A 8A FF FF MFM 500 kb/s 256 512 512 1024 2048 4096 8192 01 02 02 03 04 05 06 1A 0F 12 08 04 02 01 0E 1B 1B 35 99 C8 C8 36 54 6C 74 FF FF FF Mode READ A TRACK This command is similar to the Read Data command except for the following. The controller starts at the index hole and reads the sectors in their physical order, not their logical order. Even though the controller is reading sectors in their physical order, it will still perform a comparison of the header ID bytes with the Data programmed in the Command Phase. The exception to this is the sector number. Internally, this is initialized to a one, and then incremented for each successive sector read. Whether or not the programmed Address Field matches that read from the disk, the sectors are still read in their physical order. If a header ID comparison fails, bit 2 of ST1 (No Data) is set, but the operation will continue. If there is a CRC error in the Address Field or the Data Field, the read will also continue. The command will terminate when it has read the number of sectors programmed in the EOT parameter. READ ID This command will cause the controller to read the first Address Field that it finds. The Result Phase will contain the header bytes that are read. There is no data transfer during the Execution Phase of this command. An interrupt will be generated when the Execution Phase is completed. FORMAT A TRACK This command will format one track on the disk. After the index hole is detected, data patterns are written on the disk including all gaps, address marks, Address Fields, and Data Fields. The exact details of the number of bytes for each field is controlled by the parameters given in the Format A Track command, and the IAF (Index Address Field) bit in the Mode command. The Data Field consists of the Fill Byte specified in the command, repeated to fill the entire sector. To allow for flexible formatting, the mP must supply the four Address Field bytes (track, head, sector, number of bytes) Format Table for PC Compatible Diskette Media Media Type 360k 1.2M 720k 1.44M Sector Size Sector Code EOT Sector Gap Format Gap decimal hex hex hex hex 512 512 512 512 02 02 02 02 09 0F 09 12 2A 1B 1B 1B 50 54 50 6C Note: Format Gap is the gap length used only for the Format command. 17 Command Description (Continued) TL/F/9384 – 10 Notes: FE* e Data pattern of FE, Clock pattern of C7 FC* e Data pattern of FC, Clock pattern of D7 FB* e Data pattern of FB, Clock pattern of C7 F8* e Data pattern of F8, Clock pattern of C7 A1* e Data pattern of A1, Clock pattern of 0A C2* e Data pattern of C2, Clock pattern of 14 All byte counts in decimal. All byte values in hex. CRC uses standard polynomial x16 a x12 a x5 a 1. FIGURE 6. IBM and ISO Formats Supported by the Format Command If the SK bit is set, sectors with deleted data marks are ignored. If all sectors read are skipped, the command will terminate with D3 of ST2 set (Scan Equal Hit). The result phase of the command is shown in Table XII. SCAN COMMANDS The Scan Commands allow data read from the disk to be compared against data sent from the mP. There are three Scan Commands to choose from: TABLE XII. Scan Command Termination Values Scan Equal Disk Data e mP Data Scan Less Than or Equal Disk Data s mP Data Scan Greater Than or Equal Disk Data t mP Data Each sector is interpreted with the most significant bytes first. If the Wildcard mode is enabled from the Mode command, an FF(hex) from either the disk or the mP is used as a don’t care byte that will always match equal. After each sector is read, if the desired condition has not been met, the next sector is read. The next sector is defined as the current sector number plus the Sector Step Size specified. The Scan command will continue until the scan condition has been met, or the End of Track Sector Number has been reached, or if TC is asserted. Command 18 Status Register 2 Conditions D2 D3 Scan Equal 0 1 1 0 Disk e mP Disk i mP Scan Low or Equal 0 0 1 1 0 0 Disk e mP Disk k mP Disk l mP Scan High or Equal 0 0 1 1 0 0 Disk e mP Disk l mP Disk k mP Command Description (Continued) ible by the mP. During an execution phase in Non-DMA Mode, bit 5 (Execution Mode) in the Main Status Register is set to 1. Upon entering Result Phase this bit is set to 0. Reasons 1 and 2 do not require the Sense Interrupt Status command. The interrupt is cleared by reading or writing information to the data register. Interrupts caused by reasons 3 and 4 are identified with the aid of the Sense Interrupt Status Command. This command resets the interrupt when the command byte is written. Use bits 5, 6 and 7 of ST0 to identify the cause of the interrupt as shown in Table XIII. SEEK There are two ways to move the disk drive head to the desired track number. Method One is to enable the Implied Seek Mode. This way each individual Read or Write command will automatically move the head to the track specified in the command. Method Two is using the Seek Command. During the Execution Phase of the Seek Command, the track number to seek to is compared with the present track number and a step pulse is produced to move the head one track closer to the desired track number. This is repeated at the rate specified by the Specify Command until the head reaches the correct track. At this point an interrupt is generated and a Sense Interrupt Command is required to clear the interrupt. During the Execution Phase of the Seek Command the only indication via software that a Seek Command is in progress is bits 0 – 3 (Drive Busy) of the Main Status Register. Bit 4 of the Main Register (Controller Busy) is not set. While the internal microengine is capable of multiple seeks on 2 or more drives at the same time since the drives are selected via the Drive Control Register in software, software should ensure that only one drive is seeking at one time. No other command except the Sense Interrupt Command should be issued while a Seek Command is in progress. If the extended track range mode is enabled, a fourth byte should be written in the Command Phase to indicate the four most significant bits of the desired track number. Otherwise, only three bytes should be written. TABLE XIII. Status Register 0 Termination Codes Status Register 0 Interrupt Code Seek End Cause D7 D6 D5 1 1 0 Internal Ready Went True 0 0 1 Normal Seek Termination 0 1 1 Abnormal Seek Termination TABLE XIV. Step, Head Load and Unload Timer Definitions (500 kb/s MFM) Timer Mode 1 Value Range Mode 2 Value Step Rate (16 b N1) 1 – 16 (16 b N1) 1 – 16 Motor Off N2 c 16 0 – 240 N2 c 512 0 – 7680 Motor On N3 c 2 0 – 254 N3 c 32 0 – 4064 RECALIBRATE The Recalibrate Command is very similar to the Seek Command. It is used to step a drive head out to track zero. Step pulses will be produced until the track zero signal from the drive becomes true. If the track zero signal does not go true before 77 step pulses are issued, an error is generated. If the extended track range mode is enabled, an error is not generated until 3917 pulses are issued. Recalibrations on more than one drive at a time should not be issued for the same reason as explained in the Seek Command. No other command except the Sense Interrupt Command should be issued while a Recalibrate Command is in progress. Unit Range ms ms ms Issuing a Sense Interrupt Status Command without an interrupt pending is treated as an invalid command. If the extended track range mode is enabled, a third byte should be read in the Result Phase which will indicate the four most significant bits of the Present Track Number. Otherwise, only two bytes should be read. SPECIFY The Specify Command sets the initial values for each of the three internal timers. The timer programming values are shown in Table XIV. The Head Load and Head Unload timers are artifacts of the mPD765A. These timers determine the delay from loading the head until a read or write command is started, and unloading the head sometime after the command was completed. Since the DP8473’s head load signal is now the software controlled Motor lines in the Drive Control Register, these timers only provide some delay from the initiation of a command until it is actually started. These times can be extended by setting the TMR bit in the Mode Command. The Step Rate Time defines the time interval between adjacent step pulses during a Seek, Implied Seek, or Recalibrate Command. The times stated in the table are affected by the Data Rate. The values in the table are for 500 kb/s MFM (250 kb/s FM) and 1 Mb/s MFM (500 kb/s FM). For a 300 kb/s MFM data rate (150 kb/s FM) these values should be multiplied by 1.6667, and for 250 kb/s MFM (125 kb/s FM) these values should be doubled. The choice of DMA or Non-DMA operation is made by the NON-DMA bit. When this bit is 1 then Non-DMA mode is selected, and when this bit is 0, the DMA mode is selected. This command does not generate an interrupt. SENSE INTERRUPT STATUS An interrupt is generated by the controller when any of the following conditions occur: 1. Upon entering the Result Phase of: a. Read Data Command b. Read Deleted Data Command c. Write Data Command d. Write Deleted Data Command e. Read a Track Command f. Read ID Command g. Format Command h. Scan Commands 2. During data transfers in the Execution Phase while in the Non-DMA mode 3. Internal Ready signal changes state (only occurs immediately after a hardware or software reset). 4. Seek or Recalibrate Command termination An interrupt generated for reasons 1 and 2 above occurs during normal command operations and are easily discern19 Command Description (Continued) SENSE DRIVE STATUS PU (PUMP Pulse Output): When set enables a signal that indicates when the Data Separator’s charge pump is making a phase correction. This is a series of pulses. This signal is output on the PUMP/PREN pin when this bit is set. This is intended as a test mode to aid in evaluation of the Data Separator. (Default mode is off) RG (Read Gate): Like the PUMP output, when this bit is set it enables a pin (the DSKCHG pin) to act as an external Read Gate signal for the Data Separator. This is intended as a test mode to aid in evaluation of the Data Separator. (Default mode is off) This two byte command obtains the status of a disk drive. Status Register 3 is returned in the result phase and contains the drive status. This command does not generate an interrupt. MODE This command is used to select the special features of the controller. The bits for the command phase bytes are shown in the command description table, and their function is described below. The defaults after a hardware or software reset are shown by the ‘‘bullets’’ to the left of each item. # TMR e 0 (motor TiMeR): Timers for motor on and motor off are defined for Mode 1. (See Specify Command) TMR e 1: Timers for motor on and motor off are defined for Mode 2. (See Specify Command) SET TRACK This command is used to inspect or change the value of the internal Present Track Register. This could be useful for recovery from disk mis-tracking errors, where the real current track could be read through the Read ID command and then the Set Track Command can set the internal present track register to the correct value. The first byte of the command contains the command opcode and the R/W bit. If the R/W bit is low, a track register is to be read. In this case, the result phase contains the value in the internal register specified, and the third byte of the command is a dummy byte. If the R/W bit is high, data is written to a track register. In this case the 3rd byte of the command phase is forced into the specified internal register, and the result phase contains the new byte value written. The particular track register chosen to operate on is determined by the least significant 3 bits of the second byte of the command. The two LSB’s select the drive (DR1, DR0), and the next bit (MSB) determines whether the least significant byte (MSB e 0) or the most significant byte (MSB e 1) of the track register is to be read/written. When not in the extended track range mode, only the LSB track register need be updated. In this instance, the MSB bit is set to 0. This command does not generate an interrupt. LW PR (LoW PoweR) # 00 Completely disable the low power mode. (default) 01 Go into low power mode 500 ms after the head unload timer times out. 10 Go into low power mode now. 11 Not Used. # IAF e 0 (Index Address Format): The controller will format tracks with the Index Address Field included. (IBM Format) IAF e 1: The controller will format tracks without including the Index Address Mark Field. (ISO Format) # IPS e 0 (ImPlied Seek): The implied seek bit in the command is ignored. IPS e 1: The implied seek bit in the command is enabled so that if the bit is set in the command, a Seek will be performed automatically. # ETR e 0 (Extended Track Range): Header format is the IBM System 34 (double density) or System 3740 (single density). ETR e 1: Header format is the same as above but there are 12 bits of track number. The MSB’s of the track number are in the upper four bits of the head number byte. INVALID COMMAND If an invalid command (i.e., a command not defined) is received by the controller, the controller will respond with ST0 in the Result Phase. The Controller does not generate an interrupt during this condition. Bits 6 and 7 in the Main Status Register are both set to one’s indicating to the processor that the Controller is in the Result Phase and the contents of ST0 must be read. When the system reads ST0 it will find an 80(hex) indicating an invalid command was received. # WLD e 0 (scan WiLD card): An FF(hex) from either the mP or the disk during a Scan Command is interpreted as a wildcard character that will always match true. WLD e 1: The Scan commands do not recognize FF(hex) as a wildcard character. Head Settle: Time allowed for head to settle after an Implied Seek. Time e N c 4 ms, (0 ms–60 ms). (Based on 500 kb/s and 1 Mb/s MFM data rates. Double for 250 kb/s.) Typical Performance Characteristics Typical Window Margin Performance Characteristics at 250 kb/s MFM Typical Window Margin Performance Characteristics at 500 kb/s MFM TL/F/9384–18 TL/F/9384 – 19 20 Absolute Maximum Ratings (Notes 1 and 2) Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) Max 4.5 5.5 V 0 a 70 §C Operating Temperature (TA) b 0.5V to a 7V Supply Voltage (VCC) b 0.5V to VCC a 0.5V DC Input Voltage (VIN) b 0.5V to VCC a 0.5V DC Output Voltage (VOUT) b 65§ C to a 165§ C Storage Temperature Range (TSTG) Package Power Dissipation (PD) 750 mW Lead Temperature (TL) (Soldering, 10 seconds) 260§ C lVCC – VCCAl Min ESD Tolerance: CZAP e 100 pF RZAP e 1.5 kX (Note 5) 1500 Units V 0.6V DC Electrical Characteristics VCC e 5V g 10% unless otherwise specified (Note 3) Symbol Parameter Conditions Min Max High Level Input Voltage (except OSC2/CLK) VIL Low Level Input Voltage (except OSC2/CLK) 0.8 V IIN Input Current (except OSC pins) VIN e VCC or GND g 1.0 mA ICCA Average VCCA Supply Current VIN e 2.4V or 0.5V, IO e 0 mA (Note 4) 20.0 mA Quiescent VCCA Supply Current in Low Power Mode VIN e VCC or GND, IO e 0 mA (Note 4) 400 mA Average VCC Supply Current VIN e 2.4V or 0.5V, IO e 0 mA (Note 4) 20.0 mA Quiescent VCC Supply Current in Low Power Mode VIN e VCC or GND, IO e 0 mA (Note 4) 2 mA ICC 2.0 Units VIH V OSCILLATOR PINS (OSC2/CLK) IOSC OSC2 Input Current (OSC1 e GND) VIN e VCC or GND VIH OSC2 High Level Input Voltage OSC1 e GND VIL OSC2 Low Level Input Voltage OSC1 e GND g 1.6 mA 2.4 V 0.4 V MICROPROCESSOR INTERFACE PINS (D0–D7, INT, DAK, TC, DRQ, RD, WR, CS, A0 – A3) VOH High Level Output Voltage IOUT e b20 mA IOUT e b4.0 mA VOL Low Level Output Voltage IOUT e 20 mA IOUT e 12 mA IOZ Output TRI-STATEÉ Leakage Current VOUT e VCC or GND VCC b 0.1 3.5 V V 0.1 0.4 V V g 10.0 mA DISK DRIVE INTERFACE PINS (MTR0 – 3, DR0–3, WDATA, WGATE, RDATA, DIR, HDSEL, TRK0, WRTPRT, RPM, STEP, DSKCHG, INDEX) VH Input Hysteresis VOL Low Level Output Voltage IOUT e 48 mA 250 Typical ILKG Output High Leakage Current VOUT e VCC or GND VIH High Level Input Voltage VIL Low Level Input Voltage mV 0.4 V g 100 mA 0.8 V 2.2 Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: These DC Electrical Characteristics are measured staticly, and not under dynamic conditions. Note 4: ICC is measured with a 0.1 mF supply decoupling capacitor to ground. Note 5: Value based on test complying with NSC SOP5-028 human body model ESD testing using the ETS-910 tester. 21 V Phase Locked Loop Characteristics VCC e 5V g 10%, FXTAL e 24 MHz unless otherwise specified Conditions Typ Units VREF Symbol SETCUR Pin Reference Voltage R1 e 5.6 kX, VCC e 5V 1.1 V KVCO VCO Gain (Note 5) tDATA e 1 ms g 10% 25 Mrad/s/V R1 Recommended Pump Resistor Range 3 –12 kX KP(UP) Charge Pump Up Current Gain (IREF/IP(UP)) (Note 6) R1 e 5.6 kX 2.50 (none) KP(DWN) Charge Pump Down Current Gain (IREF/IP(DWN)) (Note 6) R1 e 5.6 kX 2.25 (none) KPLL Internal Phase Locked Loop Gain (Note 7) (R1 e 5.6 kX) Pump Up Pump Down 75 70 Mrad Mrad TSW Parameter Static Window (Note 8) 250 kb/s 500 kb/s 1.0 Mb/s TDW Dynamic Window Margin Early Late 1075 530 259 872 440 234 (R1 e 5.6 kX) (Note) 70 ns ns ns % Note: Measurements made with a repeating ‘DB6’’ data pattern with reverse write precompensation, using recommended filter values for the configuration shown in Figure 4c. 25§ C, 5.0V, 0% MSV. Note 5: The VCO gain is measured at the 1.0 Mb/s data rate by forcing the data period over a range from 900 ns to 1100 ns, and measuring the resulting voltage on the filter pin. The best straight line gain is fit to the measured points. Note 6: This is the current gain of the charge pump, which is defined as the output current divided by the current through R1. Note 7: This is the product of: VREF c KP c KVCO. The total variation in this specification indicates the total loop gain variation contributed by the internal circuitry. The KVCO portion of this specification is measured at the 1.0 Mb/s data rate by forcing the data period over a range of 900 ns to 1100 ns, and measuring the resultant KVCO. KP is measured by forcing the Filter pin to 2.1V and measuring the ratio of the charge pump current over the input current. Note 8: The DP8473 is guaranteed to correctly decode a single shifted clock pulse at the end of a long series of non-shifted preamble bits as long as the single shifted pulse is shifted less than the amount specified in TSW. The length of the preamble is long enough for the PLL to lock. The filter components used are those in Table II. 22 AC Electrical Characteristics MICROPROCESSOR READ TIMING TL/F/9384 – 11 Symbol Parameter Min Max Units tAR Address Valid prior to Read Strobe 10 ns tRA Address Hold from Read Strobe 0 ns tRR Read Strobe Width 75 ns tRD Read Strobe and Chip Select to Data Valid 75 ns tADR Address Valid to Read Data 85 ns tDR Data Hold from Read Strobe to High Impedance (TRI-STATE Note) 60 ns tRI Clear INT from Read Strobe 65 ns 5 TRI-STATE Note: This limit includes the RC delay inherent in our test method. This signal will typically turn off within 15 ns, enabling other devices to drive this signal with no contention. MICROPROCESSOR WRITE TIMING TL/F/9384 – 12 Symbol Parameter Min Max Units tAW Address Valid to Leading Edge of Write Strobe 10 ns tWA Address Hold from Write Strobe 0 ns tWW Write Strobe Width 25 ns tADW Address Valid to Trailing Edge of Write Strobe 35 ns tDW Data Setup to End of Write Strobe or Chip Select 20 ns tWD Data Hold from Write Strobe 12 ns tWI Clear INT from Write Strobe 65 23 ns AC Electrical Characteristics (Continued) OSC2/CLOCK AND RESET TIMING TL/F/9384 – 13 Symbol Parameter tH Clock High Time tL tRW Min Max Units 16 ns Clock Low Time 16 ns Reset Pulse Width 100 ns DMA TIMING (Note 9) TL/F/9384 – 14 Symbol Parameter Min Max Units 115 ns tAQ End of DRQ from DAK tQA DAK Assertion from DRQ 10 ns tAA DAK Pulse Width 75 ns tQR DRQ to Read or Write Strobe 10 ns tTT TC Strobe Width 50 ns tTQ Time after Last DRQ That TC Must Be Asserted By (Note 10) ns Note 9: DMA Acknowledge is sufficient to acknowledge a data transfer. Read or Write Strobes are neccessary only if data is to be presented to the data bus. If Read/Write Strobes are applied, then they and the Acnowledge must be removed within 1 ms of each other. Note 10: TC is is the terminal count pin which terminates the data transfer operation. There are several constraints placed on the timing of TC. 1) TC is enabled by DAK, so TC must be pulsed while DAK is low. 2) TC must occur before ((1/data rate x 8) b 1 ms). Data rate is the exact data transfer rate being used. DRIVE READ TIMING TL/F/9384 – 15 Symbol tRDW Parameter Min Read Data Pulse Width 25 24 Max Units ns AC Electrical Characteristics (Continued) DRIVE WRITE TIMING TL/F/9384 – 16 Symbol Parameter Conditions Min 250 kb/s (MFM) 300 kb/s (MFM) 500 kb/s (MFM) 1000 kb/s(MFM) 500 416 250 225 Max Units ns ns ns ns tWD Write Data Pulse Width tHDS Head Select Setup to Write Gate Assertion 50 ms tHDH Head Select Hold from Write Gate 15 ms Note 11: Whenever WGATE is asserted the WDATA line is active. At the end of each write one dummy byte is written before WGATE is deasserted. DRIVE TRACK ACCESS TIMING TL/F/9384 – 17 Symbol Parameter Min tDST Direction Setup prior to Step tDH Direction Hold from End of Step tSTP Step Pulse Width 8 tIW Index Pulse Width 100 tDRV Drive Select or Motor Time from Write Strobe Max 6 Units ms 1 step time 25 ms ns 100 ns AC Test Conditions (Notes 11, 12, 13) Input Pulse Levels Input Rise and Fall Times Input and Output Reference Levels TRI-STATE Reference Levels Capacitance TA e 25§ C, f e 1 MHz (Note 14) GND to 3V 6 ns 1.3V Active High b 0.5V Active Low a 0.5V Typ Units CIN Symbol Input Capacitance Parameter 5 pF COUT Output Capacitance 8 pF Note 14: This parameter is not 100% tested. Note 11: CL e 100 pF, includes jig and scope capacitance. Note 12: S1 e open for push-pull outputs. S1 e VCC for high impedance to active low and active low to high impedance measurements. S1 e GND for high impedance to active high and active high to high imepedance measurements. RL e 1.0 kX for mP interface pins. Note 13: For the Open Drain Drive Interface Pins S1 e VCC and RL e 150X. TL/F/9384 – 20 26 Physical Dimensions inches (millimeters) Plastic Dual-In-Line Package (N) Order Number DP8473N NS Package Number N48A 27 DP8473 Floppy Disk Controller PLUS-2 Physical Dimensions inches (millimeters) (Continued) Lit. Ý 103175 Plastic Leaded Chip Carrier (V) Order Number DP8473V NS Package Number V52A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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