LM9811 10-Bit Greyscale/30-Bit Color Linear CCD Sensor Processor General Description Features The LM9811 is a high performance integrated signal processor/digitizer for linear CCD image scanners. The LM9811 performs all the analog processing (correlated double sampling for black level and offset compensation, pixel-by-pixel gain (shading) correction, and 10-bit analog-to-digital conversion) necessary to maximize the performance of a wide range of linear CCD sensors. The LM9811 can be digitally programmed to work with a wide variety of CCDs from different manufacturers. An internal configuration register sets CCD and sampling timing to maximize performance, simplifying the design and manufacturing processes. The LM9811 can be used with parallel output color CCDs. A signal inversion mode eases use with CIS sensors. For complementary voltage reference see the LM4041. n 1.5 Million pixels/s conversion rate n Pixel-rate shading correction for individual pixels maximizes dynamic range and resolution, even on “weak” pixels n Implements Correlated Double Sampling for minimum noise and offset error n Reference and signal sampling points digitally controlled in 40ns increments for maximum performance n Generates all necessary CCD clock signals n Compatible with a wide range of linear CCDs n Supports some Contact Image Sensors (CIS) n TTL/CMOS input/output compatible n Resolution: Applications n n n n Key Specifications n Pixel Conversion Rate: Color and Greyscale Flatbed and Sheetfed Scanners Fax and Multifunction Peripherals Digital Copiers General Purpose Linear CCD Imaging 10 Bits 1.5MHz n Supply Voltage: +5V ± 5% n Supply Voltage (Digital I/O): +3.3V ± 10% or +5V ± 5% n Power Dissipation: 260mW (max) Connection Diagrams DS012813-1 DS012813-2 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. MICROWIRE™ is a trademark of National Semiconductor Corporation. SPI™ is a trademark of Motorola, Inc. © 1999 National Semiconductor Corporation DS012813 www.national.com LM9811 10-Bit Greyscale/30-Bit Color Linear CCD Sensor Processor April 1998 Block Diagram DS012813-3 Ordering Information Commercial (0˚C ≤ TA ≤ +70˚C) www.national.com Package LM9811CCV V52A 52-Pin Plastic Leaded Chip Carrier LM9811CCVF VEG52A 52-Pin Thin Quad Flatpack 2 Absolute Maximum Ratings (Notes 1, 2) Operating Ratings (Notes 1, 2) + Positive Supply Voltage (V = VA = VD = VD(I/O) with Respect to 6.5V GND = AGND = DGND = DGND(I/O) Voltage on any Input or Output Pin 0.3V to V+ +0.3V ± 25 mA Input Current at any Pin (Note 3) ± 50 mA Package Input Current (Note 3) (Note 4) Package Dissipation at TA = 25˚C ESD Susceptibility (Note 5) Human Body Model 2000V Soldering Information (Note 6) Infrared, 10 seconds LM9811CCV 300˚C LM9811CCVF 220˚C Storage Temperature −65˚C to +150˚C Operating Temperature Range LM9811CCV, LM9811CCVF VA Supply Voltage VD Supply Voltage VD(I/O) Supply Voltage |VA–VD| VA–VD(I/O) OS, REF IN Voltage Range CD0–CD7, MCLK, SYNC, SDI, SCLK, CS, RD, Voltage Range TMIN ≤ TA ≤ TMAX 0˚C ≤ TA ≤ +70˚C +4.75V to +5.25V +4.75V to +5.25V +2.7V to +5.25V ≤ 100 mV ≥ −100 mV −0.05V to VA + 0.05V −0.05V to VD(I/O) + 0.05V Electrical Characteristics The following specifications apply for AGND = DGND = DGND(I/O) = 0V, VA = VD = +5.0VDC, VD(I/O) = +5.0 or +3.0VDC, REF IN = +1.225VDC, fMCLK = 20MHz, RS = 25Ω. All LSB units are ADC LSBs unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. (Note 8) Symbol Parameter Conditions Typical Limits Units (Note 9) (Note 10) (Limits) CCD SOURCE REQUIREMENTS FOR FULL SPECIFIED ACCURACY AND DYNAMIC RANGE (Note 11) Maximum Peak CCD Differential VGA Gain = 0 dB 1.1 VWHITE Signal Range VGA Gain = 9 dB 0.4 VRFT Maximum CCD Reset FeedThrough Amplitude 2 V (min) V (min) V (min) ADC CHARACTERISTICS (Note 16) Resolution with No Missing Codes fMCLK = 12MHz = 12MHz ILE Integral Linearity Error (Note 12) fMCLK DNL Differential Non-Linearity fMCLK = 12MHz 9 Bits (min) +4.0 LSB (max) −3.0 LSB (min) +2.0 LSB (max) 8 Bits (min) 2.8 V/V (min) 1.4 % (max) 4 Bits (min) 8.5 dB (min) ± 0.15 dB (max) ± 0.9 LSB PGA CHARACTERISTICS Monotonicity PGA Adjustment Range 2.95 Gain Error at any Gain (Note 14) VGA CHARACTERISTICS Monotonicity VGA Adjustment Range 8.95 Gain Error at any Gain (Note 15) OFFSET TRIM CHARACTERISTICS Offset DAC LSB Size In Units of ADC LSBs Offset DAC DNL In Units of Offset DAC LSBs Offset Add Magnitude In Units of ADC LSBs 1.7 ± 0.25 8 LSB 6.4 LSB (min) 10.0 LSB (max) ± 3.0 % (max) SYSTEM CHARACTERISTICS Full Channel Gain Error Pre-PGA Offset Error (In ADC LSBs) Post-PGA Offset Error (In ADC LSBs) VGA Gain = 1, PGA Gain = 1 VGA Gain = 1, Offset DAC = 0 Offset Add = 0 ± 0.6 ±4 ±4 LSB LSB REFERENCE AND ANALOG INPUT CHARACTERSTICS (Note 7) OS Input Capacitance 5 3 pF www.national.com Electrical Characteristics (Continued) The following specifications apply for AGND = DGND = DGND(I/O) = 0V, VA = VD = +5.0VDC, VD(I/O) = +5.0 or +3.0VDC, REF IN = +1.225VDC, fMCLK = 20MHz, RS = 25Ω. All LSB units are ADC LSBs unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. (Note 8) Symbol Parameter Conditions Typical Limits Units (Note 9) (Note 10) (Limits) 20 nA (max) REFERENCE AND ANALOG INPUT CHARACTERSTICS (Note 7) OS Input Leakage Current RREF REF IN Measured with OS = 2.45VDC ADC Reference Ladder (REF OUTHI 2 950 to REF IN) Impedance Reference Voltage (Note 13) 1.225 500 Ω (min) 2000 Ω (max) 1.19 V (min) 1.26 V (max) DC and Logic Electrical Characteristics The following specifications apply for AGND = DGND = DGND(I/O) = 0V, VA = VD = +5.0VDC, VD(I/O) = +5.0 or +3.0VDC, REF IN = +1.225VDC, fMCLK = 20MHz, Rs = 25Ω. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. Symbol Parameter Conditions CD0–CD7, MCLK, SYNC, SDI, SCLK, CS , RD DIGITAL INPUT CHARACTERISTICS VD(I/O) = 5.25V VIN(1) Logical “1” Input Voltage VD(I/O) = 3.6V VD(I/O) = 4.75V Logical “0” Input Voltage VIN(0) VD(I/O) = 2.7V VIN = VD Input Leakage Current IIN VIN = DGND CIN Input Capacitance Typical Limits Units (Note 9) (Note 10) (Limits) 2.0 V (min) IOUT COUT Logical “0” Output Voltage TRI-STATE ® Output Current (DD0–DD9 only) TRI-STATE Output Capacitance V (max) 0.7 V (max) µA −0.1 µA 5 pF VD(I/O) = 5.25V, IOUT = 1.6 mA VD(I/O) = 3.6V, IOUT = 1.6 mA VOUT = DGND VOUT = VD V (min) 0.8 0.1 DD0–DD9, EOC , CCLK, SDO DIGITAL OUTPUT CHARACTERISTICS VD(I/O) = 4.75V, IOUT = −360 µA VD(I/O) = 4.75V, IOUT = −10 µA VOUT(1) Logical “1” Output Voltage VD(I/O) = 2.7V, IOUT = −360 µA VD(I/O) = 2.7V, IOUT = −10 µA VOUT(0) 2.0 2.4 V (min) 4.4 V (min) 2.1 V (min) 2.5 V (min) 0.4 V (max) 0.4 V (max) 0.1 µA −0.1 µA 5 pF φ1, φ2, RS, TR DIGITAL OUTPUT CHARACTERISTICS VD = 4.75V, IOUT = −360 µA VOUT(1) Logical “1” Output Voltage VD = 4.75V, IOUT = −10 µA VOUT(0) Logical “0” Output Voltage VD = 5.25V, IOUT = 1.6 mA 2.4 V (min) 4.4 V (min) 0.4 V (max) 38 mA (max) 8 mA (max) POWER SUPPLY CHARACTERISTICS IA ID ID(I/O) Analog Supply Current Digital Supply Current Digital I/O Supply Current www.national.com Operating 25 Standby 50 Operating 6 µA Standby 65 Operating, VD(I/O) = 5.0V Operating, VD(I/O) = 3.0V Standby, VD(I/O) = 5.0V or 3.0V 3.1 6 mA (max) 1.6 4 mA (max) 4 1.7 µA mA AC Electrical Characteristics, MCLK Independent The following specifications apply for AGND = DGND = DGND(I/O) = 0V, VA = VD = VD(I/O) = +5.0VDC, REF IN = +1.225VDC, fMCLK = 20MHz, tMCLK = 1/fMCLK, tr = tf = 5ns, Rs = 25Ω, CL(databus loading) = 50 pF/pin. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. Symbol fMCLK Parameter Conditions Typical Limits Units (Note 9) (Note 10) (Limits) Maximum MCLK Frequency (Note 16) 20 MHz (min) Minimum MCLK Frequency 1 MHz (max) MCLK Duty Cycle 30 40 % (min) 70 60 % (max) tA SYNC Setup of MCLK 5 10 ns (min) tCDSETUP Correction Data Valid to CLK Setup 14 20 ns (min) tCDHOLD Correction Data Valid to CLK Hold −12 0 ns (min) tD1H, tD0H RD High to DD0–DD9 TRI-STATE 5 15 ns (max) tDACC Access Time Delay from RD Low to DD0–DD9 Data Valid 15 30 ns (max) fSCLK Maximum SCLK Frequency 8 MHz (min) SCLK Duty Cycle 40 % (min) 60 % (max) tSDI SDI Set-Up Time from SCLK Rising Edge 3 10 ns (min) tHDI SDI Hold Time from SCLK Rising Edge 2 15 ns (min) tDDO Delay from SCLK Falling Edge to SDO Data Valid 25 55 ns (max) tHDO SDO Hold Time from SCLK Falling Edge 55 ns (max) 5 ns (min) tDELAY DELAY from SCLK Falling Edge to CS Rising or Falling Edge 5 10 ns (min) tSETUP Set-Up Time of CS Rising or Falling Edge to SCLK Rising Edge 0 10 ns (min) tS1H, tS0H Delay from CS Rising Edge to SDO TRI-STATE 25 50 ns (max) tRDO tFDO SDO Rise Time, TRI-STATE to High SDO Rise Time, Low to High SDO Fall Time, TRI-STATE to Low SDO Fall Time, High to Low RL = 3k, CL = 25pF RL = 3k, CL = 50pF RL = 3k, CL = 50pF RL = 3k, CL = 50pF 30 20 ns 20 ns 20 ns 20 ns AC Electrical Characteristics, MCLK Dependent The following specifications apply for AGND = DGND = DGND(I/O) = 0V, VA = VD = VD(I/O) = +5.0VDC, REF IN = +1.225VDC, fMCLK = 20MHz, tMCLK = 1/fMCLK, tr = tf = 5ns, Rs = 25Ω, CL(databus loading) = 50 pF/pin. Refer to Table 2. Configuration Register Parameters for limits labelled C.R. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. Symbol tSTART Parameter Conditions MCLK to first φ1 High Typical Limits Units (Note 9) (Note 10) (Limits) 50ns 1 tMCLK Standard CCD Mode 400ns 8 tMCLK Even/Odd CCD Mode 800ns tφ φ1, φ2 Clock Period 16 tMCLK tTRWIDTH Transfer Pulse (TR) Width C.R. µs tGUARD φ1 to TR, TR to φ1 Guardband C.R. ns tRSWIDTH Reset Pulse (RS) Width C.R. ns C.R. ns tRS Falling Edge of φ1 to RS Standard CCD Mode Either Edge of φ1 to RS Even/Odd CCD Mode 5 www.national.com AC Electrical Characteristics, MCLK Dependent (Continued) The following specifications apply for AGND = DGND = DGND(I/O) = 0V, VA = VD = VD(I/O) = +5.0VDC, REF IN = +1.225VDC, fMCLK = 20MHz, tMCLK = 1/fMCLK, tr = tf = 5ns, Rs = 25Ω, CL(databus loading) = 50 pF/pin. Refer to Table 2. Configuration Register Parameters for limits labelled C.R. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. Symbol tS/HREF tS/HSIG tS/HWIDTH Parameter Conditions Falling Edge of φ1 to Ref. Sample Standard CCD Mode Either Edge of φ1 to Ref. Sample Even/Odd CCD Mode Falling Edge of φ1 to Sig. Sample Standard CCD Mode Either Edge of φ1 to Sig. Sample Even/Odd CCD Mode Sample Pulse Width tSYNCLOW SYNC Low Between Lines SYNC Setup of φ1 to End Line tCCLKWIDTH CCLK Pulse Width tDATAVALID Data Valid Time from EOC Low tEOCWIDTH EOC Pulse Width φ1 and φ2 Frequency Limits Units (Note 10) (Limits) C.R. ns C.R. ns 1 tMCLK 50ns (Acquisition Time) tB Typical (Note 9) 100ns 250ns 2 tMCLK (min) 2 tMCLK (max) 5 tMCLK 300 ns (min) tMCLK 250ns 5 Standard CCD Mode 2.5MHz fMCLK/8 Hz Even/Odd CCD Mode 1.25MHz fMCLK/16 Hz 50 % φ1 and φ2 Duty Cycle Electrical Characteristics (Notes) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND = AGND = DGND = DGND(I/O) = 0V, unless otherwise specified. Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > VA or VD), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can simultaneously safely exceed the power supplies with an input current of 25 mA to two. Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, θJA and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJmax–TA)/θJA. TJmax = 150˚C for this device. The typical thermal resistance (θJA) of this part when board mounted is 52˚C/W for the V52A PLCC package, and 70˚C/W for the VEG52A TQFP package. Note 5: Human body model, 100pF capacitor discharged through a 1.5 kΩ resistor. Note 6: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any National Semiconductor Linear Data Book for other methods of soldering surface mount devices. Note 7: A Zener diode clamps the OS analog input to AGND as shown below. This input protection, in combination with the external clamp capacitor and the output impedance of the CCD, prevents damage to the LM9811 from transients during power-up. DS012813-4 Note 8: To guarantee accuracy, it is required that VA and VD be connected together to the same power supply with separate bypass capacitors at each supply pin. Note 9: Typicals are at TJ = TA = 25˚C, fMCLK = 20MHz, and represent most likely parametric norm. Note 10: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). www.national.com 6 Electrical Characteristics (Notes) (Continued) Note 11: For CCDs, VBLACK is defined as the CCD OS voltage for the reference period following the reset feedthrough pulse. VWHITE is defined as the peak CCD pixel output voltage for a white (full scale) image with respect to the reference level, VBLACK - VRFT is defined as the peak positive deviation above VBLACK of the reset feedthrough pulse. For CIS, VWHITE is defined as the peak CCD pixel output voltage for a white (full scale) image with respect to GND (0V). The maximum correctable range of pixel-to-pixel VWHITE variation is defined as the maximum variation in VWHITE (due to PRNU, light source intensity variation, optics, etc.) that the LM9811 can correct for using its internal PGA. CCD Output Signal CIS Output Signal DS012813-6 DS012813-5 Note 12: Integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that best fits the actual transfer function of the ADC. Note 13: Reference voltages below 1.19V may decrease SNR. Reference voltages above 1.26V may cause clipping errors inside the LM9811. The LM4041EIM3-1.2 (SOT-23 package) or the LM4041EIZ-1.2 (TO-92 package) bandgap voltage references are recommended for this application. Note 14: PGA Gain Error is the maximum difference between the measured gain for any PGA code and the ideal gain calculated by using the formula and PGA RANGE = the PGA adjustment range (in V/V) of the LM9811 under test. Note 15: VGA Gain Error is the maximum difference between the measured gain for any VGA code and the ideal gain calculated by using the formula and VGA RANGE = the VGA adjustment range (in dB) of the LM9811 under test. Note 16: ADC Characteristics (Resolution, INL and DNL) are guaranteed for fMCLK up to 12MHz. For 12MHz < fMCLK ≤ 20 MHz, all specifications are guaranteed except ADC Characteristics, which will be approximately 8 bits. Typical Performance Characteristics φ1, φ2, RS, and TR Rise and Fall Times Through a Series Resistance vs Load Capacitance DS012813-8 7 www.national.com Pin Descriptions CCLK Digital Output. This is the signal that is used to clock the Gain coefficients into the LM9811. Data is latched on the rising edge of CCLK. DD0 (LSB)– DD9 (MSB) Digital Outputs. Pixel Output Databus. This data bus outputs the 10-bit digital output data during line scan. EOC Digital Output. This is the End of Conversion signal from the ADC indicating that new pixel data is available. RD Digital Input. Taking this input low places the data stored in the output latch on the bus. When this input is high the DD0–DD9 bus is in TRI-STATE. MCLK Digital Input. This is the 12MHz (typical) master system clock. SYNC Digital Input. A low-to-high transition on this input begins a line scan operation. The line scan operation terminates when this input is taken low. VA This is the positive supply pin for the analog supply. It should be connected to a voltage source of +5V and bypassed to AGND with a 0.1 µF monolithic capacitor in parallel with a 10 µF tantalum capacitor. AGND This is the ground return for the analog supply. VD This is the positive supply pin for the digital supply. It should be connected to a voltage source of +5V and bypassed to DGND with a 0.1 µF monolithic capacitor. DGND This is the ground return for the digital supply. VD(I/O) This is the positive supply pin for the digital supply for the LM9811’s I/O. It should be connected to a voltage source of +3V to +5V and bypassed to DGND(I/O) with a 0.1 µF monolithic capacitor. If the supply for this pin is different than the supply for VA and VD, it should also be bypassed with a 10 µF tantalum capacitor. DGND(I/O) This is the ground return for the digital supply for the LM9811’s I/O. NC All pins marked NC (no connect) should be left floating. Do not tie NC pins to ground., power supplies, or any other potential or signal. CCD Driver Signals φ1 Digital Output. CCD clock signal, phase 1. φ2 Digital Output. CCD clock signal, phase 2. RS Digital Output. Reset pulse for the CCD. TR Digital Output. Transfer pulse for the CCD. OS Analog Input. This is the OS (Output Signal) from the CCD. The maximum peak signal that can be accurately digitized is equal to the voltage at REF IN, typically 1.225V. Digital Output I/O Analog I/O REF IN REF OUTHI Analog Inputs. These two pins are the system reference voltage inputs and should be tied together to a 1.225V voltage source and bypassed to AGND with a 0.1 µF monolithic capacitor. General Digital I/O Analog Output. This reference voltage is developed internally by the LM9811, and is equal to 3 times REF IN. It should be bypassed to AGND with a 0.1 µF monolithic capacitor. REF OUTMID Analog Output. This reference voltage is developed internally by the LM9811, and is equal to 2 times REF IN. It should be bypassed to AGND using a 0.1 µF monolithic capacitor. VTEST1, VTEST2 Analog Inputs/Outputs. These pins are used for testing the device during manufacture and should be left unconnected. Analog Power Digital Power Configuration Register I/O SDI Digital Input. Serial Data Input pin. SDO Digital Output. Serial Data Output pin. SCLK Digital Input. This is the serial data clock, used to clock data in through SDI and out through SDO. SCLK is asynchronous to MCLK. Input data is latched and output data is changed on the rising edge of SCLK. CS Digital Input. This is the Chip Select signal for writing to the Configuration Register through the serial interface. This input must be low in order to communicate with the Configuration Register. This pin is used for serial I/O only–it has no effect on any other section of the chip. NC Digital Coefficient I/O CD0 (LSB)– CD7 (MSB) www.national.com Digital Inputs. Correction Coefficient Databus. This is the 8-bit data path for the gain adjust PGA, used during line scan. 8 Timing Diagrams DS012813-9 FIGURE 1. Line Scan Timing Overview DS012813-10 FIGURE 2. Pixel Pipeline Timing Overview 9 www.national.com Timing Diagrams (Continued) DS012813-11 FIGURE 3. Timing for Start of Line Scan DS012813-12 FIGURE 4. Timing for End of Line/Start of Next Line DS012813-13 FIGURE 5. TR Pulse Timing DS012813-14 FIGURE 6. RS Pulse Polarity www.national.com 10 Timing Diagrams (Continued) DS012813-15 Note: Clamp signal only active during optical black pixels at beginning of line. FIGURE 7. CCD Timing DS012813-16 Note: Clamp signal only active during optical black pixels at beginning of line. FIGURE 8. CCD Timing (Even/Odd CCDs) 11 www.national.com Timing Diagrams (Continued) DS012813-17 i = value programmed in Dummy Pixel Register - 1 (for example: Dummy Pixel Register = 17→i = 16→16 Dummy Pixel). j = value programmed in Optical Black Register. FIGURE 9. Dummy Pixel and Optical Black Pixel Timing DS012813-18 FIGURE 10. Coefficient Data Timing DS012813-19 FIGURE 11. Output Data Timing www.national.com 12 Timing Diagrams (Continued) DS012813-20 FIGURE 12. Data Timing (Output and Coefficient Data Sharing Same Bus) Serial Configuration Register Timing Diagrams DS012813-21 FIGURE 13. Configuration Register Write Timing using CS, Continuous SCLK (16-Bit Word) DS012813-22 FIGURE 14. Configuration Register Read Timing using CS, Continuous SCLK (16-Bit Word) 13 www.national.com Serial Configuration Register Timing Diagrams (Continued) DS012813-23 FIGURE 15. SDO Timing DS012813-24 FIGURE 16. Configuration Register Write Timing with CS Continuously Low (16-Bit Word) DS012813-25 FIGURE 17. Configuration Register Write Timing with CS Continuously Low (Two 8-Bit Bytes) DS012813-26 FIGURE 18. Configuration Register Read Timing with CS Continuously Low (16-Bit Word) DS012813-27 FIGURE 19. Configuration Register Read Timing with CS Continuously Low (Two 8-Bit Bytes) www.national.com 14 Configuration Register tMCLK = 1/fMCLK = 1 MCLK period. Examples given in parenthesis are for fMCLK = 20MHz (tMCLK = 50ns). Times for 12MHz MCLK can be calculated by multiplying by TABLE 1. Configuration Register Address Table A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Standard RS Pulse Width Mode or 0 0 0 Even/Odd RS Pulse Polarity RS Pulse Position Mode MODE RSW1 RSW0 RSPOL RSPOS3 Sample Reference Position 0 0 1 SR3 SR2 SR1 SR0 φ1 φ2 RS TR 1 0 Enable Enable Enable Enable φ1EN φ2EN RSEN TREN 0 1 1 Signal SIGPOL 1 1 0 1 0 1 0 BLS6 BLL7 BLL6 1 SS2 SS0 TR Guardband Polarity TRGRD TRPOL BLS1 BLS0 BLL2 BLL1 BLL0 TR Pulse Width TRW1 SS1 TR–φ1 TRW0 BLS5 BLS4 BLS3 BLS2 BLL5 BLL4 BLL3 PGA Gain Coefficient GAIN7 GAIN6 Offset PGA Gain Source DAC Sign ODSIGN Offset 1 SS3 Optical Black Pixels (Minimum Register Value is 1) PGASRC 1 RSPOS0 Dummy Pixels (Minimum Register Value is 2) Polarity 0 RSPOS1 Sample Signal Position (Maximum Register Value is 14) 0 1 RSPOS2 DAC MSB VOS3 GAIN5 GAIN4 GAIN3 GAIN2 GAIN1 GAIN0 Powerdown Offset Add VGA Gain MSB VGA Gain VGA Gain VGA Gain LSB PD OFFADD VGA3 VGA2 VGA1 VGA0 Offset DAC Offset DAC VOS2 VOS1 Offset DAC Test Modes LSB VOS0 0 0 0 0 TABLE 2. Configuration Register Parameters Parameter Control Bits Result MODE MODE Standard CCD (φ frequency = fMCLK/8) Even/Odd CCD (φ frequency = fMCLK/16) 0 1 RS Pulse Width (tRSWIDTH) RS Pulse Polarity RS1 RS0 0 0 1 tMCLK (50ns) 0 1 2 tMCLK (100ns) 1 0 3 tMCLK (150ns) 1 1 4 tMCLK (200ns) RSPOL 0 RS 1 RS 15 www.national.com Configuration Register tMCLK = 1/fMCLK = 1 MCLK period. Examples given in parenthesis are for fMCLK = (Continued) 20MHz (tMCLK = 50ns). Times for 12MHz MCLK can be calculated by multiplying by TABLE 2. Configuration Register Parameters (Continued) Parameter Control Bits RSPOS3 RS Pulse Position (tRS) Sample Reference Position (tS/HREF) www.national.com RSPOS2 Result RSPOS1 RSPOS0 0 0 0 0 0.0tMCLK (0ns) 0 0 0 1 0.5tMCLK (25ns) 0 0 1 0 1.0tMCLK (50ns) 0 0 1 1 1.5tMCLK (75ns) 0 1 0 0 2.0tMCLK (100ns) 0 1 0 1 2.5tMCLK (125ns) 0 1 1 0 3.0tMCLK (150ns) 0 1 1 1 3.5tMCLK (175ns) 1 0 0 0 4.0tMCLK (200ns) 1 0 0 1 4.5tMCLK (225ns) 1 0 1 0 5.0tMCLK (250ns) 1 0 1 1 5.5tMCLK (275ns) 1 1 0 0 6.0tMCLK (300ns) 1 1 0 1 6.5tMCLK (325ns) 1 1 1 0 7.0tMCLK (350ns) 1 1 1 1 7.5tMCLK (375ns) SR3 SR2 SR1 SR0 0 0 0 0 0.0tMCLK (0ns) 0 0 0 1 0.5tMCLK (25ns) 0 0 1 0 1.0tMCLK (50ns) 0 0 1 1 1.5tMCLK (75ns) 0 1 0 0 2.0tMCLK (100ns) 0 1 0 1 2.5tMCLK (125ns) 0 1 1 0 3.0tMCLK (150ns) 0 1 1 1 3.5tMCLK (175ns) 1 0 0 0 4.0tMCLK (200ns) 1 0 0 1 4.5tMCLK (225ns) 1 0 1 0 5.0tMCLK (250ns) 1 0 1 1 5.5tMCLK (275ns) 1 1 0 0 6.0tMCLK (300ns) 1 1 0 1 6.5tMCLK (325ns) 1 1 1 0 7.0tMCLK (350ns) 1 1 1 1 16 Not Valid Configuration Register tMCLK = 1/fMCLK = 1 MCLK period. Examples given in parenthesis are for fMCLK = (Continued) 20MHz (tMCLK = 50ns). Times for 12MHz MCLK can be calculated by multiplying by TABLE 2. Configuration Register Parameters (Continued) Parameter Control Bits SS3 Sample Signal Position (tS/HSIG) SS2 Result SS1 SS0 0 0 0 0 0.0tMCLK (0ns) 0 0 0 1 0.5tMCLK (25ns) 0 0 1 0 1.0tMCLK (50ns) 0 0 1 1 1.5tMCLK (75ns) 0 1 0 0 2.0tMCLK (100ns) 0 1 0 1 2.5tMCLK (125ns) 0 1 1 0 3.0tMCLK (150ns) 0 1 1 1 3.5tMCLK (175ns) 1 0 0 0 4.0tMCLK (200ns) 1 0 0 1 4.5tMCLK (225ns) 1 0 1 0 5.0tMCLK (250ns) 1 0 1 1 5.5tMCLK (275ns) 1 1 0 0 6.0tMCLK (300ns) 1 1 0 1 6.5tMCLK (325ns) 1 1 1 0 7.0tMCLK (350ns) 1 1 1 1 7.5tMCLK (375ns) φ1EN φ1 Enable 0 φ1 Output Off 1 φ1 Output On φ2EN φ2 Enable 0 φ2 Output Off 1 φ2 Output On RSEN RS Enable 0 RS Output Off 1 RS Output On TREN TR Enable 0 TR Output Off 1 TRW1 TR Pulse Width (tTRWIDTH) TR-φ1 TR Output On TRW0 0 0 20 tMCLK (1.0 µs) 0 1 30 tMCLK (1.5 µs) 1 0 40 tMCLK (2.0 µs) 1 1 50 tMCLK (2.5 µs) TRGRD Guardband 0 1 tMCLK (50ns) (tGUARD) 1 2 tMCLK (100ns) TRPOL TR Polarity 0 TR 1 TR SIGPOL Single Polarity 0 Positive (CIS) 1 Negative (CCD) 17 www.national.com Configuration Register tMCLK = 1/fMCLK = 1 MCLK period. Examples given in parenthesis are for fMCLK = (Continued) 20MHz (tMCLK = 50ns). Times for 12MHz MCLK can be calculated by multiplying by TABLE 2. Configuration Register Parameters (Continued) Parameter Dummy Pixels Note: Minimum Register Value is 2. Actual number of dummy pixels in CCD should be one less than number in this register. Optical Black Pixels Note: Minimum Register Value is 1. Internal PGA Gain Coefficient PGA Gain Coefficient Source Offset DAC Sign Power Down Offset Add www.national.com Control Bits Result BLS6 BLS5 BLS4 BLS3 BLS2 BLS1 BLS0 Dummy Pixels 0 0 0 0 0 0 0 Not Valid 0 0 0 0 0 0 1 Not Valid 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 2 • 1 1 1 BLL7 0 0 0 0 • 1 1 1 BLL6 0 0 0 0 • 1 1 1 BLL5 0 0 0 0 • 1 1 1 BLL4 0 0 0 0 • 1 1 1 BLL3 0 0 0 0 • 0 1 1 BLL2 0 0 0 0 • 1 0 1 BLL1 0 0 1 1 BLL0 Optical Black Pixels 0 Not Valid 1 1 0 2 1 3 • 1 1 1 GAIN7 0 0 0 • 1 1 1 GAIN6 0 0 0 • 1 1 1 GAIN5 0 0 0 • 1 1 1 GAIN4 0 0 0 • 1 1 1 GAIN3 0 0 0 • 1 1 1 GAIN2 0 0 0 • 0 1 1 GAIN1 0 0 1 • 1 0 1 GAIN0 0 1 0 • 1 1 1 • 1 1 1 • 1 1 1 • 1 1 1 • 0 1 1 • 1 0 1 • • 1 1 1 1 1 1 PGASRC 0 1 ODSIGN 0 1 PD 0 1 OFF ADD 0 1 • 124 125 126 • 253 254 255 dB [V/V] 0.00 1.000 0.07 1.008 0.13 1.015 • 9.35 2.935 9.37 2.942 9.40 2.950 Internal External Negative Positive Operating Powered Down Offset z0 LSB Offset z+8 LSB 18 Configuration Register tMCLK = 1/fMCLK = 1 MCLK period. Examples given in parenthesis are for fMCLK = (Continued) 20MHz (tMCLK = 50ns). Times for 12MHz MCLK can be calculated by multiplying by TABLE 2. Configuration Register Parameters (Continued) Parameter VGA Gain Control Bits Result VGA3 VGA2 VGA1 VGA0 dB [V/V] 0 0 0 0 0.00 1.00 0 0 0 1 0.60 1.07 0 0 1 0 1.20 1.15 0 0 1 1 1.79 1.23 0 1 0 0 2.39 1.32 0 1 0 1 2.99 1.41 0 1 1 0 3.59 1.51 0 1 1 1 4.19 1.62 1 0 0 0 4.79 1.74 1 0 0 1 5.38 1.86 1 0 1 0 5.98 1.99 1 0 1 1 6.58 2.13 1 1 0 0 7.18 2.29 1 1 0 1 7.78 2.45 1 1 1 0 8.38 2.62 1 1 1 1 8.97 2.81 19 www.national.com Configuration Register tMCLK = 1/fMCLK = 1 MCLK period. Examples given in parenthesis are for fMCLK = (Continued) 20MHz (tMCLK = 50ns). Times for 12MHz MCLK can be calculated by multiplying by TABLE 2. Configuration Register Parameters (Continued) Parameter Offset DAC www.national.com Control Bits Result ODSIGN VOS3 VOS2 VOS1 VOS0 0 0 0 0 0 0 0 0 0 0 1 −1.68 0 0 0 1 0 −3.36 0 0 0 1 1 −5.04 0 0 1 0 0 −6.72 0 0 1 0 1 −8.40 0 0 1 1 0 −10.08 0 0 1 1 1 −11.76 0 1 0 0 0 −13.44 0 1 0 0 1 −15.12 0 1 0 1 0 −16.80 0 1 0 1 1 −18.48 0 1 1 0 0 −20.16 0 1 1 0 1 −21.84 0 1 1 1 0 −23.52 0 1 1 1 1 −25.20 1 0 0 0 0 0 1 0 0 0 1 +1.68 1 0 0 1 0 +3.36 1 0 0 1 1 +5.04 1 0 1 0 0 +6.72 1 0 1 0 1 +8.40 1 0 1 1 0 +10.08 1 0 1 1 1 +11.76 1 1 0 0 0 +13.44 1 1 0 0 1 +15.12 1 1 0 1 0 +16.80 1 1 0 1 1 +18.48 1 1 1 0 0 +20.16 1 1 1 0 1 +21.84 1 1 1 1 0 +23.52 1 1 1 1 1 +25.20 20 Offset (LSB) Block Diagram of LM9811-Based System DS012813-28 Power supplies and bypass capacitors not shown for clarity. FIGURE 20. LM9811 System Block Diagram output and amplified by 2. The full-scale signal range at this point is approximately 2.45Vp-p. CDS reduces or eliminates many sources of noise, including reset noise, flicker noise, and both high and low frequency pixel-to-pixel offset variation. For more information on the CDS stage, see Section 4.4. At this point an offset voltage can be injected by the 5-bit (4 bits + sign) Offset DAC. This voltage is designed to compensate for any small fixed DC offset introduced by the CDS S/Hs and the x2 amplifier. The LSB size of the DAC is approximately 1.7 ADC LSBs (4 mV). The adjustment range is ± 25 ADC LSBs. For a detailed explanation of the Offset DAC, see Section 4.6. The next stage is the PGA. This is a programmable gain amplifier that changes the gain at the pixel rate to correct for gain errors due to PRNU, uneven illumination (such as cos4 effect), RGB filter mismatch, etc. The gain adjustment range is 0 dB to 9 dB (1V/V to 3V/V) with 8 bits of resolution. The gain data (correction coefficients) is provided on the CD0–CD7 bus. The gain may also be fixed at any value between 0 dB and 9 dB with the PGA Gain Coefficient configuration register. For additional information on the PGA, see Section 4.7. An approximately 8 LSB (19 mV) offset can be added at the output of the PGA stage if necessary to ensure that the offset is greater than zero. This eliminates the possibility of a negative offset clipping the darkest output pixels. For more information on the Offset Add Bit, see Section 4.8. Applications Information 1.0 THEORY OF OPERATION The LM9811 removes errors from and digitizes a linear CCD pixel stream, while providing all the necessary clock signals to drive the CCD. Offset and gain errors for individual pixels are removed at the pixel rate. Offset errors are removed through correlated double sampling (CDS). Gain errors (which may come from any combination of PRNU, uneven illumination, cos4 effect, RGB filter mismatch, etc.) are removed through the use of a 8-bit programmable gain amplifier (PGA) in front of the ADC. 1.1 The Analog Signal Path (See Block Diagram) The analog output signal from the CCD is connected to the OS Input of the LM9811 through a 0.01 µF (typical, see Section 4.2, Clamp Capacitor Selection ) DC blocking capacitor. During the CCD’s optical black pixel segment at the beginning of every line, this input is clamped to the REF OUTMID voltage (approximately 2.45V). This DC restore operation fixes the reference level of the CCD pixel stream at REF OUTMID. The signal is then buffered and fed to a digitally-programmed 4-bit VGA (variable gain amplifier). The gain of the VGA is digitally programmable in 16 steps from 1V/V to 3V/V. The VGA is used to compensate for peak white CCD outputs less than the 1.225V full-scale required by the LM9811 for maximum dynamic range. When used with parallel output CCDs, the VGA can fine-tune the amplitude of the red, green, and blue signals. For a detailed explanation of the VGA, see Section 4.3. The output of the VGA goes into the CDS (Correlated Double Sampling) stage, consisting of two sample/hold amplifiers: S/H Ref (Reference) and S/H Signal. The reference level of the signal is sampled and held by the S/H Ref circuit and the active pixel data is sampled and held by the S/H Signal circuit. The output of S/H Ref is subtracted from the S/H Signal Finally, the output of the PGA is digitized by the ADC and made available on the DD0–DD9 bus (Section 4.9). Three reference voltages are used throughout the signal path: the externally supplied REF IN (1.225V), and the internally generated REF OUTMID (2.45V) and REF OUTHI (3.675V). 21 www.national.com Applications Information If the serial I/O to the configuration register falls out of sync for any reason, it can be reset by sending 8 or more SCLKs with CS held high. (Continued) 1.2 The CCD Clocking Signals To maximize the flexibility of the LM9811, the CCD’s φ1, φ2, RS, and TR pulses are internally generated, with a wide range of options, making these signals compatible with most commercial linear CCDs. In many cases, these output signals can drive the CCD clock inputs directly, with only series resistors (for slew rate control) between the LM9811’s outputs and the CCD clock inputs. 2.2 Writing Correction Coefficient Data on the CD0–CD7 Bus Correction coefficient data for each pixel is latched on the rising edge of the CCLK output signal (see Figure 10). Note that there is a 3 pixel latency between when the coefficient data is latched and when the output data is available. As Figure 2, Pixel Pipeline Timing Overview shows, coefficient data for pixel n is latched shortly before the output data for pixel n-2 becomes available on the output databus (DD0–DD9). Note that there is no way to provide a correction coefficient for pixel 1, the first pixel in the CCD array. This is usually not a problem since the first several pixels of a CCD are usually optical black pixels, and used for clamping. 1.3 The Digital Interface There are three main sections to the digital interface of the LM9811: a serial interface to the Configuration Register, where all device programming is done, an 8 bit-wide input databus for gain correction coefficients with a synchronous clock output (CCLK), and a 10-bit output databus for the final pixel output data with a synchronous end of conversion output signal (EOC) and an output enable input (RD). Please note that the CS input affects only the serial I/O–it has no effect on the output databus, input coefficient bus, or any other section of the LM9811. 2.3 Reading Output Data on the DD0–DD9 Bus The corrected digital output data representing each pixel is available on the DD0–DD9 databus. The data is valid after the falling edge of the EOC output. The RD input takes the databus in and out of TRI-STATE. RD can be held low at all times if there are no other devices needing the bus, or it can be used to TRI-STATE the bus between pixels, allowing other devices access to the bus. Figure 12, Data Timing (Output and Coefficient Data Sharing Same Bus), shows how EOC can be tied to RD to automatically multiplex between coefficient data and conversion data. 2.0 DIGITAL INTERFACE 2.1 Reading and Writing to the Configuration Register Communication with the Configuration Register is done through a standard MICROWIRE™ serial interface. This interface is also compatible with the Motorola SPI™ standard and is simple enough to easily be implemented in custom hardware if needed. The serial interface timing is shown in Figures 13, 14 and Figures 16, 17, 18, 19. Data is sent serially, LSB first. (Please note that some microcontrollers output data MSB first. When using these microcontrollers the bits in the configuration register are effectively reversed.) Input data is latched on the rising edge of SCLK, and output data changes on the falling edge of SCLK. CS must be low to enable serial I/O. If SCLK is only clocked when sending or receiving data from the LM9811, and held low at all other times, then CS can be tied low permanently as shown in Figures 16, 17, 18, 19. If SCLK is continuous, then CS must be used to determine the beginning and the end of a serial byte or word (see Figures 13, 14). Note that CS must make its high-to-low and low-to-high transitions when SCLK is low, otherwise the internal bit counter may receive an erroneous pulse, causing an error in the write or read operation. Data may be transmitted and received in two 8-bit bytes (typical with microcontroller interfaces) or one 16-bit word (for custom serial controllers). 2.4 MCLK This is the master clock input that controls the LM9811. The pixel conversion rate is fixed at 1/8 of this frequency. Many of the timing parameters are also relative to the frequency of this clock. 2.5 SYNC This input signals the beginning of a line. When SYNC goes high, the LM9811 generates a TR pulse, then begins converting pixels until the SYNC line is brought low again. Since there is no pixel counter in the LM9811, it will work with CCDs of any length. 3.0 DIGITAL CCD INTERFACE 3.1 Buffering φ1, φ2, RS, and TR The LM9811 can drive the φ1, φ2, RS, and TR inputs of many CCDs directly, without the need for external buffers between the LM9811 and the CCD. Most linear CCDs designed for scanner applications require 0V to 5V signal swings into 20pF to 500pF input loading. Series resistors are typically inserted between the driver and the CCD to control slew rate and isolate the driver from the large load capacitances. The values of these resistors are usually given in the CCD’s datasheet. The Configuration Register is programmed by sending a control byte to the serial port. This byte indicates whether this is a read or a write operation, and gives the 3-bit address of the register bank to be read from or written to. If this is a read operation, the next 8 SCLKs will output the data at the requested location on the SDO pin. If this is a write operation, the data to be sent to the specified location should be clocked in on the SDI input during the next 8 SCLKs. Data is sent and received using the LSB (Least Significant Bit) first format. For maximum system reliability, each configuration register location can be read back and verified after a write. www.national.com 4.0 ANALOG INTERFACE 4.1 Voltage Reference The two REF IN pins should be connected to a 1.225V ± 2% reference voltage capable of sinking between 2 mA and 5 mA of current coming from the 500Ω–1400Ω resistor string between REF OUTHI and REF IN. The LM4041-1.2 1.225V bandgap reference is recommended for this application as shown in Figure 21. The inexpensive “E” grade meets all the 22 Applications Information droop (100 mV), the number of pixels on the CCD, and the pixel conversion rate (fMCLK/8) and provides the minimum clamp capacitor value: (Continued) requirements of the application and is available in a TO-92 (LM4041EIZ-1.2) package as well as a SOT-23 package (LM4041EIM3-1.2) to minimize board space. Due to the transient currents generated by the LM9811’s ADC, PGA, and CDS circuitry, the REF IN pins, the REF OUTMID pin and the REF OUTHI pin should all be bypassed to AGND with 0.1 µF monolithic capacitors. For example, if the OS input leakage current is 20 nA worstcase, the CCD has 2700 active pixels, the conversion rate is 1.5MHz (fMCLK = 12MHz), and the max droop desired is 0.1V, the minimum clamp capacitor value is: The maximum size of the clamp capacitor is determined by the amount of time available to charge it to the desired value during the optical black portion of the CCD output. The internal clamp is on for each pixel from the rising edge of the S/H ref pulse to the falling edge of the S/H signal pulse (see Figures 7, 8). This time can be calculated using the values stored in the Sample Signal and Sample Reference configuration registers and the MCLK frequency. For normal CCDs: DS012813-29 FIGURE 21. Voltage Reference Generation 4.2 Clamp Capacitor Section This section is very long because it is relatively complicated to explain, but the answer is short and simple: A clamp capacitor value of 0.01 µF should work in almost all applications. The rest of this section describes exactly how this value is selected. And for even/odd CCDs: Where SS is the value in the Sample Signal Position register (0–15), SR is the value in the Sample Reference Position register (0–14), fMCLK is the MCLK frequency, and tDARK is the amount of time (per pixel) that the clamp is on. The following equation takes the number of optical black pixels, the amount of time (per pixel) that the clamp is closed, the CCD’s output impedance, and the desired accuracy of the final clamp voltage and provides the maximum clamp capacitor value that allows the clamp capacitor to settle to the desired accuracy within a single line: DS012813-30 FIGURE 22. OS Clamp Capacitor and Internal Clamp The output signal of many CCDs rides on a large DC offset (typically 8V to 10V) which is incompatible with the LM9811’s 5V operation. To eliminate this offset without resorting to additional higher voltage components, the output of the CCD is AC coupled to the LM9811 through a DC blocking capacitor, CCLAMP (the CCD’s DOS output is not used). The value of this capacitor is determined by the leakage current of the LM9811’s OS input and the output impedance of the CCD. The leakage through the OS input determines how quickly the capacitor value will drift from the clamp value of REF OUTMID, which then determines how many pixels can be processed before the droop causes errors in the conversion ( ± 0.1V is the recommended limit). The output impedance of the CCD determines how quickly the capacitor can be charged to the clamp value during the black reference period at the beginning of every line. Where n = the number of optical black pixels, tDARK is the amount of time (per pixel) that the clamp is on, ROUT is the output impedance of the CCD, and accuracy is the ratio of the worst-case initial capacitor voltage to the desired final capacitor voltage. For example, if a CCD has 18 black reference pixels, the output impedance of the CCD is 1500Ω, the LM9811 is configured to clamp for 500ns, the worst case initial voltage across the capacitor is 10V, and the desired voltage after clamping is 0.1V (accuracy = 10/0.1 = 100), then: The minimum clamp capacitor value is determined by the maximum droop the LM9811 can tolerate while converting one CCD line. The following equation takes the maximum leakage current into the OS input, the maximum allowable 23 www.national.com Applications Information (Continued) The final value for CCLAMP should be less than or equal to CCLAMP MAX, but no less than CCLAMP MIN. A value of 470 pF will work in this example. In some cases, depending on primarily on the choice of CCD, CCLAMP MAX may actually be less than the CCLAMP MIN, meaning that the capacitor cannot be charged to its final voltage during the black pixels at the beginning of a line and hold its voltage without drooping for the duration of that line. This is usually not a problem because in most applications the CCD is clocked continuously as soon as power is applied. In this case, a larger capacitor can be used (guaranteeing that the CCLAMP MIN requirement is met), and the final clamp voltage is forced across the capacitor over multiple lines. This is the equation to calculate how many lines are required before the capacitor settles to the desired accuracy: Using the values shown before and a clamp capacitor value of 0.01 µF, this works out to be: DS012813-31 FIGURE 23. CDS Capacitor C1 converts the electrons coming from the CCD’s shift register to an analog voltage. The source follower output stage (Q2) buffers this voltage before it leaves the CCD. Q1 resets the voltage across capacitor C1 in between every pixel at intervals 2 and 5. When Q1 is on, the output signal (OS) is at its maximum. After Q1 turns off (period 3), the OS level represents the residual voltage across C1 (VRESIDUAL). VRESIDUAL includes charge injection from Q1, thermal noise from the ON resistance of Q1, and other sources of error. When the shift register clock (φ1) makes a low to high transition (period 4), the electrons from the next pixel flow into C1. The charge across C1 now contains the voltage proportional to the number of electrons plus VRESIDUAL, an error term. If OS is sampled at the end of period 3 and that voltage is subtracted from the OS at the end of period 4, the VRESIDUAL term is canceled and the noise on the signal is reduced. ([VSIGNAL+VRESIDUAL] −VRESIDUAL = VSIGNAL). This is the principal of Correlated Double Sampling. The LM9811 implements CDS with two switched-capacitor S/H amplifiers. With a 12MHz MCLK input, the LM9811’s S/Hs acquire a signal within an 83ns window which can be placed anywhere in the pixel period with 42ns precision. See Figures 7, 8 for more detailed timing information. At a 2.5MHz conversion rate, this is about 14ms. In this example a 0.01 µF capacitor takes 14ms after power-up to charge to its final value, but its droop across all subsequent lines is now less than 2 mV (using the previous example’s values). This wide margin is the reason a CCLAMP value of 0.01 µF will work in most applications. 4.3 VGA The LM9811 has a VGA (Variable Gain Amplifier) that can be used to increase the amplitude of the CCD signal prior to sampling, correction, and digitization. The gain of the VGA is 0 dB to 9 dB and is determined by the codes in the 4-bit VGA Gain register, as given by the equation: This gain may be changed at the line rate (not the pixel rate) by writing to the configuration register. You can write to the configuration register to change the gain at any time, but if you write during a line, the remaining pixels of that line may be corrupted. It is best to change the gain after all active pixels have been read out or while SYNC is low. 4.5 CIS Mode The LM9811 provides some support for CIS (Contact Image Sensor) devices by offering a sampling mode for capturing positive going signals, as opposed to the CCD’s negative going signal. 4.4 Correlated Double Sampler (CDS) Figure 23 shows the output stage of a typical CCD and the resulting output waveform: www.national.com 24 Applications Information 4.9 ADC (Continued) The ADC converts the normalized analog output signal to a 10-bit digital code. The EOC output goes from high to low to indicate that a new conversion is ready. ADC data can be latched by external memory on the rising edge of EOC. The RD input takes the ADC’s output buffer in and out of TRI-STATE. RD may be tied to EOC in many applications, putting the data on the bus only when EOC is low, and allowing other data on the bus (such as CD0–CD7 correction data) at other times. In this way the output data and correction coefficient data can share the same databus (see Figure 12). 5.0 CALIBRATION Calibration of a CCD scanner is done to normalize the pixels of a linear CCD so that each pixel produces the same digital output code at the output of the scanner when presented with the same image light intensity. This intensity ranges from black (no light) to white (maximum light intensity). The CCD’s analog output may have large pixel-to-pixel DC offsets (corresponding to errors on black signals) and pixel-to-pixel variations in their output voltage given the same white image (corresponding to errors on brighter signals). If these offsets are subtracted from each pixel, and each pixel is given its own gain setting to correct for different efficiencies, then these errors can be eliminated. Ideally the digital output code for any pixel would be zero for a black image, and some code near fullscale for an image with maximum brightness. For a 10-bit system like the LM9811, that code might be 1000. This code will be called the Target Code. The LM9811 eliminates these global and pixel-to-pixel offset and gain errors with its Correlated Double Sampling (CDS), Offset DACs, Variable Gain Amplifier, and pixel-rate Programmable Gain Amplifier. This section describes how to program the LM9811 and the coefficient RAM being used with it to eliminate these errors. Calibration of a LM9811-based system requires 3 steps. The first, described in Section 5.1, Offset Calibration, takes a black image and normalizes the digital output code for each pixel to a code at or near 0. The second step, Section 5.2, Coarse Gain (VGA) Calibration, finds the optimum gain setting that places the output voltage of all the pixels within the 9 dB adjustment range of the PGA. The final step, described in Section 5.3, PGA Correction Coefficients (Shading Calibration), describes how to calculate the gain required to normalize the output of each pixel to the desired output code (the Target code). DS012813-32 FIGURE 24. CIS vs CCD Output Signals While CIS devices do not usually have a reference level with which to perform correlated double sampling, many have a very repeatable reset level which can be used as a black reference allowing the LM9811 to perform pseudo CDS on the signal. For more information on CIS applications, see Section 9.0. When the Signal Polarity bit is set to a zero, the LM9811 expects a positive going signal, typically from a CIS device. When the Signal Polarity bit is set to a one, the LM9811 expects a negative going signal, typically from a CCD sensor. 4.6 Offset DAC The 4 bit plus sign offset DAC is used to compensate for DC offsets due to the correlated double sampling stage. The offset can be corrected in 31 steps of 1.7 ADC LSB size between −25.2 LSB and +25.2 LSB. Note that the DAC comes before the PGA, so any offset errors at this stage are multiplied by the gain of the PGA. The calibration procedure described in Section 5.0 demonstrates how to use the DAC to eliminate offset errors before scanning begins. Note that this DAC is programmed during LM9811 calibration/configuration and is not meant to compensate for pixel-to-pixel CCD offset errors. CDS cancels the pixel-rate offset errors. 4.7 Programmable Gain Amplifier (PGA) The PGA provides 8 bits of pixel-to-pixel gain correction over a 0 dB to 9 dB (x1 to x3) range. After the input signal is sampled and held by the CDS stage, it is amplified by the gain indicated by the data (“PGA Code”) on the CD0–CD7 databus using the formula: 5.1 Offset Calibration This procedure corrects for static offsets generated by the CCD and the LM9811. Because the LM9811 uses CDS to eliminate the pixel-to-pixel offset errors of the CCD, no pixel-rate offset correction is required. 4.8 Offset Add Bit In addition to the Offset DAC, there is a bit in the configuration register which, when set, adds a positive 8 LSB offset at the output of the PGA. This offset ensures that any offset between the output of the PGA and the ADC is positive, so that no dark level information is lost due to negative offsets. The calibration procedure described in Section 5.0 demonstrates how to set this bit. 25 www.national.com Applications Information Offset DAC code = -(VOS1)(15/25.2) = (25.2 + (VADC1–VADC2)/1.95)(15/25.2) = 15 + 0.3(VADC1–VADC2) (Continued) (Note: This calculation can be approximated as 15 + 10(VADC1–VADC2)/32 for ease of programming in 8-bit microcontrollers) 12. If 3VADC1 > VADC2, then set the Offset Add bit to 0. If 3VADC1 < VADC2, set the Offset Add bit to 1. 13. The final value of the offset present at the ADC input can be used for the shading calibration calculations. Calculate the final value of the ADC input offset (VOFFSET) using: DS012813-33 FIGURE 25. Offset Calibration To use the Offset DAC and Offset Add bit for offset correction, the offset errors (VOS1 and VOS2) must first be determined, as shown in Figure 25. This is done be measuring the voltage at the PGA output, using the ADC with a black image on the CCD (a black image can usually be created simply by turning off the scanner’s illumination). If this voltage is known with a PGA gain of 1.00V/V (0 dB) and 2.95V/V (9 dB), then the offset errors (VOS1 and VOS2) can be determined from the following two equations: VADC1 = 1(VOS1 + VDAC1) + VOS2 + VDAC2 (PGA gain = 1) A. (3VADC1–VADC2)/2 (if the Offset Add bit is 0), or B. (3VADC1–VADC2)/2 + 8 (if the Offset Add bit is 1) 5.2 Coarse Gain Calibration The LM9811’s PGA corrects for up to 9 dB of variation in the CCD output signal’s white level intensity. That 9 dB range has to be centered inside the 9 dB window of correction as shown in Figure 26. The window’s upper limit is determined by the Target code, and the lower limit by the Target code divided by 2.8 (this corresponds to the minimum gain range of the PGA). To allow proper calibration, the amplitude of all the pixels in the CCD should be inside this range when those pixels are scanning an image corresponding to the Target code. The placement of the pixels inside the 9 dB window can be controlled by any of three ways: changing the gain of the VGA, changing the integration time of the CCD, or changing the intensity of the light source. In most designs, the output waveform of the CCD can be brought into the 9 dB correction range of the PGA by adjusting the gain of the VGA. This is the next step in system calibration. VADC2 = 2.95(VOS1 + VDAC1) + VOS2 + VDAC2 (PGA gain = 2.95) Solving for VOS1 and VOS2: VOS1 = (VADC2–VADC1)/1.95–VDAC1 VOS2 = (2.95VADC1–VADC2)/1.95–VDAC2 These equations were used to produce this procedure for cancelling the LM9811’s offset errors. Please note that all voltages and measurements are in units of ADC LSBs to simplify calibration. 1. Set the VGA Gain to 1V/V (VGA code = 0). 2. Set the Offset DAC (VDAC1) to its maximum value (+25.2 LSBs) to ensure the total offset is positive and therefore measurable by the ADC. 3. Set the Offset Add bit (VDAC2) to 0. 4. Set the PGA Gain to 1V/V (PGA code = 0). 5. 6. 7. 8. 9. 10. Digitize a black line. Calculate the average (in ADC LSBs) of all the valid pixels in the black line and store that number as VADC1. Set the PGA Gain to 2.95V/V (PGA code = 255). Digitize a black line. Calculate the average (in ADC LSBs) of all the valid pixels in the black line and store that number as VADC2. Calculate VOS1: VOS1 = (VADC2)–VADC1)/1.95–25.2 DS012813-34 FIGURE 26. CCD Input Signal In Range Figure 27 is a flowchart of one technique to find the optimum VGA gain setting during calibration. Calibration begins with a VGA gain setting of 1V/V and increments the VGA gain until one of the four possible results occur. Result 1 is the desired outcome, where the signal falls into the range shown in Figure 26 and the VGA calibration has been successful. 11. Program the Offset DAC register using the formula: www.national.com 26 Applications Information (Continued) DS012813-35 FIGURE 27. VGA Calibration Flowchart has more uniform illumination, higher quality lenses, or other opto-mechanical techniques to reduce variation across all the active pixels. There are several conditions that can cause the VGA gain calibration routine to fail. Result 2, “Signal is too strong: Decrease light intensity or integration time” is shown in Figure 28. This condition indicates that the amplitude of one or more of the white pixels coming from the CCD is greater than the maximum input voltage that the LM9811 is capable of accepting (about 1.2Vp-p). In this case the amplitude of the analog CCD output must be reduced before it enters the LM9811’s OS input to prevent clipping. This can be done by reducing the intensity of the light source or shortening the integration time of the CCD. DS012813-37 FIGURE 29. CCD Input Signal Range Too Wide DS012813-36 FIGURE 28. CCD Input Signal Too Strong The second possible failure mode of the VGA calibration (Result 3) occurs if there is “Too much variation” in the amplitude of the pixels coming from the CCD (Figure 29). The LM9811 can correct for up to a 2.8 to 1 variation in pixel amplitude. If the variation is greater than this than it must be reduced before it can perform shading correction on all the pixels. Typically this is done by using a better light source that DS012813-38 FIGURE 30. CCD Input Signal Too Weak The final problem that can occur during VGA calibration (Result 4) is the “Signal too weak: increase light intensity or integration time” condition, shown in Figure 30. In this case, 27 www.national.com Applications Information In systems with separate analog and digital +5V supplies, all the supply pins of the LM9811 should be powered by the analog +5V supply. Each supply input should be bypassed to its respective ground with a 0.1 µF capacitor located as close as possible to the supply input pin. A single 10 µF tantalum should be placed near the VA supply pin to provide low frequency bypassing. (Continued) even with the VGA gain set to a maximum of 2.8, the amplitude of one or more pixels is less than the minimum required for shading correction. The solution is to increase the intensity of the light source or lengthen the integration time of the CCD to increase the CCD’s output amplitude. To ensure that a scanner system is manufacturable, the result of the VGA calibration must always be State 1. States 2, 3, and 4 must be eliminated either by ensuring that the total variation in light intensity (from all sources) from system to system to a maximum of 9 dB, or by being able to adjust the light source’s intensity and/or the CCD’s light integration time. To minimize noise, keep the LM9811 and all analog components as far as possible from noise generators, such as switching power supplies and high frequency digital busses. If possible, isolate all the analog components and signals (OS, reference inputs and outputs, VA, AGND) on an analog ground plane, separate from the digital ground plane. The two ground planes should be tied together at a single point, preferably the point where the power supply enters the PCB. 5.3 PGA Correction Coefficients (Shading Calibration) 6.2 3V Compatible Digital I/O If 3V digital I/O operation is desired, the VD(I/O)pin may be powered by a separate 3V ± 10% or 3.3V ± 10% supply. In this case, all the digital I/O pins (CD0–CD7, CCLK, MCLK, DD0–DD9, EOC, RD, SYNC, CS, SCLK, SDO, and SDI) will be 3V compatible. The CCD clock signals (φ1, φ2, RS, and TR) remain 5V outputs, powered by VD. In this case the VD(I/O) input should be bypassed to DGND(I/O) with a parallel combination of a 0.1 µF capacitor and a 10 µF tantalum capacitor. Once the input signal has been centered inside the range the LM9811 can correct for, correction coefficients must be generated for each pixel to compensate for the gain error of that pixel. 1. Set Offset DAC and Add Bit as determined in Section 5.1. 2. 3. 4. Set the VGA gain to the value determined in Section 5.2. Set the PGA gain to 0 dB. Scan a reference line corresponding to all white or light grey and store it in memory. 5. Calculate the required gain correction coefficients for each pixel using the formula: 6.3 Power Down Mode Setting the Power Down bit to a “1” puts the device in a low power standby mode. The CCD outputs (φ1, φ2, RS, and TR) are pulled low and the analog sections are turned off to conserve power. The digital logic will continue to operate if MCLK continues and SYNC is held high, so for minimum power dissipation MCLK should be stopped when the LM9811 enters the Power Down mode. Recovery from Power Down typically takes 50 µs (the time required for the reference voltages to settle to 0.5 LSB accuracy). Where Uncorrected Coden is the ADC output code for pixel n with the PGA gain = 0 dB, Target Code is the number that corresponds to the desired output from the ADC with the given reference line input, and Correction Coefficientn is the gain correction number that is sent to the CD0–CD7 correction databus to provide gain correction for pixel n when digitizing a line with the LM9811’s PGA gain correction operating. If it is difficult or undesirable to do the division, subtraction, and multiplication operations shown above for every pixel, then a lookup table can be generated in advance that will return the Correction Coefficient for any Uncorrected Code. This table can be stored in ROM or RAM and can speed up the calibration process. The disadvantage of this technique is that the Target Code must be fixed when the table is generated, so only one Target Code can be used (unless multiple tables are generated). 7.0 COLOR There are two primary ways to use the LM9811 in a color system with a triple output (RGB) CCD. The first is to use one LM9801 with an external multiplexer. This is the simplest solution. The second technique is to use one LM9811 per RGB color. 7.1 Parallel Output CCD, One LM9811 Figure 31 is an example of how to use a single LM9811 with a triple-output RGB CCD. In this case an entire line of red is digitized, followed by an entire line of green, then blue. This solution provides a 1.5 Mpixels/sec (for an effective 500k RGB pixels/sec after de-interleaving) pixel rate using a high performance triple output color CCD. The Mux 1 multiplexer, located between the CCD’s OS outputs and the LM9811’s OS input, selects the color to be digitized according to the states of the A and B inputs (described below). The multiplexer’s speed requirements are minimal because the mux switches at the line rate, not the pixel rate. Also, since the output of the mux goes into a high impedance, low-capacitance input, the ON resistance of the mux is not critical. The 74HC4052 is a good choice for this application. All the Correction Coefficients must be stored and sent to the LM9811 through the CD0–CD7 databus for every line scanned. 6.0 POWER SUPPLY CONSIDERATIONS 6.1 General The LM9811 should be powered by a single +5V source (unless 3V-compatible digital I/O is required — see Section 6.2). The analog supplies (VA) and the digital supplies (VD and VD(I/O)) are brought out individually to allow separate bypassing for each supply input. They should not be powered by two or more different supplies. www.national.com 28 Applications Information (Continued) DS012813-39 FIGURE 31. Parallel Output CCD Application Circuit DS012813-40 FIGURE 32. Parallel Output CCD Timing since each color will need a different VGA gain, the appropriate VGA gain value for each color should be sent to the LM9811 during this time. To maximize the integration time for the Red, Green, and Blue photodiodes, the transfer (TR) pulses should be staggered as shown in Figure 32. This is done by a demultiplexer (Mux 2) between the TR output of the LM9811 and the transfer gate inputs of the CCD. If the CCD’s transfer gate input capacitance is relatively low (see the CCD datasheet for this specification and the requirements for TR pulse rise and fall time), then the other half of the 74HC4052 may be used to switch the TR pulses as shown. If the TR gate input capacitance is so large that the minimum TR rise and fall times can not be met because of the 200Ω max on resistance of the 74HC4052’s switches, then the 74HC4052 can not be used to multiplex the TR output and should be replaced with an active demultiplexer such as the 74HC155 dual 2-to-4 demultiplexer. Two signals (A and B) must be generated to choose which color is going to be digitized and receives the TR pulse. These signals can be as simple as the output of a two bit counter that counts from 0 to 2 (0, 1, 2, 0, 1, 2, etc.). This counter should be incremented after the end of the previous line and before the first transfer pulse of the next line. Also, 7.2 Parallel Output CCD, Three LM9811s Figure 33 uses three LM9811s to achieve a 4.5 Mpixel/sec (1.5M RGB pixels/sec) pixel rate. The three LM9811s are synchronized by applying the same MCLK and SYNC signals to all three devices. One LM9811 provides the clock signals required for the CCD. Since the coefficient data for all three LM9811s will be latched simultaneously on the rising edge of CCLK, the correction coefficient bus must either be at least 24 bits wide (8 correction coefficient bits by 3 LM9811s) or run at a 4.5MHz rate and be latched into a buffer between the correction coefficient databus and each LM9811. Similarly, the output data for all three LM9811s will be available simultaneously at the 3 output databusses. Since each LM9811 is dedicated to one color, the VGA gain does not change during line scan. 29 www.national.com Applications Information Sample Reference Position = 14, Sample Signal Position = 8, φ1/φ2/RS/TR Enable = 1/1/1/1 TR Pulse Width = 0 TR-φ1 Guardband = 0 (Continued) TR Polarity = 0* Signal Polarity = 1 Dummy Pixels = 2* Optical Black Pixels = 5* (*Value given in CCD datasheet) The Mode is set to Even/Odd, RS Pulse Width is set to its minimum value, and RS polarity is positive. The timing, shown in Figure 35, is determined by the RS, SR, and SS registers. The RS pulse position (RS) is set to 10, dividing the pixel period so that the signal portion is available for the first 5 MCLKs following a φ1 clock edge and the black reference portion appears during the last 2 MCLKs (following the 1 MCLK wide reset pulse). Sample Reference (SR) is set to 14, so it samples the black reference just before the next φ1 clock edge. Sample Signal (SS) is set to 8, so it samples the black reference just before the next reset pulse. These values can be adjusted to account for differences in CCDs, CCD data delays, settling time, etc., but this is often not necessary. DS012813-41 FIGURE 33. Parallel Output CCD, Three LM9811 8.0 TYPICAL GREYSCALE APPLICATION Figure 34 shows the interface between the LM9811 and a typical greyscale even/odd output CCD, the TCD1250. The interface for most other CCDs will be similar, the only difference being the values for the series resistors (if required). The clamp capacitor value is determined as shown in Section 4.2. The resistor values are usually given in the CCD’s datasheet. If the datasheet’s requirement is given as a particular rise/fall time, the resistor can be chosen using the graph of φ1, φ2, RS and TR Rise Times Through A Series Resistance vs Load Capacitance graph in the Typical Performance Characteristics section. Given the required rise time and the input capacitance of the input being driven, the resistor value can be estimated from the graph. DS012813-43 FIGURE 35. Typical Even/Odd Timing All 4 digital outputs (φ1, φ2, RS, and TR) are enabled. The TR pulse width is set to the minimum, 20 MCLKs, as is the guardband between φ1 and TR. Either of these settings can be increased if necessary. The TR polarity is positive, as is the RS polarity. Some CCDs may require one or both of these signals to be inverted, in which case the corresponding bit can be set to a “1”. If there is an inverting buffer between the LM9811 and the CCD, these bits may be used to correct the output polarity at the CCD. Note that if φ1 and φ2 are inverted, then φ2 should be used as φ1 at the CCD, and φ1 should be used as φ2 at the CCD (Figure 36 ). DS012813-42 FIGURE 34. Greyscale CCD Interface Example These are the Configuration Register parameters recommended for use as a starting point for most even/odd CCDs: Mode = 1 (Even/Odd mode)* RS Pulse Width = 0 (1 MCLK), RS Pulse Polarity = 0* RS Pulse Position = 10, www.national.com DS012813-44 FIGURE 36. φ1 and φ2 After Inversion 30 Applications Information The final “trick” required to interface a CIS to the LM9811 is the generation of optical black pixels for the LM9811 to clamp to at the beginning of a line. Unlike CCDs, CIS devices do not have a sequence of optical black pixels at the beginning of a line — the first pixel out of a CIS is valid image data. There are several ways to create black pixels for the LM9811 to clamp to. (Continued) Since this is a CCD sensor, the Signal Polarity is set to a 1 (inverted) to match the CCD’s output signal. The number of dummy pixels and optical black reference pixels are given in the CCD’s datasheet. The dummy pixel register should be programmed with the number of dummy pixels in the CCD + 1 (for example, if the CCD has 16 dummy pixels then the register should contain 17). The optical black reference register should be programmed with the number of optical black pixels in the CCD. The PGA gain coefficient register and PGA Gain Source bit are used during calibration (see Section 5.0). The Power Down bit should be set to 0 for normal operation. The Offset Add bit is also programmed during calibration. The VGA and Offset DAC bits are programmed during calibration (Section 5.0). The Test Mode bits should always be set to “0”. DS012813-47 FIGURE 39. CIS Interface Digital Timing The simplest solution is to physically place a light shield (black plastic, tape or metal) over the first 10 or so pixels. This reduces the voltage output of the CIS to nearly 0V, which is adequate for the LM9811 to clamp to. This has the side effect of slightly reducing the number of active pixels available for image capture. A second option is to artifically generate “black” pixels by holding the CLOCK input high for 10 or so RS pulses (Figure 40). This forces the output voltage to zero for the time that the CLOCK input is high, and only one active image pixel is lost. The BLACK signal could be generated by the ASIC/ external logic that generates a pulse on the first rising edge of RS after the TR pulse. 9.0 TYPICAL CIS APPLICATION Many CIS sensors (such as those made by Dyna Image Corporation) have only one clock input, a transfer signal, and an output signal that is referred to ground (Figure 37). Figure 38 shows the analog and digital circuitry required to connect a typical Dyna CIS to the LM9811. DS012813-45 FIGURE 37. CIS Waveforms DS012813-46 FIGURE 38. Minimum CIS Interface Because the CIS requires only one clock with a duty cycle of less than 50%, the LM9811’s RS output is used as the CIS’s CLK source. φ1 and φ2 are not used. The 74HC74 D flip-flop is used to lengthen the transfer pulse (SI, or “Shift In” on the CIS) so that it overlaps the first RS pulse and meets the timing requirement of the CIS (see Figure 39). DS012813-48 FIGURE 40. Generating Artificial Black Pixels Suggested timing for CIS devices is: Mode = 0 (Standard Mode)* RS Pulse Width = 0 (2 MCLKs) 31 www.national.com Applications Information 10.0 HINTS AND COMMON SYSTEM DESIGN PROBLEMS (Continued) RS Pulse Polarity = 0 (or 1 if circuit of Figure 40 is used)* RS Pulse Position = 0 Sample Reference Position = 2 Sample Signal Position = 14 10.1 Reading and Writing to the Configuration Register The Configuration Register sends and receives data LSB (Least Significant Byte) first. Some microcontrollers send out data MSB (Most Significant Byte) first. The order of the bits must be reversed to when using these microcontrollers. φ1/φ2/RS/TR Enable = 0/0/1/1 TR Pulse Width = 0 TR-φ1 Guardband = 0 Note: Unlike the LM9800, the SYNC pin does not have to be held high to send or receive data to or from the Configuration Register. TR Polarity = 1* Signal Polarity = 0 Dummy Pixels = 2 10.2 Setting the Dummy and Optical Black Pixel Registers The minimum value in the Dummy Pixels register is 2 (a value of 0 or 1 will cause errors in the EOC and CCLK timing). Note that the value in this register should be equal to 1 plus the actual number of dummy pixels in the CCD. For example, if the CCD being used with the LM9811 has 12 dummy pixels, this register should be set to 13. The minimum number in the Optical Black Pixels register is 1. Optical Black Pixels = 10 (*Value given in CCD datasheet) As CIS sensors approach pixel rates of 1MHz and above (corresponding to MCLK frequencies of 8MHz and above), the voltage during the reset level becomes less stable, making it difficult to perform CDS on the output (Figure 41). The solution is to create the ground reference externally, shorting the LM9811’s input to ground for half of the time using the φ1 clock, as shown in Figure 42. 10.3 Stretching the TR-φ1 Guardband Some CCDs (Sony’s ILX514, ILX518, and ILX524, for example) require a TR to φ1 guardband greater than the 167ns (2 MCLKs) provided by the LM9811. The circuit shown in Figure 43 produces a 1 µs φROG (transfer) pulse with a guardband between the end of the φROG pulse and the next edge of φ1. This is done by setting the LM9800’s TR pulse width register to 2 µs and using the 74HC4538 to generate a 1 µs pulse inside that TR period to send to the CCD. DS012813-49 FIGURE 41. High Speed CIS Waveforms DS012813-51 FIGURE 43. Stretching the TR-φ1 Guardband Figure 44 shows a different technique for increasing the TR-φ1 guardband and/or increasing the length of the TR pulse by stopping the MCLK during the TR period. When TR initially goes high, the first one-shot (U1A) triggers, effectively disabling the LM9811s MCLK for ≈2 µs, thereby lengthening the TR pulse width by ≈2 µs over the value programmed in the configuration register. On the falling edge of TR, the second one-shot (U1B) fires, disabling the LM9811s MCLK for ≈1 µs and increasing the TR-φ1 guardband by that amount. DS012813-50 FIGURE 42. High Speed CIS Interface www.national.com 32 Applications Information (Continued) DS012813-52 FIGURE 44. Stretching TR and the TR-φ1 Guardband 33 www.national.com 34 Physical Dimensions inches (millimeters) unless otherwise noted 52-Pin Plastic Leaded Chip Carrier (PLCC) Order Number LM9811CCV NS Package Number V52A Dimensions are in millimeters 52-Pin Thin Quad Flatpak Order Number LM9811CCVF NS Package Number VEG52A 35 www.national.com LM9811 10-Bit Greyscale/30-Bit Color Linear CCD Sensor Processor LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life support 1. 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