STV0502 CCD SENSORS ANALOG PROCESSOR IC . . . . . SERIAL BUS CONTROL VIDEO CORRELATED DOUBLE SAMPLING OF THE CCD SIGNAL DIGITALLY CONTROLLED VARIABLE AMPLIFIER AND BLACK CLAMP LEVEL 8 BITS PIXEL RATE ADC AUDIO MICROPHONE PREAMP WITH SWITCHABLE AGC (RANGE 34dB - 60dB) OR FIXED GAIN TQFP44 Full (10 x 10 x 1.40mm) (Plastic Quad Flat Pack) ORDER CODE : STV0502 DESCRIPTION The chip integrates the analog functions needed in a CCD Video Camera, more particularly for videoconferencing purpose. The CCD signal is sampled, amplified to a useful level and digitized by an 8 bits ADC. The gain of the amplifier and the black level clamp can be adjusted by a serial bus. The audio microphone preamplifier allows a microphone to be connected to the chip, which outputs a differential audio line level signal ready for digital conversion or straight amplification. The preamplifier incorporates an AGC to adapt to the income signal level. The AGC is switchable ON/OFF by the serial interface. VCC GND VTOP VBOT TEST ONLY AGC LEVEL OB_CAP NOT USED BLACK_REF VCC GND PIN CONNECTIONS 44 43 42 41 40 39 38 37 36 35 34 VAGCIN 1 33 VBIAS CDS_OUT 2 32 VCC CDS_REF 3 31 AF_OUT- CDS_IN 4 30 AF_OUT+ VSS 5 29 CAGC NOT USED 6 28 ACC NOT USED 27 MIC_REF DATA7 7 8 26 MICRO_IN DATA6 9 25 GND DATA5 10 24 ADC_CLOCK DATA4 11 23 SCLK October 1998 0502-01.EPS FS FCDS OB VSS SDATA_IO VDD VDD DATA0 DATA1 DATA2 DATA3 12 13 14 15 16 17 18 19 20 21 22 1/15 STV0502 PINOUT DESCRIPTION Pin Signal Ana./Dig. Type 1 VAGCIN Analog I Video Variable Gain Input Description 2 CDS_OUT Analog O CDS Output 3 CDS_REF Analog - CDS Reference 4 CDS_IN Analog I CDS Input 5 VSS Digital - ADC Data Ground 8 DATA[7] Digital O ADC Output - MSB 9 DATA[6] Digital O ADC Output 10 DATA[5] Digital O ADC Output 11 DATA[4] Digital O ADC Output 12 DATA[3] Digital O ADC Output 13 DATA[2] Digital O ADC Output 14 DATA[1] Digital O ADC Output 15 DATA[0] Digital O ADC Output - LSB 16 VDD Digital - ADC Data Supply 17 VDD Digital - Digital Supply 18 SDATA_IO Digital I/O 19 VSS Digital - Digital Ground 20 OB Digital I OB Pulse 21 FCDS Digital I FCDS Pulse 22 FS Digital I FS Pulse 23 SCLK Digital I Serial Bus Clock Wire 24 ADC_CLOCK Digital I ADC Clock Input Pulse 25 GND Analog - Microphone Ground 26 MICRO_IN Analog - Microphone Input 27 MICRO-REF Analog - Microphone Internal Reference 28 ACC Analog - Microphone Preamplifier DC Level Capacitor 29 CAGC Analog - Microphone Preamplifier AGC Capacitor 30 AF_OUT+ Analog O Microphone Preamplifier Output (diff. +) 31 AF_OUT- Analog O Microphone Preamplifier Output (diff. -) 32 VCC Analog - Microphone Preamplifier Supply 33 VBIAS Analog - Microphone Internal Supply (regulated) 34 VCC Analog - ADC Supply 35 GND Analog - ADC Ground 36 VTOP Analog - ADC Top Reference 37 VBOT Analog - ADC Bottom Reference 38 TEST ONLY Analog - Test only (AGCOUT/ADCIN) 39 AGCLEVEL Analog - Audio AGC Threshold Configuring Pin 40 OB_CAP Analog - Black Clamp DC Loop Capacitor 42 BLACK_REF Analog - Video Voltage Reference 43 VCC Analog - Video Supply 44 GND Analog - Video Ground 6-7 41 NC NC - - Not to be connected Not to be connected 2/15 0502-01.TBL Serial Interface Data Wire STV0502 BLOCK DIAGRAM VREF CORRELATED DOUBLE SAMPLING VIDEO GAIN AMPLIFIER & A/D CONVERTER INTERFACE 6dB/18dB G=1 G=1 A/D CONV G=1 Range 0-18dB BIAS BIAS AUDIO INTERFACE COMP G=1 BLACK LEVEL ADJUST & CLAMP STV0502 FUNCTIONAL DESCRIPTION 1 - Video Section A CCD signal is provided to the STV0502, via a coupling capacitor, as well as the pulses FS/FCDS. The CDS (Correlated Double Sampling) is performing a clamp of the CCD signal during the FCDS pulse. The signal obtained is then sampled during the FS pulse, and held the rest of the period. The resulting signal is then the difference between the useful pixel level, and the pixel level corresponding to no charge which can vary from one pixel to another. Therefore, the parasitic level offset from one pixel to another is removed. This signal is DC coupled to the ACG, amplified by a variable gain amplif ier, bus co ntrolled (0.07dB step), which gain is in the range +6dB to +23.7dB (17.7dB range). Typically, the amplifier is controlled in order to keep the signal at an optimum level (AGC) to be digitized. An extra 12dB can be added up via a bit of the serial interface. In this case the gain range becomes +18dB up to + 36dB. At this point, the signal is clamped to a Black level during the OB pulse. The black level is 5 bits bus controlled, and its range corresponds to [0 LSB ; 31 LSB] of the ADC. The black level is made with a 5 bits DC frequency DAC, using the same VBOTTOM and VTOP voltage references than the ADC for matching purposes. The clamp is made out of a OB pulse sampled comparator between the DAC output voltage (Black) and the ADC input signal. The comparator has a symetrical current output charging a capacitor. The obtained voltage is buffered and used as a feedback to the AGC input stage. This clamp makes sure that ADCin is matched to the DAC black setting during the OB pulse, disregarding any offset in the AGC path. Then the signal is digitized by a fast ADC, clocked at the pixel rate. The output of the chip is then an 8-bit pixel DATA, ready for digital post-processing. 2 - Audio Section The chip integrates a high gain audio amplifier, in order to process low signals coming from a speech microphone, and provide on its output a line level, differential audio signal, for digital conversion, or power amplification. Two modes can be selected : fixed gain mode or AGC mode. In case of AGC mode, a peak detection of the signal is performed in order to regulate the output signal on a defined level of 1.5VPP or 1VPP (non-diff). This regulated level can be chosen at 1.5VPP or 1VPP thanks to a pin at respectively ground or supply voltage (a pullup resistor to supply is already included on chip), for compatibility purposes between the 502 and various back-end chips. The system includes a Low-Noise fixed amplifier (26dB), and a bias circuitry at the front. 3/15 0502-02.EPS AGC SERIAL BUS INTERFACE VREG PSRR D/A CONV STV0502 FUNCTIONAL DESCRIPTION (continued) threshold, to be regulated at. An external capacitor (CAGC) is used for the AGC time constants. If the signal goes above the threshold, a 500µA current is charging the capacitor with a fast reponse time(attack). In case of very big signals, a second charge cureent of about 5mA is given, in order to reduce the period during which the output signal is saturated. Otherwise, a constant 1µA current discharges the capacitor with a slow response time (decay). The capacitor voltage controls the VCA gain. This constitues the AGC loop. It is followed by a Voltage Controlled Amplifier (range 8dB - 34dB), that can be switched into a fixed 26dB gain amplifier. The VCA output is differential and 2 buffers are driving the two output pins, with a load impedance down to 5kΩ. A bias circuitry and an external capacitor (ACC) form a DC feedback loop on the VCA DC bias, in order to correct any DC offset on the VCA output. Finally, a peak detector (double alternance) is used to compare the output signal with the reference Figure 1 Pixel N Pixel N+1 Pixel N+2 Pixel N+3 Pixel N+4 Pixel N+5 CDS_IN t1 t3 FCDS t2 t4 FS CDS_OUT tPROP ADC_IN Sampling Period Pixel N Pixel N+1 Pixel N+2 Pixel N+3 Pixel N+4 ADC_CLOCK tDADC DATA_OUT Pixel N-4 Pixel N-3 Pixel N-2 Pixel N-1 Pixel N Pixel N+1 3 CLK Pipe-Line Delay t1, t2, t3 and t4 must be kept > 0 in the Application. - tPROP is the propagation delay between CDS_OUT and ADC_IN signals (within the AGC block). - tDADC is the delay on the ADC outputs between the rising edge of the clock and data output. 0502-03.EPS Notation : - t1 is the delay between the falling edge of FCDS and the beginning of the active pixel level from the CCD. - t2 is the delay between the falling edge of FS and the end of the active pixel level from the CCD. Figure 2 CDS_IN = CCD Signal Feedtrough Level Signal Level FCDS CDS_OUT 4/15 0502-04.EPS FS STV0502 FUNCTIONAL DESCRIPTION (continued) Please note that : 1/ On power On conditions, SDATA line is in Write (Input) Mode. 2/ In case of a read pattern, the SDATA line is automatically set to Read (Output mode) during 8 clock cycles (Data D7 - D0) after R/W bit has been sent, and comes back in Write (Input mode) after the 13th clock cycle. 3/ There is no timing restriction between two consecutive patterns (a pattern being defined as one of the two above). 3 - Serial Bus Specification It is a 2-wires (data and clock) serial bus, used as a slave. Clock line is monodirectional (input) and allways sent by the master to the chip, whereas Data line is bidirectional (I/O). There are 3 registers (8 bits), both writable/readable. Each register can be addressed by a 4 bits address word, followed by a R/W bit, and an 8 bits word Data (read/write). 2 main patterns can be sent : Reset Pattern and Read/Write pattern. 3.2 - Register Summary Address (A3-A0) 0000 0001 0001 0001 0010 Register 3.1 -Timings and Protocol The data bit is taken into account when the clock is rising. - Reset Pattern : resets all the registers to their default (Power On) values : format = 16 * (data=1) | 2 * (data=0) (total = 18 clocks) - Read/Write Pattern : format = 4 addr bits | R/W bit | 8 data bits (total = 13 clocks) Video Amplifier Gain Black Level Adjust Video High Gain Select Test Mode Microphone AGC X D Data Format (D7-D0) DDDD.DDDD XXXD.DDDD XXDX.XXXX DDXX.XXXX XXXX.XXXD : unused bits : means useful bits Please note that 3 different functions are merged in register address 01. Figure 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 CLK SDATA 2 CLK Cycles 0502-05.EPS Minimum 16 CLK Cycles Reset Pattern Figure 4 1 2 3 4 5 6 7 8 9 10 11 12 13 CLK A3 A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0 0502-06.EPS SDATA Read/Write Pattern 5/15 STV0502 FUNCTIONAL DESCRIPTION (continued) 3.3 - Control Data Video Amplifier Gain Control (8 bits used) Address : 0000 POR value : 0000.0000 ---> 6dB Gain is expressed from CDSoutput to ADC input (ADC range 1.55VPP) - 0.07dB / LSB step - Overall range (256 steps) : 17.7dB Video Gain (dB) 6 6.07 6.14 ... 7.12 7.19 ... 23.63 23.7 Data 0000.0000 0000.0001 0000.0010 ... 0001.0000 0001.0001 ... 1111.1110 1111.1111 Black Level Adjustment Control (5 bits used) Address : 0001 POR Value : 0001.0000 ---> 16LSB The adjustment is controlling the black reference voltage. However, it is preferred to express the Black level adjustment in terms of the ADC output code variation (in ADC LSBs, compared to the nominal default setting) depending on the Black setting. Typically, 16 LSBs black level is recommended. - 1 ADC LSBs / LSB step - Overall range : 31 ADC LSBs Black Level (ADC Ouput Variation) 0 LSBs 1 LSBs ... 30 LSBs 31 LSBs 6/15 Data XXX0.0000 XXX0.0001 ... XXX1.1110 XXX1.1111 Video High Gain Select (1 bit used) Address : 0001 POR Value : 0 ---> Nominal gain This bit controls an extra 12dB gain in the video path (adding to gain described in previous page). Video High Gain Select Data Nominal Gain XX0X.XXXX Extra 12dB Gain XX1X.XXXX Video AGCOUT Test Signal ON/OFF (2 bits used) Address : 0001 POR Value : 00 ---> High Z pad A pin is reserved to output the ADC input signal, or input the ADC input signal for test and evaluation purpose. Those bits control the state of the output buffer. To limit Xtalk and pollutions, the buffer is in High impedance mode during normal operation. VAGCOUT PIn State Data Normal Operation (High Z Pin) 00XX.XXXX AGC Output Test 10XX.XXXX ADC Input Test 11XX.XXXX Microphone AGC Switch (1 bit used) Address : 0010 POR value : 0000.0000 ---> AGC OFF The switch is controlling the state of the AGC : ON or OFF. In OFF mode, the Micro Preamp. is set at a fixed nominal gain of 52dB. In ON mode, the AGC is operating in a gain range [34dB ; 60dB] (see further in this document for details). Microphone AGC Data OFF 0000.0000 ON 0000.0001 STV0502 Symbol VDD, VCC VI II Tstg Toper Tlead Parameter Supply Voltage Digital Input Pin Voltage Digital Input Pin Current Storage Temperature Operating Temperature Lead Temperature (10s Max.) Value -0.5, 7 -0.5, VDD + 0.5 1.6 +80 0, +70 +260 Unit V V mA o C o C o C 0502-02.TBL ABSOLUTE MAXIMUM RATINGS ESD : The STV0502 withstands 2kV in Human Body Model and 100V in Machine Model for all Pins versus VDD and VSS. Symbol Rth (j-a) Parameter Value Junction-ambient Thermal Resistance Max. Unit o 65 C/W 0502-03.TBL THERMAL DATA ELECTRICAL CHARACTERISTICS Tamb = 25oC, VDD = VCC = 5V, unless otherwise specified Symbol Parameter Test Conditions Min. Typ. Max. Unit 4.5 40 5 55 5.5 70 V mA 0.3 VDD V V µA µA SUPPLY VCC, VDD All Supplies ISUP Total Current Consumption VCC = VDD = 5V CMOS DIGITAL INPUTS VIL VIH IIL IIH Low Level Input Voltage High Level Input Voltage Low Level Input Current High Level Input Current 0.7 VDD -1.0 1.0 CMOS DIGITAL OUTPUTS (4mA drivers) VOL VOH IOL IOH Low Level Output Voltage High Level Output Voltage Low Level Output Current High Level Output Current 0.4 4.0 -4.0 V V mA mA 1 60 700 700 200 200 V MHz % ns ns ns ns 2.4 Slevel fCLK DutyC tDR tDW tR tF SDATA, SCLK Levels Bus Clock Frequency Clock Duty Cycle Delay between CLK Rising Edge and Data Out Delay between CLK Rising Edge and Data In Clock Rise Time Clock Fall Time SCLK Read Mode, see Figure 5 Write Mode, see Figure 5 SCLK SCLK 40 300 300 CMOS 0.5 50 500 500 0502-04.TBL SERIAL INTERFACE Figure 5 tR tF SCLK tDW 0502-07.EPS tDR SDATA_IO 7/15 STV0502 ELECTRICAL CHARACTERISTICS Tamb = 25oC, VDD = VCC = 5V, unless otherwise specified (continued) Symbol Parameter Test Conditions Min. Typ. Max. Unit 8 11 14 kΩ VIDEO CDS RIN Input Resistance Pin 4 CIN Input Capacitance Pin 4 6 pF Input Dynamic Range Pin 4, before output clipping 0.6 0.7 VPP S/H Slew Rate Pin 2, FS high 0.6 0.9 V/15ns CDS_DR S/H Droop Rate Pin 2, FS low -20 +20 mV/µs CDS_HM S/H Hold Mode Feed through Pin 2, FS low, fIN = 1MHz -55 -45 dB CDS Linearity Pin 2, 500mVPP (1) 0.3 1.5 % 0 dB 250 Ω INDyn CDS_SR CDS_lin CDS Gain ROUT OUTload FS FCDS PIX_FRE PSRR Overall Input to Output Gain Pin 2, normal operation CDS Output Impedance Pin 2, FCDS & FS high CDS Ouput Load -2 -1 100 Ω PS Pulse Width See timings 12 ns FSDS Pulse Width See timings 12 ns Pixel Rate Pins 4, 21, 22 6 Power Supply Rejection Measured on Pin 2 (2) 12 MHz 60 dB kΩ VIDEO AMPLIFIER Input Resistance Pin 1 2 Input Capacitance Serial bus from H00 to HFF 18 Min. Gain Max. Gain Minimum Gain Maximum Gain Serial bus = H00/no extra gain Serial bus = HFF/no extra gain Min. Gain Max. Gain Minimum Gain Maximum Gain Gset-err Out_Max pF 6.5 23.2 6 23.7 dB dB Serial bus = H00/extra gain Serial bus = HFF/extra gain 12 35.7 12.5 35.2 dB dB Gain Setting Relative Error Serial bus from H00 to HFF -0.5 0.5 dB Max. Output Signal before clipping Pin 38, VCC = 4.5V G = 6dB, VIN = 0.8VPP G = 23.7dB, VIN = 0.1VPP 1.6 1.6 Square input 10 tR Output Rise Time tF VPP VPP 15 ns Output Fall Time Square input 10 15 ns tPROP AGC Propagation Time Pin 1 to Pin 38 15 20 ns PSRR Power Supply Rejection Measured on Pin 38 (2) 45 dB Xtalk Xtalk from Video to Audio Measured on Pin 38, compared to Pins 20 and 21 (2) 60 dB Notes : 1. Normal operation means FS & FCDS run at specified timings and 12MHz frequency. 2. On a 20Hz to 10MHz frequency range, with 10µF filtering capacitors on all supplies, and well splitted supplies and grounds. 8/15 0502-05.TBL RIN CIN STV0502 ELECTRICAL CHARACTERISTICS Tamb = 25oC, VDD = VCC = 5V, unless otherwise specified (continued) Symbol Parameter Test Conditions Min. Typ. Max. Unit 8 BITS ADC & OB CLAMP OB High Time Constant Pin 38, OB 0 to 1 OB_decay OB Low Time Constant Pin 38, OB 1 to 0 BLK_RAN Black Level Adjust Range Pins 8 to 15, OB high, Serial bus from H00 to H1F 31 LSBs BLK_res Black Level Adjust Resolution Pins 8 to 15, per serial bus LSB step 1 LSBs BLK_LEV Black Level Adjust Pins 8 to 15 Bus = H00 Bus = H1F ADC_DN ADC Input Dynamic Range (output from 0 to 255) 4 -2 Pin 38 test signal above black clamping level (VBOT) fCLK ADC Clock Frequency Pin 24 tPCLK Output Pipeline Delay (3) From a sampling to data out mV/µs mV/ms 29 0 31 2 33 LSBs LSBs 1.4 1.55 1.7 VPP 12 3 MHz 3 CLK cycles tDADC Clock to Data Out (4) CLK positive edge, CLOAD = 20pF 17 ns RLADD Ladder Resistance Between Pins 36 and 37 330 Ω VTOP Top Reference Voltage Pin 36 3.2 3.35 3.5 V VBOT Bottom Reference Voltage Pin 37 1.71 1.8 1.89 V ADC Linearity Data out, input signal between [VBOT + 25mV ; VTOP - 25mV] 1 % ADC_lin 0502-06.TBL OB_rise Notes : 3. The signal is being sampled as long as ADC_CLK is high. 4. See Figure 6 for data reading timing constraint. Figure 6 ADC_IN Sampling Period Pixel N Pixel N+1 ADC_CLOCK tDADC Pixel N-4 Pixel N-3 Pixel N-2 Pixel N-1 Pixel N 0502-08.EPS DATA_OUT Data available on falling edge of clock Due to tDADC, and to make sure the data are read when they are stable, please read the data on the falling edge of the ADC clock. 9/15 STV0502 ELECTRICAL CHARACTERISTICS Tamb = 25oC, VDD = VCC = 5V, unless otherwise specified (continued) Symbol Parameter Test Conditions Min. Typ. Max. Unit MICROPHONE PREAMPLIFIER IN_ref Bias Audio Voltage Pin 26 3.8 V Micro Input Voltage Pin 33 2 V RIN Input Impedance Pin 33 50 kΩ GFIX Overall Gain AGC Mode off 48 50 52 dB GAGC Overall Gain AGC Mode on VAGC = 0.5V VAGC = 4V 54 56 20 58 34 dB dB On Pins 30/31, AGC on, Input = [1.5mVPP ; 30mVPP] AGClevel (Pin 39) = 0 AGClevel (Pin 39) = 5 1.1 0.7 1.5 1 1.9 1.3 VPP VPP Regulated Output Level ALC1 ALC2 500 µA -1 µA Step +6dB, CAGC = 2.2µF 5 ms Step -6dB, CAGC = 2.2µF 2.5 s 2 2 VPP VPP 2.1 V Ich AGC Charge Current Idis AGC Discharge Current All the time with AGC on tATT Output Response Time tDEC Output Response Time OUT_Max Output Clipping Level OUT_DC OUT_OF Output DC Voltage On Pin 29 when signal out above threshold Pins 30/31 AGC off : VIN = 5mVPP AGC on : VIN > 40mVPP 1.7 1.7 Pins 30/31 Channel DC Mismatch Pins 30/31 ROUT Output Impedance Pins 30/31 100 THD Overall THD 1VPP out, 1kHz signal, BW 15kHz 0.15 PSRR PSRR from VCC f = 1kHz, VCC + sine 100mVPP (2) 60 CMRR CMRR from VCC f = 1kHz, VCC + sine 100mVPP (2) 60 Low Cut-off Frequency CIN = 2.2µF, CACC = 10µF HFc High Cut-off Frequency CIN = 2.2µF, CACC = 10µF Xtalk Xtalk from video to audio Measure on Pins 30/31, compared to Pin 38 (2) LFc -350 0 350 mV 0.4 % Ω dB dB 250 20 Hz kHz 60 dB 0502-07.TBL VBIAS Notes : 2. On a 20Hz to 10MHz frequency range, with 10µF filtering capacitors on all supplies, and well splitted supplies and grounds. Figure 7 INPUT +6dB -6dB tDEC tATT 10/15 0502-09.EPS OUTPUT STV0502 I/O DIAGRAMS Figure 8 : VAGCIN Figure 9 : CDS_OUT 1.33kW 1 0502-10.EPS 8.67kW CDS_OUT Figure 10 : CDS_REF 0502-11.EPS 2 Figure 11 : CDS_IN CDS_REF CDS_IN 4 10kW 0502-12.EPS 3 Figure 12 : DATA[7:0] 0502-13.EPS VAGCIN Figure 13 : SDATA_IO DATA[7:0] Pins 8 to 15 SDATA_IO 18 Figure 14 : OB, FCDS, FS, SCLK, ADC_CLOCK Figure 15 : MICRO_IN 220W 0502-17.EPS MICRO_IN 26 0502-16.EPS OB, FCDS, FS SCLK, ADC_CLOCK Pins 20, 21, 22, 23, 24 0502-15.EPS 0502-14.EPS 220W 11/15 STV0502 I/O DIAGRAMS (continued) Figure 16 : MIC_REF Figure 17 : ACC 27 MIC_REF Figure 18 : CAGC 0502-19.EPS 0502-18.EPS 28 ACC Figure 19 : AF_OUT+, AF_OUT- 29 CAGC 10kW AF_OUT+, AF_OUTPins 30/31 Figure 20 : VBIAS 0502-21.EPS 0502-20.EPS 10kW Figure 21 : VTOP 0502-22.EPS 22kW 36 VTOP Figure 22 : VBOT Figure 23 : VAGCOUT 330W 10kW 37 VBOT 38 VAGCOUT 0502-24.EPS 12/15 330W 0502-25.EPS 40kW 10kW 0502-23.EPS 33 VBIAS STV0502 I/O DIAGRAMS (continued) Figure 24 : AGCLEVEL Figure 25 : OB_CAP 0502-26.EPS 0502-27.EPS 40 OB_CAP AGCLEVEL 39 Figure 26 : BLACK_REF 0502-28.EPS 42 BLACK_REF 13/15 STV0502 TYPICAL APPLICATION VCC Video 10m F VDD ADC 10m F 220nF 1m F 42 41 40 39 38 37 36 35 34 VCC BLACK_REF NC OB_CAP AGCLEVEL TESTONLY VBOT VTOP GND VCC 1m F 43 GND 1m F 44 1 VAGCIN 10m F VCC Micro 10m F VBIAS 33 2 CDS_OUT VCC 32 3 CDS_REF AF_OUT- 31 4 CDS_IN AF_OUT+ 30 1m F From CCD LINE OUTPUTS 33nF 6.8m F 5 GND CAGC 29 3.3kW 10m F STV0502 6 NC ACC 28 7 NC 10m F MICRO_REF 27 5.1kW 8 DATA[7] 3 x 1N4148 MICRO_IN 26 1kW 2.2m F 9 DATA[6] GND 25 10 DATA[5] ADC_CLOCK 24 11 DATA[4] SCLK 23 MICROPHONE DATA[7] ADC_CLOCK DATA[0] 14/15 VDD SDATA_IO GND OB FCDS FS 12 13 14 15 16 17 18 19 20 21 22 VDD OB FCDS FS SCLK SERIAL SDATA INTERFACE 0502-29.EPS DATA[1] VDD DATA[2] DATA[0] DATA[3] DATA[1] DATA[4] DATA[2] DATA[5] DATA[3] DATA[6] STV0502 PACKAGE MECHANICAL DATA 44 PINS - FULL PLASTIC QUAD FLAT PACK (THIN) (TQFP) A A2 e 44 A1 34 33 11 23 E3 E1 E B 1 0,10 mm .004 inch SEATING PLANE c 22 Dimensions A A1 A2 B C D D1 D3 e E E1 E3 L L1 K Min. 0.05 1.35 0.30 0.09 0.45 Millimeters Typ. 1.40 0.37 12.00 10.00 8.00 0.80 12.00 10.00 8.00 0.60 1.00 Max. 1.60 0.15 1.45 0.40 0.20 0.75 Min. 0.002 0.053 0.012 0.004 0.018 PM-4Y.EPS K 0,25 mm .010 inch GAGE PLANE Inches Typ. 0.055 0.015 0.472 0.394 0.315 0.031 0.472 0.394 0.315 0.024 0.039 Max. 0.063 0.006 0.057 0.016 0.008 0.030 4Y.TBL L D3 D1 D L1 12 0o (Min.), 7o (Max.) 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