RT8253A 3A, 23V, 340kHz Synchronous Step-Down Converter General Description Features The RT8253A is a high efficiency, monolithic synchronous step-down DC/DC converter that can deliver up to 3A output current from a 4.5V to 23V input supply. The RT8253A's current mode architecture and external compensation allow the transient response to be optimized over a wide range of loads and output capacitors. Cycle by cycle current limit provides protection against shorted outputs and soft-start eliminates input current surge during start up. Fault conditions also include output under voltage protection and thermal shutdown. The low current (<3μA) shutdown mode provides output disconnect, enabling easy power management in battery powered systems. The RT8253A is available in a SOP-8 (Exposed Pad) package. z z z z z z z z z z z z z z z Ordering Information RT8253A Richtek products are : ` 4.5V to 23V Input Voltage Range 3A Output Current Integrated N-MOSFET Switches Current Mode Control Fixed Frequency Operation : 340kHz Output Adjustable from 0.8V to 20V Up to 95% Efficiency Programmable Soft-Start Stable with Low ESR Ceramic Output Capacitors Cycle by Cycle Over Current Protection Input Under Voltage Lockout Output Under Voltage Protection Thermal Shutdown Protection RoHS Compliant and Halogen Free Applications Industrial and Commercial Low Power Systems z Set Top Box z LCD Monitors and TVs Lead Plating System G : Green (Halogen Free and Pb Free) z Green Electronics/Appliances H : UVP Hiccup z Point of Load Regulation of High Performance DSPs L : UVP Latch-Off z Wireless AP/Router Package Type SP : SOP-8 (Exposed Pad-Option 1) Note : ±1.5% High Accuracy Feedback Voltage RoHS compliant and compatible with the current require- z Pin Configurations (TOP VIEW) ments of IPC/JEDEC J-STD-020. ` Suitable for use in SnPb or Pb-free soldering processes. Marking Information RT8253AGSP : Product Number RT8253A GSPYMDNN YMDNN : Date Code DS8253A-02 March 2011 8 BOOT VIN 2 SW GND 3 GND EN 6 COMP 5 FB 9 4 SS 7 SOP-8 (Exposed Pad) www.richtek.com 1 RT8253A Typical Application Circuit 2 VIN 4.5V to 23V CIN 10µF x 2 REN 100k CSS 0.1µF BOOT VIN 1 RT8253A SW 3 7 EN 8 SS 4, 9 (Exposed Pad) GND CBOOT L 100nF 10µH R1 31.25k FB 5 COMP 6 CC 3.3nF RC 15k VOUT 3.3V/3A COUT 22µF x 2 R2 10k CP Open Functional Pin Description Pin No. 1 BOOT 2 VIN Pin Function Bootstrap for High Side Gate Driver. Connect 0.1μF or greater ceramic capacitor from BOOT to SW pins. Input Supply Voltage. Must bypass with a suitably large ceramic capacitor. 3 SW Phase Node Connect to external L-C filter. 4, 9 (Exposed Pad) Pin Name GND 5 FB 6 COMP 7 EN 8 SS www.richtek.com 2 Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. Feedback Input Pin. This pin is connected to the converter output. It is used to set the output of the converter to regulate to the desired value via an internal resistive divider. For an adjustable output, an external resistive divider is connected to this pin. Compensation Node. COMP is used to compensate the regulation control loop. Connect a series RC network from COMP to GND. In some cases, an additional capacitor from COMP to GND is required. Enable Input Pin. A logic high enables the converter; a logic low forces the RT8253A into shutdown mode reducing the supply current to less than 3μA. Attach this pin to VIN with a 100kΩ pull up resistor for automatic startup. Soft-Start Control Input. SS controls the soft-start period. Connect a capacitor from SS to GND to set the soft-start period. A 0.1μF capacitor sets the soft-start period to 13.5ms. DS8253A-02 March 2011 RT8253A Function Block Diagram VIN Internal Regulator Oscillator 340kHz / 110kHz Slope Comp Shutdown Comparator VA VCC 1.2V + Foldback Control - 5k EN 0.4V Lockout Comparator + 2.7V Current Sense Amplifier + VA - + BOOT UV Comparator 3V VCC S + R Current Comparator Q 85mΩ Q 85mΩ SW GND 6µA 0.8V SS FB DS8253A-02 March 2011 + +EA - COMP www.richtek.com 3 RT8253A Absolute Maximum Ratings z z z z z z z z z z z (Note 1) VIN -----------------------------------------------------------------------------------------------------------------SW ----------------------------------------------------------------------------------------------------------------BOOT ------------------------------------------------------------------------------------------------------------All Other Voltages ---------------------------------------------------------------------------------------------BOOT − SW ----------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C −0.3V to 25V −0.3V to (VIN + 0.3V) (SW−0.3V) to (SW + 6V) −0.3V to 6V −0.3V to 6V SOP-8 (Exposed Pad) ---------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) SOP-8 (Exposed Pad), θJA ----------------------------------------------------------------------------------SOP-8 (Exposed Pad), θJC ---------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------Junction Temperature -----------------------------------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------------ESD Susceptibility (Note 3) HBM (Human Body Mode) ----------------------------------------------------------------------------------MM (Machine Mode) ------------------------------------------------------------------------------------------- 1.333W Recommended Operating Conditions z z z 75°C/W 15°C/W 260°C 150°C −65°C to 150°C 2kV 200V (Note 4) Supply Voltage, VIN -------------------------------------------------------------------------------------------- 4.5V to 23V Junction Temperature Range --------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range --------------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VIN = 12V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Shutdown Supply Current VEN = 0V -- 0.5 3 μA Supply Current VEN = 3 V, VFB = 0.9V -- 0.8 1.2 mA 0.788 0.8 0.812 V -- 940 -- μA/V RDS(ON)1 -- 85 -- mΩ RDS(ON)2 -- 85 -- mΩ VEN = 0V, VSW = 0V -- 0 10 μA Min. Duty Cycle, VBOOT − VSW = 4.8V -- 5.8 -- A -- 5.6 -- A/V 300 340 380 kHz Feedback Reference Voltage Error Amplifier Transconductance High Side Switch On Resistance Low Side Switch On Resistance High Side Switch Leakage Current VFB 4.5V ≤ VIN ≤ 23V gEA ΔI C = ± 10μA Upper Switch Current Limit COMP to Current Sense Transconductance Oscillation Frequency f OSC1 Short Circuit Oscillation Frequency f OSC2 VFB = 0V -- 110 -- kHz Maximum Duty Cycle DMAX VFB = 0.7V -- 93 -- % Minimum On Time t ON -- 100 -- ns gCS To be continued www.richtek.com 4 DS8253A-02 March 2011 RT8253A Parameter Symbol Test Conditions Min Typ Max Unit 3.8 4.2 4.5 V -- 320 -- mV Input Under Voltage Lockout Threshold Input Under Voltage Lockout Threshold Hysteresis Logic-High EN Threshold Voltage Logic-Low VIH 2.7 -- 5.5 VIL -- -- 0.4 Soft-Start Current ISS VSS = 0V -- 6 -- μA Soft-Start Period tSS CSS = 0.1μF -- 13.5 -- ms Thermal Shutdown TSD -- 150 -- °C VIN Rising V Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in natural convection at TA = 25°C on a high effective thermal conductivity four-layer test board of JEDEC 51-7 thermal measurement standard. The measurement case positions of θJC are on the lead of the SOP package and the expose pad for the SOP(Exposed Pad) package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. DS8253A-02 March 2011 www.richtek.com 5 RT8253A Typical Operating Characteristics Efficiency vs. Load Current Reference Voltage vs. Input Voltage 104 0.820 96 0.815 Reference Voltage (V) 88 Efficiency (%) 80 72 VIN = 4.5V VIN = 12V VIN = 23V 64 56 48 40 32 24 16 8 0.010 0.100 1.000 0.805 0.800 0.795 0.790 VIN = 4.5V to 23V, VOUT = 3.3V, VEN = VIN, IOUT = 0.5A 0.785 VOUT = 3.3V, VEN = VIN 0 0.001 0.810 0.780 10.000 4 Load Current (A) 0.815 3.375 0.810 0.805 0.800 0.795 25 50 75 100 3.350 22 25 VIN = 4.5V VIN = 12V VIN = 23V 3.325 3.300 3.275 3.250 125 3.200 0.001 0.01 Temperature (°C) 0.1 1 10 Load Current (A) Switching Frequency vs. Temperature Switching Ferquency vs. Input Voltage 380 380 375 370 365 360 355 350 345 340 335 330 325 320 315 310 305 300 Switching Frequency (kHz)1 Switching Frequency (kHz) 1 19 VIN = 12V, VOUT = 3.3V, VEN = VIN 0.785 0 16 3.225 VIN = 12V, VOUT = 3.3V, VEN = VIN, IOUT = 0.5A -25 13 Output Voltage vs. Load Current 3.400 Output Voltage (V) Reference Voltage (V) Reference Voltage vs. Temperature -50 10 Input Voltage (V) 0.820 0.790 7 VIN = 4.5V to 23V, VOUT = 3.3V, VEN = VIN, IOUT = 0.5A 370 360 350 340 330 320 VIN = 12V, VOUT = 3.3V, VEN = VIN, IOUT = 0.5A 310 300 4 7 10 13 16 Input Voltage (V) www.richtek.com 6 19 22 25 -50 -25 0 25 50 75 100 125 Temperature (°C) DS8253A-02 March 2011 RT8253A Current Limit vs. Temperature Current Limit vs. Duty Cycle 8.0 7.0 Current Limit (A) Current Limit (A) 1 7.5 6.5 6.0 5.5 5.0 VIN = 4.5V to 23V, VOUT = 3.3V, VEN = VIN 4.5 4.0 0 15 30 45 60 75 90 8.00 7.75 7.50 7.25 7.00 6.75 6.50 6.25 6.00 5.75 5.50 5.25 5.00 4.75 4.50 4.25 4.00 VIN = 12V, VOUT = 3.3V, VEN = VIN -50 105 -25 0 25 50 75 100 Duty Cycle (%) Temperature (°C) Load Transient Response Load Transient Response VOUT (200mV/Div) VOUT (200mV/Div) I LOAD (2A/Div) I LOAD (2A/Div) VIN = 12V, VOUT = 3.3V, VEN = VIN, IOUT = 1.5A to 3A VIN = 12V, VOUT = 3.3V, VEN = VIN, IOUT = 0A to 3A Time (100μs/Div) Time (100μs/Div) Switching Waveform Switching Waveform VOUT (10mV/Div) VOUT (10mV/Div) VSW (10V/Div) VSW (10V/Div) IL (2A/Div) IL (2A/Div) VIN = 12V, VOUT = 3.3V, VEN = VIN, IOUT = 3A Time (1μs/Div) DS8253A-02 March 2011 125 VIN = 12V, VOUT = 3.3V, VEN = VIN, IOUT = 1.5A Time (1μs/Div) www.richtek.com 7 RT8253A Power On From VIN Power Off From VIN VIN (10V/Div) VIN (5V/Div) VOUT (5V/Div) VOUT (2V/Div) IL (5A/Div) IL (2A/Div) VIN = 12V, VOUT = 3.3V, VEN = VIN, IOUT = 3A VIN = 12V, VOUT = 3.3V, VEN = VIN, IOUT = 3A Time (4ms/Div) Time (4ms/Div) Power On From EN Power Off From EN VEN (5V/Div) VEN (5V/Div) VOUT (2V/Div) VOUT (2V/Div) IL (2A/Div) IL (2A/Div) VIN = 12V, VOUT = 3.3V, VEN = VIN, IOUT = 3A Time (4ms/Div) www.richtek.com 8 VIN = 12V, VOUT = 3.3V, VEN = VIN, IOUT = 3A Time (4ms/Div) DS8253A-02 March 2011 RT8253A Application Information The RT8253A is a single phase buck PWM converter with internal N-MOSFET switches. It provides single feedback loop, current mode control with fast transient response. An internal 0.8V reference allows the output voltage to be precisely regulated for low output voltage applications. A fixed switching frequency (340kHz) oscillator is integrated to eliminate external component count. The RT8253A also supports programmable soft start function by an external capacitor. Protection features include over current protection, under voltage protection and input Under Voltage Lockout (UVLO). PWM Operation The RT8253A utilizes DEM control to improve light load efficiency. Depending on the load current, the controller automatically operates in Diode Emulation Mode (DEM) or in Continuous Conduction Mode (CCM) with fixed frequency PWM. At light load condition, the RT8253A automatically operates in diode emulation mode to reduce switching frequency to improve efficiency. As the output current decreases from heavy load condition, the inductor current decreases, and eventually the inductor valley current decreases to zero, which is the boundary between continuous conduction mode and discontinuous conduction mode. By emulating the behavior of diodes, the low side MOSFET allows only partial negative current to flow when the inductor freewheeling current becomes negative. As the load current further decreases, it takes longer and longer to discharge the output capacitor to the level that allows the next UGATE on-time to begin. When the output current increases from light load to heavy load, the switching frequency increases to the CCM value as the inductor current reaches the continuous conduction condition. The controller will then operate in continuous conduction mode with 340kHz fixed PWM switching frequency. Output Voltage Setting Connect a resistive voltage divider at the FB pin between VOUT and GND to adjust the respective output voltage between 0.8V and 20V (Figure 1). Choose R2 to be approximately 10kΩ, and solve for R1 using the equation : DS8253A-02 March 2011 ⎛ ⎛ R1 ⎞ ⎞ VOUT = VFB x ⎜ 1 + ⎜ ⎟⎟ ⎝ ⎝ R2 ⎠ ⎠ where VFB is 0.8V (typ.). VOUT R1 FB RT8253A R2 GND Figure 1. Setting VOUT with a Resistive Voltage Divider External Bootstrap Diode & Capacitor The bootstrap capacitor must be 0.1μF and located between the BOOT pin and SW pin. This capacitor provides the gate driver voltage for the high side MOSFET and should be a high quality ceramic type with X7R or X5R grade dielectric for temperature stability. An external bootstrap diode may enhance the efficiency of the regulator and it is recommended to add one between an external 5V source and the BOOT pin (Figure 2). The applicable conditions of the external bootstrap diode are as follows : z Input voltage is lower than 5.5V; and VOUT z Duty cycle is high: D = >65% VIN In these cases, the external 5V source can be a fixed 5V from the system or the output of the RT8253A. Note that the external boot voltage must be lower than 5.5V. 5V BOOT RT8253A 0.1µF SW Figure 2. External Bootstrap Diode & Capacitor Chip Enable and Disable The EN pin is the RT8253A enable input. Drive EN below the precise input falling edge trip level to place the RT8253A in its low power shutdown state. The RT8253A quiescent current drops to lower than 3μA while in shutdown. When www.richtek.com 9 RT8253A shutdown mode is activated, the RT8253A will stop switching. The accurate 0.4V falling edge threshold on the EN pin can be used to detect a specific analog voltage level and to shutdown the device. Once in shutdown, the 2.7V rising edge threshold must be triggered to reactivate the power up sequence. For external timing control (e.g. RC), the EN pin can also be externally pulled high by adding a REN* resistor and CEN* capacitor from the VIN pin. For general applications, the EN pin is externally pulled high by adding a 100kΩ from the VIN pin (see Figure 3). period of time and then recover automatically. The Hiccup Mode UVP can reduce input current in short circuit conditions. Latch Off Mode For the RT8253AL, Latch Off Mode Under Voltage Protection (UVP) function is provided. When the FB voltage drops below half of the feedback voltage, VFB, the UVP function will be triggered and the RT8253AL will shut down in Latch Off Mode. In shutdown condition, the RT8253AL can only be reset through EN or power input VIN. UVLO Protection The RT8253A has an input under voltage lockout protection (UVLO). If the input voltage exceeds the UVLO rising threshold voltage (4.2V typ.), the converter will reset and prepare the PWM for operation. If the input voltage falls below the UVLO falling threshold voltage during normal operation, the device will stop switching. The UVLO rising and falling threshold voltage has a hysteresis to prevent noise caused reset. External Soft-Start (SS) It is highly recommended to program the soft start time externally because it is not included internally. The RT8253A effectively uses the lower voltage of the internal voltage reference or the SS pin voltage as the power supply's reference voltage which is fed into the error amplifier and regulate accordingly. A capacitor (CSS) between the SS pin and ground implements a soft start time. The RT8253A has an internal pull up current source of 6μA that charges the external soft start capacitor. The equation for the soft start time is shown below : tSS = CSS x VREF ISS where VREF is 0.8V and ISS current is 6μA. Generally, a 0.1μF capacitor is used and the soft start time will be 13.5ms (typ.) Under Voltage Protection Hiccup Mode For the RT8253AH, Hiccup Mode Under Voltage Protection (UVP) function is provided. When the FB voltage drops below half of the feedback voltage, VFB, the UVP function will be triggered and the RT8253AH will shut down for a www.richtek.com 10 Input Inrush Current To calculate the input inrush current, the following equation can be used : IINRUSH = COUT x VOUT tSS where IINRUSH is the input current during start up, COUT is the total output capacitance, VOUT is the desired output voltage, and tSS is the soft start time. If the inrush current is higher than the current limit level, current limit will be triggered. Inductor Selection The switching frequency (on-time) and operating point (% ripple or LIR) determine the inductor value as shown below : L= VOUT x(VIN − VOUT ) fSW x LIR x ILOAD(MAX) x VIN where LIR is the ratio of the peak to peak ripple current to the average inductor current. Find a low loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK) : IPEAK = ILOAD(MAX) + ⎡⎣(LIR/2 ) xILOAD(MAX) ⎤⎦ The calculation above shall serve as a general reference. To further improve transient response, the output inductor can be reduced further. This needs to be considered along with the selection of the output capacitor. DS8253A-02 March 2011 RT8253A Input Capacitor Selection For a given output voltage sag specification, the ESR value can be determined. Voltage rating and current rating are the key parameters in selecting the input capacitor. Generally, the input capacitor should have a voltage rating 1.5 times greater than the maximum input voltage to be considered a conservatively safe design. Another parameter that has influence on the output voltage sag is the equivalent series inductance (ESL). The rapid change in load current results in di/dt during transient. Therefore ESL contributes to part of the voltage sag. Use a capacitor that has low ESL to obtain better transient performance. Generally, using several capacitors connected in parallel will have better transient performance than using one single capacitor for the same total ESR. The input capacitor is used to supply the input RMS current, which can be approximately calculated using the following equation : IIN_RMS = ILOAD x ⎛ V ⎞ VOUT x ⎜ 1− OUT ⎟ VIN V ⎝ IN ⎠ The next step is to select a proper capacitor for RMS current rating. For a good design use more than one capacitor with low Equivalent Series Resistance (ESR) in parallel to form a capacitor bank. Unlike the electrolytic capacitor, the ceramic capacitor has relatively low ESR and can reduce the voltage deviation during load transient. However, the ceramic capacitor can only provide low capacitance value. Therefore, using a mixed combination of electrolytic capacitor and ceramic capacitor can also have better transient performance. Output Capacitor Selection EMI Consideration The output capacitor and inductor form a low pass filter in the buck topology. In steady state condition, the ripple current flowing into/out of the capacitor results in ripple voltage. The output voltage ripple (Vp-p) can be calculated by the following equation. Since parasitic inductance and capacitance effects in PCB circuitry would cause a spike voltage on the SW pin when high side MOSFET is turned on/off, this spike voltage on SW may impact EMI performance in the system. In order to enhance EMI performance, there are two methods to suppress the spike voltage. One method is to place an RC snubber between SW and GND and locate them as close as possible to the SW pin (see Figure 3). Another way is adding a resistor in series with the bootstrap capacitor, CBOOT, but this will decrease the driving capability to the high side MOSFET. It is strongly recommended to reserve the R-C snubber during PCB layout for EMI improvement. Moreover, reducing the SW trace area and keeping the main power in a small loop will be helpful for EMI performance. For detailed PCB layout guideline, please refer to the section on Layout Consideration. ⎛ ⎞ 1 VP−P = LIR x ILOAD(MAX) x ⎜ ESR + ⎟ 8 x COUT x fSW ⎠ ⎝ When load transient occurs, the output capacitor supplies the load current before the controller can respond. Therefore, the ESR will dominate the output voltage sag during load transient. The output voltage undershoot (VSAG) can be calculated by the following equation : VSAG = ΔILOAD x ESR 2 VIN 4.5V to 23V Chip Enable REN* CIN 10µF x 2 BOOT VIN 1 RBOOT* CBOOT 0.1µF RT8253A 7 EN SW 3 Cs* CSS 0.1µF 4, 9 (Exposed Pad) GND VOUT 3.3V/3A Rs* CEN* 8 SS L 10µH R1 31.25k COUT 22µF x 2 FB 5 COMP 6 RC 15k CC 3.3nF R2 10k CP NC Figure 3. Reference Circuit with Snubber and Enable Timing Control DS8253A-02 March 2011 www.richtek.com 11 RT8253A VIN Thermal Shutdown Oscillator Current Sense Slope Comp GM + The RT8253A uses a high gain Operational Transconductance Amplifier (OTA) as the error amplifier. As Figure 4 shows, the OTA works as the voltage controlled current source. The characteristic of OTA is shown as below : ΔIOUT ,where ΔVM = ( V + ) − ( V −) ΔVM VREF R2 VCOMP CC RC CP Figure 5. Typical Current Mode Buck Converter with Type-II Compensator The modulator transfer function is the small signal transfer function of VOUT/VCOMP (output voltage over the error amplifier output). According to the derivation of the Ridley’s thesis, the transfer function is dominated by a DC gain, a double pole, a low frequency pole, and an ESR zero as shown in Figure 6. 1 RLOAD x TS 1+ x [mC x (1− D) − 0.5] L x Fp (s) x Fh (s) x + GM - R1 VOUT ≅ RLOAD x gCS VCOMP and ΔVCOMP = ΔIOUT x ZOUT V- ESR COMP The RT8253A is a current mode converter and requires external compensation to have an accurate output voltage regulation with fast transient response. The main concern of compensation deals with the position of the capacitor ESR zero and mid frequency to high frequency gain boost. V+ VOUT COUT FB Loop Compensation GM = L PWM + Control + Current Comparator - The device implements an internal thermal shutdown function to protect itself when the junction temperature exceeds 150°C. The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal shutdown threshold. Once the die temperature decreases below 150°C, the device reinstates the power up sequence. IOUT VCOMP ZOUT Figure 4. Operational Transconductance Amplifier, OTA Figure 5 shows a typical buck control loop using Type-II compensator. The control loop consists of the power stage, current comparator and a compensation network. The current comparator compares VCOMP with the sum of current sense and slope comp to provide Pulse Width Modulated (PWM) gate driving signal with the oscillator. The PWM wave is smoothed out by the output filter, L and COUT. The output voltage (VOUT) is sensed and fed to the inverting input of the error amplifier. where RLOAD is the load resistor; gCS is the current sense transconductance; mC is the slope comp value; D is the duty cycle; TS is the switching period. And : Fp (s) = 1 + sCOUT x ESR s 1+ ωp where ωp = COUT TS 1 + x RLOAD L x COUT x [mc x (1− D) − 0.5] And 1 Fh (s) = 1+ www.richtek.com 12 S S2 + 2 ωnQp ωn DS8253A-02 March 2011 RT8253A where Qp = ωn = Thermal Considerations 1 Π x [mc x (1 − D) − 0.5 ] Π TS The goal of the compensation network is to provide adequate phase margin (usually greater than 45 degrees) and the highest bandwidth (0dB crossing frequency). It is also recommended to manipulate loop frequency response that its gain crosses over 0dB at a slope of -20dB/dec. According to Figure 5, the compensation network frequency is shown as below : fP1 = 0 For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : PD(MAX) = (TJ(MAX) − TA) / θJA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. 1 ⎛ C xC ⎞ 2Π x RC x ⎜ P C ⎟ ⎝ CP + CC ⎠ 1 fz = 2Π x CC x RC For recommended operating condition specifications of the RT8253A, the maximum junction temperature is 125°C and TA is the ambient temperature. The junction to ambient thermal resistance, θ JA , is layout dependent. For Determining the 0dB crossing frequency (fC, control loop bandwidth) is the first step of compensator design. Usually, fC is set to 0.1 to 0.5 times switching frequency. The second step is to calculate the open loop modulator gain and find out the gain loss at fC. The third step is to design a compensator gain that can compensate the modulator gain loss at fC. The final step is to design fZ and fP2 to make loop have sufficient phase margin. PD(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W for SOP-8 (Exposed Pad) package Gain (dB) f Z is designed to cancel the low frequency pole of modulator. fP2 is usually placed below switching frequency (typically, 0.5 to 1 times switching frequency) to eliminate high frequency noise. Zero generated by Compensation network, fZ Pole generated by Compensation network, fP2 fC Double pole generated by Fh (s) 0 Pole generated by FP (s) Zero generated by ESR and COUT of FP (s) Modulation Gain Compensation Gain Loop Gain Frequency (Hz) SOP-8 (Exposed Pad) packages, the thermal resistance, θJA, is 75°C/W on a standard JEDEC 51-7 single layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formula : The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA. For the RT8253A package, the derating curve in Figure 7 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. Maximum Power Dissipation (W)1 fP2 = 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 Four-Layer PCB 0 Figure 6. Typical Bode Plot of a Current Mode Buck Converter DS8253A-02 March 2011 25 50 75 100 125 Ambient Temperature (°C) Figure 7. Derating Curve for RT8253A Package www.richtek.com 13 RT8253A Layout Considerations Layout is very important in high frequency switching converter design. PCB could radiate excessive noise and contribute to the converter instability with improper layout. Certain points must be considered before starting a layout using the RT8253A (Figure 8). ` ` Keep the traces of the main current paths as short and wide as possible. ` SW node is with high frequency voltage swing and should be kept at small area. Keep sensitive components away from SW node to prevent stray capacitive noise pick up. ` Ensure all feedback network connections are short and direct. Place the feedback network and compensation components are close to the chip as possible. ` The GND pin and Exposed Pad should be connected to a strong ground plane for heat sinking and noise protection. ` An example of PCB layout guide is shown in Figure 8 for reference. Put the input capacitor as close as possible to the device pins (VIN and GND). Input capacitor must be placed as close to the IC as possible. GND VIN CIN The feedback components must be connected as close to the device as possible. SW GND VIN CS BOOT CIN L VOUT C S* COUT RS* COUT VIN 2 SW 3 GND 4 GND REN 8 SS 7 EN 6 COMP 5 FB 9 CC CP RC R1 R2 SW should be connected to inductor by wide and short trace. Keep sensitive components away from this trace. VOUT GND Figure 8. PCB Layout Guide www.richtek.com 14 DS8253A-02 March 2011 RT8253A Outline Dimension H A M EXPOSED THERMAL PAD (Bottom of Package) Y J X B F C I D Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 4.801 5.004 0.189 0.197 B 3.810 4.000 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.510 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.170 0.254 0.007 0.010 I 0.000 0.152 0.000 0.006 J 5.791 6.200 0.228 0.244 M 0.406 1.270 0.016 0.050 X 2.000 2.300 0.079 0.091 Y 2.000 2.300 0.079 0.091 X 2.100 2.500 0.083 0.098 Y 3.000 3.500 0.118 0.138 Option 1 Option 2 8-Lead SOP (Exposed Pad) Plastic Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. DS8253A-02 March 2011 www.richtek.com 15