DS89C387 Twelve Channel CMOS Differential Line Driver General Description The driver’s input (DI) is compatible with both TTL and CMOS signal levels. The DS89C387 is a high speed twelve channel CMOS differential driver that meets the requirements of TIA/EIA-422-B. The DS89C387 features a low ICC specification of 1.5 mA maximum, which makes it ideal for battery powered and power conscious applications. The device replaces three DS34C87s and offers a PC board space savings up to 30%. The twelve channel driver is available in a SSOP package. The device is ideal for wide parallel bus applications. Each TRI-STATE ® enable (EN) allows the driver outputs to be active or in a HI-impedance off state. Each enable is common to only two drivers for flexibility and control. The drivers may be disabled to turn off load current and to save power when data is not being transmitted. n Low power ICC: 1.5 mA maximum n Meets TIA/EIA-422-B (RS-422) n Guaranteed AC parameters: — Maximum driver skew −3 ns — Maximum transition time −10 ns n Available in SSOP packaging: — Requires 30% less PCB space than 3 DS34C87TMs Connection Diagram Functional Diagram Features 48L SSOP DS89C387 DS012086-2 1/6 of package Truth Table Enable Input EN DI DO Outputs DO* L X Z Z H H H L H L L H DS012086-1 Order Number DS89C387TMEA See NS Package Number MS48A TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1998 National Semiconductor Corporation DS012086 www.national.com DS89C387 Twelve Channel CMOS Differential Line Driver May 1995 Absolute Maximum Ratings (Notes 1, 2) Lead Temperature (TL) (Soldering 4 sec.) 260˚C This device does not meet 2000V ESD rating. (Note 11) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Operating Conditions Supply Voltage (VCC) −0.5 to 7.0V −1.5 to VCC +1.5V DC Voltage (VIN) −0.5 to 7V DC Output Voltage (VOUT) ± 20 mA Clamp Diode Current (IIK, IOK) ± 150 mA DC Output Current, per pin (IOUT) ± 500 mA DC VCC or GND Current (ICC) −65˚C to +150˚C Storage Temperature Range (TSTG) Maximum Power Dissipation (PD) @ 25˚C (Note 3) SSOP Package 1359 mW Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) DS89C387T Input Rise or Fall Times (tr, tf) Min 4.50 0 Max 5.50 VCC Units V V −40 +85 500 ˚C ns DC Electrical Characteristics (Notes 2, 4) VCC = 5V ± 10% (unless otherwise specified) Symbol VIH Parameter Conditions High Level Input Min Max Units 2.0 Typ VCC V GND 0.8 V Voltage VIL Low Level Input Voltage VOH VOL High Level Output VIN = VIH or VIL, Voltage IOUT = −20 mA VIN = VIH or VIL, Low Level Output Voltage VT Differential Output Voltage |VT|–|VT| Difference In Differential Output VOS Common Mode Output Voltage |VOS–VOS| Difference In Common Mode Output IIN Input Current ICC Quiescent Supply Current IOZ TRI-STATE Output Leakage Current ISC Output Short Circuit Current IOFF 2.5 3.4 0.3 IOUT = 48 mA RL = 100Ω 2.0 2.0 (Note 5) RL = 100Ω (Note 5) VIN = VCC, GND, VIH, or VIL IOUT = 0 µA, 600 VIN = VCC or GND VIN = 2.4V or 0.5V (Note 6) VOUT = VCC or GND −115 Control = VIL VIN = VCC or GND Power Off Output (Notes 5, 7) VCC = 0V Leakage Current (Note 5) −30 VOUT = 6V VOUT = −0.25V 0.5 3.1 (Note 5) RL = 100Ω (Note 5) RL = 100Ω V V V 0.4 V 3.0 V 0.4 V ± 1.0 µA 1500 µA 0.8 2.0 mA ± 0.5 ± 5.0 µA −150 mA 100 µA −100 µA Note 1: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The table of “Electrical Characteristics” provide conditions for actual device operation. Note 2: Unless otherwise specified, all voltages are referenced to ground. All currents into device pins are positive; all currents out of device pins are negative. Note 3: Ratings apply to ambient temperature at 25˚C. Above this temperature derate SSOP (MEA) Package 10.9 mW/˚C. Note 4: Unless otherwise specified, min/max limits apply across the −40˚C to 85˚C temperature range. All typicals are given for VCC = 5V and TA = 25˚C. Note 5: See TIA/EIA-422-B for exact test conditions. Note 6: Measured per input. All other inputs at VCC or GND. Note 7: This is the current sourced when a high output is shorted to ground. Only one output at a time should be shorted. www.national.com 2 Switching Characteristics (Note 4) VCC = 5V ± 10%, tr, tf ≤ 6 ns (Figures 1, 2, 3, 4) Symbol tPLH, tPHL Parameter Propagation Delay Min Typ Max Units S1 Open Conditions 2 6 11 ns 0 Input to Output Skew (Note 8) S1 Open 0.5 3 ns tTLH, tTHL Differential Output Rise S1 Open 6 10 ns ns And Fall Times tPZH Output Enable Time S1 Closed 12 25 tPZL Output Enable Time S1 Closed 13 26 ns tPHZ Output Disable Time (Note 9) S1 Closed 4 8 ns tPLZ Output Disable Time (Note 9) S1 Closed 6 12 CPD Power Dissipation ns 100 pF 6 pF Capacitance (Note 10) CIN Input Capacitance Note 8: Skew is defined as the difference in propagation delays between complementary outputs at the crossing point. Note 9: Output disable time is the delay from the control input being switched to the output transistors turning off. The actual disable times are less than indicated due to the delay added by the RC time constant of the load. Note 10: CPD determines the no load dynamic power consumption, PD = CPD V2CC f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC. Note 11: ESD Rating: HBM (1.5 kΩ, 100 pF) Inputs ≥ 1500V Outputs ≥ 1000V EIAJ (0Ω, 200 pF) All Pins ≥ 350V Logic Diagram DS012086-3 3 www.national.com Parameter Measurement Information DS012086-4 C1 = C2 = C3 = 40 pF (including Probe and Jig Capacitance), R1 = R2 = 50Ω, R3 = 500Ω FIGURE 1. AC Test Circuit DS012086-5 FIGURE 2. Propagation Delays DS012086-6 FIGURE 3. Enable and Disable Times www.national.com 4 Parameter Measurement Information (Continued) DS012086-7 Input pulse; f = 1 MHz, 50%, tr ≤ 6 ns, tf ≤ 6 ns FIGURE 4. Differential Rise and Fall Times Typical Application DS012086-8 * RT is optional although highly recommended to reduce reflection. FIGURE 5. Two-Wire Balanced System, RS-422 not always consistant. Therefore, skew calculated in this datasheet, may not be calculated the same as skew defined in another. This is important to remember whenever making a skew comparison. Skew may be calculated for the DS89C387, from many different propagation delay measurements. They may be classified into three categories, single-ended, differential, and complementry. Single-ended skew is calculated from tPHL and tPLH measurements (see Figures 6, 7). Differential skew is calculated from tPHLD and tPLHD measurements (see Figures 8, 9). Complementry skew is calculated from tPHL and tPLH measurements (see Figures 10, 11). Application Information SKEW Skew may be thought of in a lot of different ways, the next few paragraphs should clarify what is represented by “Skew” in the datasheet and how it is determined. Skew, as used in this databook, is the absolute value of a mathematical difference between two propagation delays. This is commonly accepted throughout the semiconductor industry. However, there is no standardized method of measuring propagation delay, from which skew is calculated, of differential line drivers. Elucidating, the voltage level, at which propagation delays are measured, on both input and output waveforms are (Circuit 2) (Circuit 1) DS012086-9 DS012086-10 FIGURE 6. Circuits for Measuring Single-Ended Propagation Delays (See Figure 7) 5 www.national.com Application Information (Continued) Waveforms for Circuit 1 Waveforms for Circuit 2 DS012086-12 DS012086-11 FIGURE 7. Propagation Delay Waveforms for Circuit 1 and Circuit 2 (See Figure 6) In Figure 2, VX, where X is a number, is the waveform voltage level at which the propagation delay measurement either starts or stops. Furthermore, V1 and V2 are normally identical. The same is true for V3 and V4. However, as mentioned before, these levels are not standardized and may vary, even with similar devices from other companies. Also note, NC (no connection) in Figure 1 means the pin is not used in propagation delay measurement for the corresponding circuit. The single-ended skew provides information about the pulse width distortion of the output waveform. The lower the skew, the less the output waveform will be distorted. For best case, skew would be zero, and the output duty cycle would be 50%, assuming the input has a 50% duty cycle. However, if V3 and V4 are specified voltages, then V3 and V4 are less likely to be equal to the crossing point voltage. Thus, the differential propagation delays will not be measured to zero volts on the differential waveform. The differential skew also provides information about the pulse width distortion of the differential output waveform relative to the input waveform. The higher the skew, the greater the distortion of the differential output waveform. Assuming the input has a 50% duty cycle, the differential output will have a 50% duty cycle if skew equals zero and less than a 50% duty cycle if skew is greater than zero. (Circuit 4) (Circuit 3) DS012086-15 FIGURE 10. Circuit for Measuring Complementary Skew (See Figure 11) DS012086-13 FIGURE 8. Circuit for Measuring Differential Propagation Delays (See Figure 9) Waveforms for Circuit 4 Waveforms for Circuit 3 DS012086-16 FIGURE 11. Waveforms for Circuit 4 (See Figure 10) DS012086-14 Complementary skew is calculated from single-ended propagation delay measurements on complementary output signals, DO and DO*. Note, when V3 and V4 are absolute values, they are identical on DO and DO*; but vary whenever they are relative values. FIGURE 9. Propagation Delay Waveforms for Circuit 3 (See Figure 8) For differential propagation delays, V1 should equal V2. Furthermore, the crossing point of DO and DO* corresponds to zero volts on the differential waveform (see bottom waveform in Figure 9). This is true whether V3 equals V4 or not. www.national.com The complementary skew reveals information about the contour of the rising and falling edge of the differential output 6 Application Information low propagation delay. The minimum channel to channel skew is 0 ns since it is possible for all 12 drivers to have identical propagation delays. Note, this is best and worst case calculations used whenever Skew (channel) is not independently characterized and specified in the datasheet. The device to device skew may be calculated in the same way and the results are the same. Therefore, the device to device skew is 9 ns and 0 ns maximum and minimum respectively. (Continued) signal of the driver. This is important information because the receiver will interpret the differential output signal. If the differential transitions do not continuously ascend or decend through the receivers threshold region, errors may occur. Errors may also occur if the transitions are too slow. In addition, complementary skew provides information about the common mode modulation of the driver. The common mode voltage is represented by (DO–DO*)/2. This information may be used as a means for determining EMI affects. Only “Skew” is specified in this datasheet for the DS89C387. It refers to the complementary skew of the driver. Complementary skew is measured at both V3 and V4 (see Figure 11). More information can be calculated from the propagation delays. The channel to channel and device to device skew may be calculated in addition to the types of skew mentioned previously. These parameters provide timing performance information beneficial when designing. The channel to channel skew is calculated from the variation in propagation delay from receiver to receiver within one package. The device to device skew is calculated from the variation in propagation delay from one DS89C387 to another DS89C387. For the DS89C387, the maximum channel to channel skew is 9 ns (tp max–tp min) where tp is the low to high or high to TABLE 1. DS89C387 Skew Table Parameter Min Typ Max Units Skew (comp.) 0 0.5 3 ns Skew (channel) 0 9 ns Skew (device) 0 9 ns Note Skew (comp.) in Table 1 is the same as “Skew” in the datasheet. Also Skew (channel) and Skew (device) are calculations, but are guaranteed by the propagation delay tests. Both Skew (channel) and Skew (device) would normally be tighter whenever specified from characterization data. The information in this section of the datasheet is to help clarity how skew is defined in this datasheet. This should help when designing the DS89C387 into most applications. DS89C387 Equivalent Input/Output Circuits DS012086-18 FIGURE 13. Driver Input or Driver Enable Equivalent Circuit DS012086-17 FIGURE 12. Driver Output Equivalent Circuit 7 www.national.com Pin Descriptions TABLE 2. Device Pin Names and Descriptions Pin # Pin Name 7, 8, 15, 16, 22, 23, DI TTL/CMOS Compatible Driver Input DO Non-Inverting Driver Output Pin DO* Inverting Driver Output Pin Pin Description 31, 32, 39, 40, 46, 47 2, 6, 9, 13, 17, 21, 26, 30, 33, 37, 41, 45 3, 5, 10, 12, 18, 20, 27, 29, 34, 36, 44, 44 4, 11, 19, 28, 35, 43 EN 38 VCC Positive Power Supply Pin +5 ± 10% 14, 24 GND Device Ground Pin 1, 25, 48 NC www.national.com Active High Dual Driver Enabling Pin Unused Pin (NOT CONNECTED) 8 9 DS89C387 Twelve Channel CMOS Differential Line Driver Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead (0.300" Wide) Molded Shrink Small Outline Package, JEDEC Order Number DS89C387TMEA NS Package Number MS48A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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