COP472-3 Liquid Crystal Display Controller General Description Features The COP472–3 Liquid Crystal Display (LCD) Controller is a peripheral member of the COPSTM family, fabricated using CMOS technology. The COP472-3 drives a multiplexed liquid crystal display directly. Data is loaded serially and is held in internal latches. The COP472-3 contains an on-chip oscillator and generates all the multi-level waveforms for backplanes and segment outputs on a triplex display. One COP472-3 can drive 36 segments multiplexed as 3 x 12 (4(/2 digit display). Two COP472-3 devices can be used together to drive 72 segments (3 x 24) which could be an 8(/2 digit display. Y Y Y Y Y Y Y Y Y Y Direct interface to TRIPLEX LCD Low power dissipation (100 mW typ.) Low cost Compatible with all COPS processors Needs no refresh from processor On-chip oscillator and latches Expandable to longer displays Operates from display voltage MICROWIRETM compatible serial I/O 20-pin Dual-In-Line package and 20-pin SO Block Diagram TL/DD/6932 – 1 COPSTM and MICROWIRETM are trademarks of National Semiconductor Corporation. C1996 National Semiconductor Corporation TL/DD/6932 RRD-B30M56/Printed in U. S. A. http://www.national.com COP472-3 Liquid Crystal Display Controller July 1995 Absolute Maximum Ratings Voltage at CS, DI, SK pins Voltage at all other Pins b 0.3V to a 9.5V Storage Temperature b 0.3V to VDD a 0.3V Operating Temperature Range b 65§ C to a 150§ C Lead Temp. (Soldering, 10 Seconds) 300§ C 0§ C to 70§ C DC Electrical Characteristics GND e 0V, VDD e 3.0V to 5.5V, TA e 0§ C to 70§ C (depends on display characteristics) Parameter Conditions Min Max Units 3.0 5.5 Volts VDD e 5.5V 250 mA VDD e 3V 100 mA 0.7 VDD 0.8 9.5 Volts Volts VDDb0.6 0.6 VDD Volts Volts VDDb0.4 0.4 VDD Volts Volts During BP a Time VDDb DV (/3 VDDb DV VDD (/3 VDD a DV Volts Volts During BPb Time 0 )/3 VDDb DV DV )/3 VDD a DV Volts Volts During BP a Time 0 )/3 VDDb DV DV )/3 VDD a DV Volts Volts During BPb Time VDDb DV (/3 VDDb DV VDD (/3 VDD a DV Volts Volts Power Supply Voltage, VDD Power Supply Current, IDD (Note 1) Input Levels DI, SK, CS VIL VIH BPA (as Osc. in) VIL VIH Output Levels, BPC (as Osc. Out) VOL VOH Backplane Outputs (BPA, BPB, BPC) VBPA, BPB, BPC ON VBPA, BPB, BPC OFF VBPA, BPB, BPC ON VBPA, BPB, BPC OFF Segment Outputs (SA1 E SA4) VSEG ON VSEG OFF VSEG ON VSEG OFF Internal Oscillator Frequency 15 80 kHz Frame Time (Int. Osc. d 192) 2.4 12.8 ms Scan Frequency (1/TSCAN) 39 208 Hz 4 250 kHz SK Clock Frequency SK Width 1.7 ms 1.0 100 ms ns 1.0 1.0 ms ms DI Data Setup, tSETUP Data Hold, tHOLD CS tSETUP tHOLD Output Loading Capacitance 100 Note 1: Power supply current is measured in stand-alone mode with all outputs open and all inputs at VDD. Note 2: DV e 0.05VDD. http://www.national.com 2 pF Absolute Maximum Ratings Storage Temperature If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Voltage at CS, DI, SK Pins Voltage at All Other Pins Operating Temperature Range b 65§ C to a 150§ C Lead Temperature (Soldering, 10 seconds) b 0.3V to a 9.5V 300§ C b 0.3V to VDD a 0.3V b 40§ C to a 85§ C DC Electrical Characteristics GND e 0V, VDD e 3.0V to 5.5V, TA e b40§ C to a 85§ C (depends on display characteristics) Parameter Conditions Power Supply Voltage, VDD Power Supply Current, IDD (Note 1) 3.0 5.5 Volts mA VDD e 3V 120 mA 0.7 VDD 0.8 9.5 Volts Volts VDDb0.6 0.6 VDD Volts Volts VDDb0.4 0.4 VDD Volts Volts During BP a Time VDDb DV (/3 VDDb DV VDD (/3 VDD a DV Volts Volts During BPb Time 0 )/3 VDDb DV DV )/3 VDD a DV Volts Volts During BP a Time 0 )/3 VDDb DV DV )/3 VDD a DV Volts Volts During BPb Time VDDb DV (/3 VDDb DV VDD (/3 VDD a DV Volts Volts Output Levels, BPC (as Osc. Out) VOL VOH Segment Outputs (SA1 E SA4) VSEG ON VSEG OFF VSEG ON VSEG OFF Units 300 BPA (as Osc. In) VIL VIH VBPA, BPB, BPC ON VBPA, BPB, BPC OFF Max VDD e 5.5V Input Levels DI, SK, CS VIL VIH Backplane Outputs (BPA, BPB, BPC) VBPA, BPB, BPC ON VBPA, BPB, BPC OFF Min Internal Oscillator Frequency 15 80 kHz Frame Time (Int. Osc. d 192) 2.4 12.8 ms Scan Frequency (1/TSCAN) 39 208 Hz 4 250 kHz SK Clock Frequency SK Width 1.7 ms 1.0 100 ms ns 1.0 1.0 ms ms DI Data Setup, tSETUP Data Hold, tHOLD CS tSETUP tHOLD Output Loading Capacitance 100 pF Note 1: Power supply current is measured in stand-alone mode with all outputs open and all inputs at VDD. Note 2: DV e 0.05 VDD. 3 http://www.national.com Dual-In-Line Package Top View Pin CS VDD GND DI SK BPA BPB BPC SA1 E SC4 Description Chip select Power supply (display voltage) Ground Serial data input Serial clock input Display backplane A (or oscillator in) Display backplane B Display backplane C (or oscillator out) 12 multiplexed outputs TL/DD/6932–2 Order Number COP472MW-3 or COP472N-3 See NS Package Number M20A or N20A FIGURE 2. Connection Diagram TL/DD/6932 – 3 FIGURE 3. Serial Load Timing Diagram TL/DD/6932 – 4 FIGURE 4. Backplane and Segment Waveforms TL/DD/6932 – 5 FIGURE 5. Typical Display Internal Connections Epson LD-370 http://www.national.com 4 Functional Description The COP472-3 drives 36 bits of display information organized as twelve segments and three backplanes. The COP472-3 requires 40 information bits: 36 data and 4 control. The function of each control bit is described below. Display information format is a function of the LCD interconnections. A typical segment/backplane configuration is illustrated in Figure 5 , with this configuration the COP472-3 will drive 4 digits of 9 segments. To adapt the COP472-3 to any LCD display configuration, the segment/backplane multiplex scheme is illustrated in Table I. Two or more COP472-3 chips can be cascaded to drive additional segments. There is no limit to the number of COP472-3’s that can be used as long as the output loading capacitance does not exceed specification. SEGMENT DATA BITS Data is loaded in serially, in sets of eight bits. Each set of segment data is in the following format: SA Segment, Backplane 1 2 3 4 5 6 7 8 SA1, BPC SB1, BPB SC1, BPA SC1, BPB SB1, BPC SA1, BPB SA1, BPA SB1, BPA SH SG SF SE SD SC SB SA 9 10 11 12 13 14 15 16 SA2, BPC SB2, BPB SC2, BPA SC2, BPB SB2, BPC SA2, BPB SA2, BPA SB2, BPA SH SG SF SE SD SC SB SA Digit 2 17 18 19 20 21 22 23 24 SA3, BPC SB3, BPB SC3, BPA SC3, BPB SB3, BPC SA3, BPB SA3, BPA SB3, BPA SH SG SF SE SD SC SB SA Digit 3 25 26 27 28 29 30 31 32 SA4, BPC SB4, BPB SC4, BPA SC4, BPB SB4, BPC SA4, BPB SA4, BPA SB4, BPA SH SG SF SE SD SC SB SA Digit 4 33 34 35 36 37 38 39 40 SC1, BPC SC2, BPC SC3, BPC SC4, BPC not used Q6 Q7 SYNC SPA SP2 SP3 SP4 Digit 1 Digit 2 Digit 3 Digit 4 SC SD SE SF SG SH CONTROL BITS The fifth set of 8 data bits contains special segment data and control data in the following format: SYNC TABLE I. COP472-3 Segment/Backplane Multiplex Scheme Bit Number SB Data is shifted into an eight bit shift register. The first bit of the data is for segment H, digit 1. The eighth bit is segment A, digit 1. A set of eight bits is shifted in and then loaded into the digit one latches. The second set of 8 bits is loaded into digit two latches. The third set into digit three latches, and the fourth set is loaded into digit four latches. Q7 Q6 X SP4 SP3 SP2 SP1 The first four bits shifted in contain the special character segment data. The fifth bit is not used. The sixth and seventh bits program the COP472-3 as a stand alone LCD driver or as a master or slave for cascading COP472-3’s. BPC of the master is connected to BPA of each slave. The following table summarizes the function of bits six and seven: Data to Numeric Display Digit 1 Q7 Q6 1 1 Slave Function 0 1 Stand Alone 1 0 Not Used 0 0 Master BPC Output BPA Output Backplane Output Backplane Output Internal Osc. Output Internal Osc. Output Oscillator Input Backplane Output Oscillator Input Backplane Output The eighth bit is used to synchronize two COP472-3’s to drive an 8(/2-digit display. 5 http://www.national.com LOADING SEQUENCE TO DRIVE A 4(/2-DIGIT DISPLAY Steps: 1. Turn CE low. 2. Clock in 8 bits of data for digit 1. 3. 4. 5. 6. Clock in 8 bits of data for digit 2. Clock in 8 bits of data for digit 3. Clock in 8 bits of data for digit 4. Clock in 8 bits of data for special segment and control function of BPC and BPA. 0 0 1 1 SP4 SP3 SP2 SP1 7. Turn CS high. Note: CS may be turned high after any step. For example to load only 2 digits of data, do steps 1, 2, 3, and 7. CS must make a high to low transition before loading data in order to reset internal counters. LOADING SEQUENCE TO DRIVE AN 8(/2-DIGIT DISPLAY Two or more COP472-3’s may be connected together to drive additional segments. An eight digit multiplexed display is shown in Figure 7 . The following is the loading sequence to drive an eight digit display using two COP472-3’s. The right chip is the master and the left the slave. Steps: 1. Turn CS low on both COP472-3’s. TL/DD/6932 – 6 FIGURE 6. System Diagram – 4(/2 Digit Display 2. Shift in 32 bits of data for the slave’s four digits. 3. Shift in 4 bits of special segment data: a zero and three ones. 1 1 1 0 SP4 SP3 SP2 SP1 This synchronizes both the chips and BPA is oscillator input. Both chips are now stopped. Turn CS high to both chips. Turn CS low to master COP472-3. Shift in 32 bits of data for the master’s 4 digits. Shift in four bits of special segment data, a one and three zeros. 4. 5. 6. 7. 0 0 0 1 SP4 SP3 SP2 SP1 This sets the master COP472-3 to BPA as a normal backplane output and BPC as oscillator output. Now both the chips start and run off the same oscillator. 8. Turn CS high. The chips are now synchronized and driving 8 digits of display. To load new data simply load each chip separately in the normal manner, keeping the correct status bits to each COP472-3 (0110 or 0001). http://www.national.com TL/DD/6932 – 7 FIGURE 7. System Diagram – 8(/2 Digit Display 6 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Molded DIP (M) Order Number COP472MW-3 NS Package Number M20B 7 http://www.national.com COP472-3 Liquid Crystal Display Controller Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Molded DIP (N) Order Number COP472N-3 NS Package Number N20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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