MM145453 Liquid Crystal Display Driver General Description Features The MM145453 is a monolithic integrated circuit utilizing CMOS metal gate, low threshold enhancement mode devices. The chip can drive up to 33 LCD segments and can be paralleled to increase this number. The chip is capable of driving a 41⁄2 digit 7-segment display with minimal interface between the display and the data source. n n n n n n n The MM145453 stores display data in latches after it is clocked in, and holds the data until new display data is received. The MM145453 is available in a molded 44 pin surface mount PLCC package. The MM145453 is pin out and functionally compatible with the MC145453. Serial Data Input Wide Power Supply operation TTL Compatibility Up to 33 LCD Segments Alphanumeric or Bar Graph capability Cascaded operation capability Pin Compatible with MC145453 Applications n n n n n COPS™ or microprocessor displays Industrial control indicator Digital clock, thermometer, counter, voltmeter Instrumentation displays Remote displays Connection Diagram DS101283-1 Top View Order Number MM145453V See NS Package Number V44A © 1999 National Semiconductor Corporation DS101283 www.national.com MM145453 Liquid Crystal Display Driver December 1999 MM145453 Absolute Maximum Ratings (Note 1) Junction Temperature If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Lead Temperature (Soldering, 10s) Voltage at Any Pin, Referenced to Gnd -65˚C to +150˚C Power Dissipation at 25˚C 350mW Power Dissipation at 70˚C 300mW 300˚C Recommended Operating Conditions -0.3V to +10V Storage Temperature +150˚C VDD 3V to 10V Operating Temperature 0˚C to 70˚C Electrical Characteristics The following specifications apply for TA within operation range, VDD = 3.0V to 10V, VSS = 0V, unless otherwise specified. Parameter Conditions Min Average Supply Current, IDD Input Logical ’0’ Voltage, VIL Input Logical ’1’ Voltage, VIH Typical 3 Supply Voltage, VDD Max Units 10 V All Outputs Open, Clock=Gnd, Data=Gnd,OSC=Gnd, BP_IN 32Hz VDD= 5V 10 µA VDD= 10V 40 µA VDD= 3V 0.4 V VDD= 5V 0.8 V VDD= 10V 0.8 V VDD= 3V 2.0 V VDD= 5V 2.0 V VDD= 10V 8.0 Segment Sink Current, IOL VDD= 3V, VOUT= 0.3V -20 -40 µA Segment Source Current, IOH VDD= 3V, VOUT= 2.7V 20 40 µA Backplane Out Sink Current, IOL VDD= 3V, VOUT= 0.3V -320 -500 µA Backplane Out Source Current, IOH VDD= 3V, VOUT= 2.7V 320 500 µA Segment Output Offset Voltage Segment Load = 250pF (Note 2) Backplane Output Offset Voltage Backplane Load = 8750pF (Note 2) Backplane Out Frequency ROSC_IN= 50kΩ, COSC_IN= 0.01µF Clock Input Frequency, fCLOCK V +/-50 mV +/-50 mV VDD= 3V (Notes 2, 3) 500 kHz VDD= 5V (Note 2) 750 kHz VDD= 10V (Note 2) 1.0 MHz 75 Hz 60 % Clock Input Duty Cycle 40 Data Input Set-Up Time, tDS 300 ns Data Input Hold Time, tDH 300 ns Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: This parameter is guaranteed (but not production tested) over the operating temperature range and the operating supply voltage range. Not to be used in Q.A. testing. Note 3: AC input waveform for test purposes: tr≤ 20ns, tf≤ 20ns, fCLOCK = 500kHz, Duty Cycle = 50% ± 10% Note 4: Clock input rise time (tr) and fall time (tf) must not exceed 300ns www.national.com 2 MM145453 Electrical Characteristics (Continued) DS101283-2 FIGURE 1. Block Diagram DS101283-3 FIGURE 2. of the first shift register, thus allowing continuous operation. The data during the 35th and 36th clock cycles is ″don’t care″, but setting data to logical ’0’ for these two clock cycles is the preferred format. The data input bits map directly to the segment output pins and the display. The MM145453 does not have any format restrictions, as all outputs are controllable. The MM145453 has an internal oscillator which can generate the required clock signal to drive the LCD back plane. The frequency of the internal oscillator is set by a pull-up resistor (ROSC_IN) connected from the OSC_IN pin to VDD, and a capacitor (COSC_IN) connected from the OSC_IN pin to Ground. Due to the current sink limitations of the OSC_IN circuitry, the lowest recommended resistor value for setting the oscillator frequency is 9kΩ. It will typically take 2 to 4 RC time constants to charge the OSC_IN pin from near 0V to within 1V of VDD which is the high threshold voltage point for the OSC_IN circuitry. An approximate calculation of fOSC is: fOSC = 1 / (lη(VDD/1V) X ROSC_IN X COSC_IN) A ROSC_IN resistor value of 50kΩ with a COSC_IN capacitor value of 0.01µF and a VDD value of 5.00V would produce a typical oscillator frequency ( fOSC) of about 1200Hz. The fOSC signal is divided by 16 before it is presented at the BP_OUT pin. For this example the approximate BP_OUT frequency will be fOSC/16, or about 75Hz. Applications Information The MM145453 is specifically designed to operate 41⁄2 digit 7-segment displays with minimal interface with the display and data source. Serial data transfer from the data source to the display driver is accomplished with 2 signals, serial Data and Clock. Using a format of a leading ″1″ followed by the 33 data bits and 2 trailing don’t care bits, allows data transfer without the need of an additional Data Load signal. Since the MM145453 does not contain a character generator, the formatting of the segment information must be done prior to inputting the data to the MM145453. The transfer of the 33 data bits is complete at the falling edge of the 36th clock cycle, thus providing non-multiplexed, direct drive to the display. Outputs change only if the serial data bits differ from the previous time. Figure 3 shows the data input format. A single start bit of logical ’1’ precedes the 33 bits of segment data for a total of 34 bits that need to be defined and clocked in. After the 34 bits are clocked in, 2 additional clock cycles are required. At the 36th clock cycle an internal LOAD signal is generated synchronously with the rising edge of the Clock In signal, which loads the 33 bits of segment data in the shift register into the latches. At the falling edge of the 36th clock cycle an internal RESET signal is generated which clears all the shift registers for the next set of data. The shift registers are static masterslave configuration. There is no clear for the master portion 3 www.national.com MM145453 Applications Information from the display. When using an external clock for the back plane drive the internal oscillator should be disabled by connecting the OSC_IN pin directly to ground. This will prevent possible internal oscillations, and reduce device dissipation. The MM145453 is a pin out variation of the MM5453. For additional applications information please refer to the MM5453 data sheet. (Continued) The BP_IN pin of the MM145453 can be used with an externally supplied signal, provided it has a duty cycle of 50%. Any deviation from a precise 50% duty cycle will result in an offset voltage on the LCD. The use of an external clock allows synchronizing the display drive with AC power, other internal clocks, or DVM integration time to reduce interference Input Data Format DS101283-4 www.national.com 4 MM145453 Liquid Crystal Display Driver Physical Dimensions inches (millimeters) unless otherwise noted Top View Order Number MM145453V See NS Package Number V44A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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