MF8 4th-Order Switched Capacitor Bandpass Filter General Description Features The MF8 consists of two second-order bandpass filter stages and an inverting operational amplifier. The two filter stages are identical and may be used as two tracking second-order bandpass filters, or cascaded to form a single fourth-order bandpass filter. The center frequency is controlled by an external clock for optimal accuracy, and may be set anywhere between 0.1 Hz and 20 kHz. The ratio of clock frequency to center frequency is programmable to 100:1 or 50:1. Two inputs are available for TTL or CMOS clock signals. The TTL input will accept logic levels referenced to either the negative power supply pin or the ground pin, allowing operation on single or split power supplies. The CMOS input is a Schmitt inverter which can be made to selfoscillate using an external resistor and capacitor. By using the uncommitted amplifier and resistors for negative feedback, any all-pole (Butterworth, Chebyshev, etc.) filter can be formed. This requires only three resistors for a fourth-order bandpass filter. Q of the second-order stages may be programmed to any of 31 different values by the five ‘‘Q logic’’ pins. The available Q values span a range from 0.5 through 90. Overall filter bandwidth is programmed by connecting the appropriate Q logic pins to either V a or Vb. Filters with order higher than four can be built by cascading MF8s. Y Y Y Y Y Y Y Y Center frequency set by external clock Q set by five-bit digital word Uncommitted inverting op amp 4th-order all-pole filters using only three external resistors Cascadable for higher-order filters Bandwidth, response characteristic, and center frequency independently programmable Separate TTL and CMOS clock inputs 18 pin 0.3× wide package Key Specifications Y Y Y Y Center frequency range 0.1 Hz to 20 kHz Q range 0.5 to 90 Supply voltage range 9V to 14V ( g 4.5V to g 7V) Center frequency accuracy 1% over full temperature range Typical Application & Connection Diagrams Dual-In-Line Package TL/H/8694 – 2 Top View Order Number MF8CCJ or MF8CCN See NS Package Number J18A or N18A TL/H/8694 – 1 Fourth-Order Butterworth Bandpass Filter C1995 National Semiconductor Corporation TL/H/8694 RRD-B30M115/Printed in U. S. A. MF8 4th-Order Switched Capacitor Bandpass Filter January 1995 Absolute Maximum Ratings (Note 1) See AN-450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ for other methods of soldering surface mount devices. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VS e V a b Vb) b 0.3V to a 15V Operating Ratings (Note 1) Voltage at any Input (Note 2) Vb b0.3V to V a a 0.3V g 1 mA Input Current at any Input Pin (Note 2) g 1 mA Output Short-Circuit Current (Note 7) Power Dissipation (Note 3) 500 mW b 65§ C to a 150§ C Storage Temperature Soldering Information: J Package: 10 sec. 260§ C N Package: 10 sec. 300§ C SO Package: Vapor Phase (60 sec.) 215§ C Infrared (15 sec.) 220§ C Temperature Range MF8CCN MF8CCJ Supply Voltage (VS e V a b Vb) fCLK c Q Range for 10 Hz s fCLK s 250 kHz for 250 kHz s fCLK s 1 MHz TMIN s TA s TMAX 0 § C s TA s a 70§ C b 40§ C s TA s a 85§ C a 9V to a 14V any Q fCLK c Q s 5 MHz ESD rating is to be determined. Filter Electrical Characteristics The following specifications apply for V a e a 5V, Vb e b5V, CLOAD e 50 pF and RLOAD e 50 kX on filter output unless otherwise specified. Boldface limits apply for TMIN to TMAX; all other limits TA e TJ e 25§ C. MF8CCN Parameter (Notes 4, 5) Symbol Ho Gain at fo Q Q R fCLK/fo Ho Gain at fo Q Q R fCLK/fo Ho Gain at fo Q Q R fCLK/fo Ho Gain at fo Conditions fCLK e 250 kHz 100:1 ABCDE e 11100 fCLK e 250 kHz 100:1 ABCDE e 10011 fCLK e 250 kHz 50:1 ABCDE e 00001 VS e g 5V g 5% fCLK s 250 kHz DQ/QTH Q Deviation from VS e g 5V g 5% Theoretical fCLK s 250 kHz, Q l 1 (See Table I) fCLK s 100 kHz, 1 k Q k 57 DR/RTH fCLK/fo Deviation VS e g 5V g 5% from Theoretical fCLK s 250 kHz (See Table I) Q Q fCLK e 250 kHz, 50:1 ABCDE e 00110 Dynamic Range ABCDE e 11100 (Note 6) ABCDE e 10011 ABCDE e 00001 Clock Feedthrough Filter and Op Amp fCLK s 250 kHz Qs1 Ql1 IS Maximum Supply fCLK e 250 kHz, no Current loads on outputs VOS Maximum Filter Output Offset Voltage fCLK e 250 kHz, Q e 4 50:1 100:1 Minimum Filter Output Swing RLOAD e 5 kX (Note 6) VOUT Typical (Note 9) 6.02 g .05 MF8CCJ Tested Design Limit Limit (Note 10) (Note 11) 6.02 g 0.2 3.92 g 2% 3.92 g 10% 99.2 g 0.3% 99.2 g 1% 6.02 g 0.2 Typical (Note 9) Tested Limit (Note 10) 6.02 g 0.05 6.02 g 0.2 3.92 g 2% 3.92 g 10% Design Units Limit (Note 11) dB 99.2 g 0.3% 99.2 g 1% 6.02 g 0.5 15.5 g 3% 15.5 g 12% 99.7 g 0.3% 99.7 g 1% 6.02 g 0.2 6.02 g 0.5 15.5 g 3% 15.5 g 12% 99.7 g 0.3% 99.7 g 1% 5.85 g 0.4 5.85 g 1 5.85 g 0.4 5.85 g 1 55 g 5% 55 g 14% 55 g 5% 55 g 14% 49.9 g 0.2% 49.9 g 1% dB dB 49.9 g 0.2% 49.9 g 1% 6.02 g 0.5 6.02 g 1.5 6.02 g 0.5 g 5% g 15% g 5% g 15% g 2% g 6% g 2% g 6% g 0.3% g 1% g 0.3% g 1% 10.6 10.6 g 2% g 10% 6.02 g 1.5 dB 10.6 g 2% 10.6 g 10% 86 80 75 86 80 75 dB dB dB 80 40 80 40 mV mV 9 12 g 40 g 80 g 120 g 240 g 4.1 g 3.8 2 12 g 3.8 9 13 mA g 40 g 80 g 120 g 240 mV mV g 4.1 g 3.6 V Op Amp Electrical Characteristics The following specifications apply for V a e a 5V, Vb e b5V and no load on the Op Amp output unless otherwise specified. Boldface limits apply for TMIN to TMAX; all other limits TA e TJ e 25§ C. MF8CCN Symbol Parameter Conditions MF8CCJ Typical Tested Design Typical Tested Design Units Limit Limit Limit Limit (Note 9) (Note 10) (Note 11) (Note 9) (Note 10) (Note 11) VOS Maximum Input Offset Voltage g8 IB Maximum Input Bias Current 10 g 20 g8 10 g 20 mV pA VOUT Minimum Output Voltage Swing RLOAD e 5 kX g 3.5 g 3.5 V AVOL Open Loop Gain 80 80 dB GBW Gain Bandwidth Product 1.8 1.8 MHz SR Slew Rate 10 10 V/ms Logic Input and Output Characteristics The following specifications apply for V a e a 10V and Vb e 0V unless otherwise specified. Boldface limits apply for TMIN to TMAX; all other limits TA e TJ e 25§ C. MF8CCN Symbol VT a Parameter Positive Threshold Negative Threshold Voltage on pin 8 VOH VOL IOH IOL VIH VIL Min VS e V a b Vb referred b e 0V (Note 8) Max to V Output Voltage on Min High pin 9 (Note 12) Max Low 0.7VS 0.58VS 0.7VS 0.89VS V 0.11VS 0.35VS 0.11VS V 0.35VS 0.47VS 0.35VS 0.47VS V 9.0 V IO e b10 mA IO e a 10 mA 9.0 9.0 1.0 1.0 5.0 2.5 Input Voltage on Min High pins: 1, 2, 3, 10, Max Low 17, & 18 (Note 12) 7.0 9.0 3.0 1.0 Input Voltage on pin 7 Min High Max Low 10 V a e a 10V, Vb e 0V or V a e a 5V, Vb e b5V V 0.89VS 3.0 VIH 0.58VS 0.7VS 6.0 Input Current on pins: 1, 2, 3, 7, 8, 10, 17, & 18 0.7VS 0.35VS Output Current on Min Source Pin 9 tied to Vb pin 9 Min Sink Pin 9 tied to V a IIN VIL Conditions Min VS e V a b Vb referred b e 0V (Note 8) Max to V Voltage on pin 8 VTb MF8CCJ Typical Tested Design Typical Tested Design Units Limit Limit Limit Limit (Note 9) (Note 10 (Note 11) (Note 9) (Note 10) (Note 11) 1.0 V 3.0 mA 5.0 2.5 mA 7.0 9.0 V 3.0 1.0 V 10 mA 6.0 10 2.0 2.0 2.0 V 0.8 0.8 0.8 V Note 1: Absolute Maximum Raings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2: When the applied voltage at any pin falls outside the power supply voltages (VIN k Vb or VIN l V a ), the absolute value of current at that pin should be limited to 1 mA or less. Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, HJA, and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD e (TJMAX b TA)/HJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, TJMAX e 125§ C, and the typical junction-to-ambient thermal resistance of the MF8CCN when board mounted is 50§ C/W. For the MF8CCJ, this number increases to 65§ C/W. Note 4: The center frequency of each 2nd-order filter section is defined as the frequency where the phase shift through the filter is zero. Note 5: Q is defined as the measured center frequency divided by the measured bandwidth, where the bandwidth is the difference between the two frequencies where the gain is 3 dB less than the gain measured at the center frequency. Note 6: Dynamic range is defined as the ratio of the tested minimum output swing of 2.69 Vrms ( g 3.8V peak-to-peak) to the wideband noise over a 20 kHz bandwidth. For Qs of 1 or less the dynamic range and output swing will degrade because the gain at an internal node is 2/Q. Keeping the input signal level below 1.23xQ Vrms will avoid distortion in this case. 3 Note 7: If it is possible for a signal output (pin 6, 14, or 15) to be shorted to V a , Vb or ground, add a series resistor to limit output current. Note 8: If Vb is anything other than 0V then the value of Vb should be added to the values given in the table. For example for V a e a 5V and Vb e b 5V the typical VT a e 0.7 (10V) a ( b 5V) e a 2V. Note 9: Typicals are at 25§ C and represent the most likely parametric norm. Note 10: Tested Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 11: Design Limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels. Note 12: These logic levels have been referenced to Vb. The logic levels will shift accordingly for split supplies. Pin Descriptions Q Logic Inputs A, B, C, D, E (3, 2, 1, 18, 17): AGND (4): V a (12), Vb (11): F1 IN (16), F2 IN (5): F1 OUT (15), F2 OUT (6): A IN (13): A OUT (14): 50/100 (10): TTL CLK (7): CMOS CLK (8): This pin allows the MF8 to generate its own clock signal. To do this, connect an external resistor between the RC pin and the CMOS Clock input, and an external capacitor from the CMOS Clock input to AGND. The TTL Clock input should be connected to Vb or V a . When the MF8 is driven from an external clock, the RC pin should be left open. These inputs program the Qs of the two 2nd-order bandpass filter stages. Logic ‘‘1’’ is V a and logic ‘‘0’’ is V b. This is the analog and digital ground pin and should be connected to the system ground for split supply operation or biased to mid-supply for single supply operation. For best filter performance, the ground line should be ‘‘clean’’. RC (9): These are the positive and negative power supply inputs. Decoupling the power supply pins with 0.1 mF or larger capacitors is highly recommended. These are the inputs to the bandpass filter stages. To minimize gain error the source impedance should be less than 2 kX. Input signals should be referenced to AGND. These are the outputs of the bandpass filter stages. This is the inverting input to the uncommitted operational amplifier. The non-inverting input is internally connected to AGND. This is the output of the uncommitted operational amplifier. This pin sets the ratio of the clock frequency to the bandpass center frequency. Connecting this pin to V a sets the ratio to 100:1. Connecting it to Vb sets the ratio to 50:1. This is the TTL-level clock input pin. There are two logic threshold levels, so the MF8 can be operated on either single-ended or split supplies with the logic input referred to either Vb or AGND. When this pin is not used (or when CMOS logic levels are used), it should be connected to either V a or Vb. This pin is the input to a CMOS Schmitt inverter. Clock signals with CMOS logic levels may be applied to this input. If the TTL input is used this pin should be connected to Vb. 1.0 Application Information 1.1 INTRODUCTION A simplified block diagram for the MF8 is shown in Figure 1 . The analog signal path components are two identical 2ndorder bandpass filters and an operational amplifier. Each filter has a fixed voltage gain of 2. The filters’ cutoff frequency is proportional to the clock frequency, which may be applied to the chip from an external source or generated internally with the aid of an external resistor and capacitor. The proportionality constant fCLK/f0 can be set to either 50 or 100 depending on the logic level on pin 10. The ‘‘Q’’ of the two filters can have any of 31 values ranging from 0.5 to 90 and is set by the logic levels on pins 1, 2, 3, 17, and 18. Table I shows the available values of Q and the logic levels required to obtain them. The operational amplifier’s non-inverting input is internally grounded, so it may be used only for inverting applications. The components in the analog signal path can be interconnected in several ways, three of which are illustrated in Figures 2a, 2b and 2c. The two second-order filter sections can be used as separate filters whose center frequencies track very closely as in Figure 2a . Each filter section has a high input impedance and low output impedance. The op amp may be used for gain scaling or other inverting functions. If sharper cutoff slopes are desired, the two filter sections may be cascaded as in Figure 2b . Again, the op amp is uncommitted. The circuit in Figure 2c uses both filter sections with the op amp and three resistors to build a ‘‘multiple feedback loop’’ filter. This configuration offers the greatest flexibility for fourth-order bandpass designs. Virtually any fourth-order all pole response shape (Butterworth, Chebyshev) can be obtained with a wide range of bandwidths, simply by proper choice of resistor values and Q. The three connection schemes in Figure 2 will be discussed in more detail in Sections 1.4 and 1.5. 4 Typical Performance Characteristics fCLK/fo Ratio vs Clock FrequencyÐ50:1 Mode fCLK/fo Ratio vs Clock FrequencyÐ100:1 Mode fCLK/fo Ratio vs Supply VoltageÐ50:1 and 100:1 Mode fCLK/fo Ratio vs TemperatureÐ100:1 Mode fCLK/fo Ratio vs TemperatureÐ50:1 Mode Q vs TemperatureÐ 50:1 and 100:1 Q vs Supply VoltageÐ 50:1 and 100:1 Q vs Clock FrequencyÐ 50:1 and 100:1 Q vs Clock FrequencyÐ 50:1 and 100:1 Op AmpÐOpen Loop Frequency Response Positive Power Supply Rejection Negative Power Supply Rejection TL/H/8694 – 24 5 Typical Performance Characteristics (Continued) Positive Swing vs Load Resistance Negative Swing vs Load Resistance Negative Swing vs Supply Voltage Positive Swing vs Supply Voltage Negative Swing vs Temperature (Filter and Op Amp) Positive Swing vs Temperature (Filter and Op Amp) Supply Current vs Temperature Supply Current vs Supply Voltage Filter Offset Voltage vs Supply Voltage Filter Offset Voltage vs QÐ50:1 and 100:1 Filter Offset Voltage vs Clock FrequencyÐ50:1 and 100:1 Filter Offset Voltage vs TemperatureÐ50:1 and 100:1 TL/H/8694 – 25 6 1.0 Application Information (Continued) TL/H/8694 – 3 FIGURE 1. Simplified Block Diagram of the MF8 TL/H/8694 – 4 FIGURE 2a. Separate Second-Order ‘‘Tracking’’ Filters TL/H/8694 – 5 FIGURE 2b. Fourth-Order Bandpass Made by Cascading Two Second-Order Stages 7 1.0 Application Information (Continued) TL/H/8694 – 6 FIGURE 2c. Multiple Feedback Loop Connection Clock signals derived from a crystal-controlled oscillator are recommended when maximum center frequency accuracy is desired, but in less critical applications the MF8 can generate its own clock signal as in Figures 3c and 4c . An external resistor and capacitor determine the oscillation frequency. Tolerance of these components and part-to-part variations in Schmitt-trigger logic thresholds limit the accuracy of the RC clock frequency. In the self-clocked mode the TTL Clock input should be connected to either pin 11 or pin 12. 1.2 CLOCKS The MF8 has two clock input pins, one for CMOS logic levels and the other for TTL levels. The TTL (pin 7) input automatically adjusts its switching threshold to enable operation on either single or split power supplies. When this input is used, the CMOS logic input should be connected to pin 11(Vb). The CMOS Schmitt trigger input at pin 8 accepts CMOS logic levels. When it is used, the TTL input should be connected to either pin 11 (Vb) or pin 12 (V a ). The basic clock hookups for single and split supply operation are shown in Figures 3 and 4 . TL/H/8694–7 TL/H/8694 – 8 (a) MF8 Driven with CMOS Logic Level Clock (b) MF8 Driven with TTL Logic Level Clock fCLK e RC ln 1 VS b VTb À #V S b VT a Typically for VS* e 10V 1 fCLK e 1.69 RC *VS e V a b Vb TL/H/8694 – 9 (c) MF8 Driven with Schmitt Trigger Oscillator FIGURE 3. Dual Supply Operation 8 J #V J À VT a Tb 1.0 Application Information (Continued) pled to the filter input or biased to V a /2. It is strongly recommended that each power supply pin be bypassed to ground with at least a 0.1 mF ceramic capacitor. In single supply applications, with V b connected to ground, V a and AGND should be bypassed to system ground. 1.3 POWER SUPPLIES AND ANALOG GROUND The MF8 can be operated from single or dual-polarity power supplies. For dual-supply operation, the analog ground (pin 4) should be connected to system ground. When single supplies are used, pin 4 should be biased to V a /2 as in Figures 3 and 4 . The input signal should either be capacitively cou- TL/H/8694 – 10 (a) MF8 Driven with CMOS Logic Level Clock TL/H/8694 – 11 (b) MF8 Driven with TTL Logic Clock fCLK e RCIN 1 VS b VTb À #V S b VT a Typically for VS e 10V fCLK e 1 1.69 RC TL/H/8694 – 12 (c) MF8 Driven with the Schmitt Trigger Oscillator FIGURE 4. Single supply operation. The AGND pin must be biased to mid-supply. The input signal should be dc biased to mid-supply or capacitor-coupled to the input pin. 9 VT a J #V J À Tb 1.0 Application Information (Continued) 1.4 MULTIPLE FEEDBACK LOOP CONFIGURATION The multi-loop approach to building bandpass filters is highly flexible and stable, yet uses few external components. Figure 5 shows the MF8’s internal operational amplifier and two second-order filter stages with three external resistors in a fourth-order multiple feedback configuration. Higher-order filters may be built by adding more second-order sections and feedback resistors as in Figure 6 . The filter’s response is determined by the clock frequency, the clock-tocenter-frequency ratio, the ratios of the feedback resistor values, and the Qs of the second-order filter sections. The design procedure for multiple feedback filters can be broken down into a few simple steps: 1) Determine the characteristics of the desired filter. This will depend on the requirements of the particular application. For a given application, the required bandpass response can be shown graphically as in Figure 7 , which shows the limits for the filter response. Figure 7 also makes use of several parameters that must be known in order to design a filter. These parameters are defined below in terms of Figure 7 . TL/H/8694 – 15 FIGURE 7. Graphical representation of the amplitude response specifications for a bandpass filter. The filter’s response should fall within the shaded area. TL/H/8694 – 13 FIGURE 5. General fourth-order multiple-feedback bandpass filter circuit. MF8 pin numbers are shown. TL/H/8694 – 14 FIGURE 6. By adding more second-order filter stages and feedback resistors, higher order multiple-feedback filters may be built. 10 1.0 Application Information (Continued) fC1 and fC2: The filter’s lower and upper cutoff frequencies. These define the filter’s passband. fS1 and fS2: The boundaries of the filter’s stopband. Table I shows the available Q values; the nearest value is 8.5, which is programmed by tying pins 1, 2, 3, and 18 to V a and pin 17 to V b. Note that the resistor values obtained from the tables are normalized for center frequency gain HOBP e 1. For different gains, simply divide R0 by the desired gain. BW: The filter’s bandwidth. BW e fC2 b fC1. SBW: The width of the filter’s stopband. SBW e fS2 b fS1. f0: The center frequency of the filter. f0 is equal to the geometric mean of fC1 and fC2: f0 e 0fC1fC2. f0 is also equal to the geometric mean of fS1 and fS2. H0BP: The nominal passband gain of the bandpass filter. This is normally taken to be the gain at f0. f0/BW: The ratio of the center frequency to the bandwidth. For second-order filters, this quantity is also known as ‘‘Q’’. SBW/BW: The ratio of stopband width to bandwidth. This quantity is also called ‘‘Omega’’ and may be represented by the symbol ‘‘X’’. Amax: The maximum allowable gain variation within the filter passband. This will depend on the system requirements, but typically ranges from a fraction of a dB to 3 dB. Amin: The minimum allowable attenuation in the stopband. Again, the required value will depend on system constraints. 2). Choose a Butterworth or Chebyshev response characteristic. Butterworth bandpass filters are monotonic on either side of the center frequency, while Chebyshev filters will have ‘‘ripple’’ in the passband, but generally faster attenuation outside the passband. Chebyshev filters are specified according to the amount of ripple (in dB) within the passband. 3) Determine the filter order necessary to meet the response requirements defined above. This may be done with the aid of the nomographs in Figures 8 and 9 for Butterworth and Chebyshev filters. To use the nomographs, draw a line through the desired values on the AMAX/AMIN scales to the left side of the graph. Draw a horizontal line to the right of this point and mark its intersection with the vertical line corresponding to the required ratio SBW/BW. The required filter order will be equal to the number of the curve falling on or just above the intersection of the two lines. This is illustrated in Figure 10 for a Chebyshev filter with 1 dB ripple, 30 dB minimum attenuation in the stopband, and SBW/BW e 3. From the Figure, the required filter order is 6. 4) The design tables in section 2.0 can now be used to find the component values that will yield the desired response for filters of order 4 through 12. The ‘‘Kn’’ give the ratios of resistors ‘‘Rn’’ to RF, and KQ is Q divided by f0/BW. As an example of the Tables’ use, consider a fourth-order Chebyshev filter with 0.5 dB ripple and f0/BW e 6. Begin by choosing a convenient value for RF, such as 100 kX. From the ‘‘0.5 dB Chebyshev’’ filter table, K0 e R0/RF e 1.3405. This gives R0 e RF c 1.345 e 134.05k. In a similar manner, R2 is found to equal 201.61k. Q is found using the column labeled KQ. This gives Q e KQ c f0/BW e 8.4174. 5) Choose the clock-to-center-frequency ratio. This will nominally be 100:1 when pin 10 is connected to pin 12(V a ) and 50:1 when pin 10 is connected to pin 11(Vb). 100:1 generally gives a response curve nearer the ideal and fewer (if any) problems with aliasing, while 50:1 allows operation over the highest octave of center frequencies (10 kHz to 20 kHz). Supply the MF8 with a clock signal of the appropriate frequency to either the TTL or CMOS input, depending on the available clock logic levels. TABLE I. Q and Clock-to-Center-Frequency Ratio Versus Logic Levels on ‘‘Q-set’’ Pins 50:1 mode 11 100:1 mode ABCDE FCLK/Fo Q FCLK/Fo Q 10000 11000 01000 10100 00100 01100 11100 01010 10010 10110 00010 11110 00110 11001 11010 11101 01001 10011 10101 01110 10001 10111 11011 11111 00101 01011 00111 00001 01101 00011 01111 43.7 45.8 46.8 48.4 48.7 48.9 49.2 49.3 49.4 49.4 49.5 49.6 49.6 49.6 49.7 49.7 49.7 49.7 49.7 49.7 49.8 49.8 49.8 49.8 49.8 49.8 49.8 49.9 49.9 49.9 49.9 0.45 0.71 0.96 2.0 2.5 3.0 4.0 5.0 5.7 6.4 7.6 8.5 10.6 11.7 12.5 13.6 14.7 15.8 16.5 17 19 22 27 30 33 40 44 57 68 79 90 94.0 95.8 96.8 98.4 98.7 98.9 99.2 99.3 99.4 99.4 99.5 99.6 99.6 99.6 99.7 99.7 99.7 99.7 99.7 99.7 99.8 99.8 99.8 99.8 99.8 99.8 99.8 99.9 99.9 99.9 99.9 0.47 0.73 0.98 2.0 2.5 3.0 4.0 5.0 5.7 6.4 7.6 8.5 10.6 11.7 12.5 13.6 14.7 15.8 16.5 17 19 22 27 30 33 40 44 57 68 79 90 1.0 Application Information (Continued) in numerical order: Filter 1 (pins 16 and 15) should always precede Filter 2 (pins 5 and 6). If a second MF8 is used, Filter 2 of the first MF8 should precede Filter 1 of the second MF8, and so on. Higher-order filters are designed in a similar manner. An eighth-order Chebyshev with 0.1 dB ripple, center frequency equal to 1 kHz, and 100 Hz bandwidth, for example, could be built as in Figure 11 with the following component values: R0 e 79.86k RF e 100k R2 e 57.82k R3 e 188.08k R4 e 203.42k Pins 1, 3, 17 and 18 high, pin 2 low. For 100:1 clock-to-center-frequency ratio, pin 10 is tied to V a and the clock frequency is 100 kHz. For 50:1 clock-to-center-frequency ratio, pin 10 is tied to V b and the clock frequency is 50 kHz. When building filters of order 4 or higher, best performance will always be realized when the filter blocks are cascaded Dynamic Considerations Some filter response characteristics will result in high gain at certain internal nodes, particularly at the op amp output. This can cause clipping in intermediate stages even when no clipping is evident at the filter output. The consequences are significant distortion and degradation of the overall transfer function. The likelihood of clipping at the op amp output becomes greater as RF/R0 increases. As the design tables show, RF/R0 increases with increasing filter order and increasing ripple. It is good practice to keep out-of-band input signal levels small enough that the first stage can’t overload. 12 TL/H/8694 – 16 FIGURE 8. Butterworth Bandpass Filter Design Nomograph 13 TL/H/8694 – 17 FIGURE 9. Chebyshev Bandpass Filter Design Nomograph 14 TL/H/8694 – 18 FIGURE 10. Example of Chebyshev Bandpass Nomograph Use. SBW e 3, resulting in n e 6. Amax e 1 dB, Amin e 30 dB, and BW 15 1.0 Application Information (Continued) TL/H/8694 – 19 FIGURE 11. Eighth-Order multiple-feedback bandpass filter using two MF8s. The circuit shown accepts a TTL-level clock signal and has a clock-to-center-frequency ratio of 100:1. 1.5 TRACKING AND CASCADED SECOND-ORDER BANDPASS FILTERS The individual second-order bandpass stages may be used as ‘‘stand-alone’’ filters without adding external feedback resistors. The clock frequency and Q logic voltages set the center frequency and bandwidth of both second-order bandpass filters, so the two filters will have equivalent responses. Thus, they may be used as separate ‘‘tracking’’ filters for two different signal sources as in Figure 2a , or cascaded as in Figure 2b . For individual or cascaded second-order bandpass filters, the b3 dB bandwidth and the amplitude response are given by the following two equations: TL/H/8694 – 21 f0 BW(b3) e 02(1/N) b 1 Q N w0 s Q H(s) e 2 c w0 s a w02 s2 a Q % (1) FIGURE 13. Design Nomograph for Cascaded Identical Second-Order Bandpass Filters Q e the Q of each second order bandpass stage f0 e the center frequency of the filter in Hertz w0 e 2 qf0 e the center frequency of the filter in radians per second (2) – where BW(b3) e the b3 dB bandwidth of the overall filter N e the number of cascaded second-order stages e n 2 H(s) e the overall filter transfer function H(s) for a second order bandpass filter is plotted in Figure 12 . Curves are shown for several different values of Q. Center frequency is normalized to 1 Hz and center-frequency gain is normalized to 0 dB. To find the necessary order n for cascaded second-order bandpass filters using the nomograph in Figure 13 , first determine the b3 dB bandwidth BW(b3), stopband width SBW, and minimum stopband attenuation Amin. Draw a vertical line up from SBW/BW(b3), and a horizontal line across from Amin. The required order is shown on the curve just above the point of intersection of the two lines. Remember that each second-order filter section will have a center frequency gain of 2, so the overall gain of a cascaded filter will be 2N. Cascading filters in this way may provide acceptable performance when minimum external parts count is very impor- TL/H/8694–20 FIGURE 12. H(s) For second-order bandpass filters with various values of Q. Ho normalized in each case to 0 dB. 16 1.0 Application Information (Continued) was fs/2 b 10 Hz. This phenomenon is known as ‘‘aliasing’’. Aliasing can be reduced or eliminated by limiting the input signal spectrum to less than fs/2. This may in some cases require the use of a bandwidth-limiting filter (a simple passive RC network will generally suffice) ahead of the MF8 to attenuate unwanted high-frequency signals. However, since the clock frequency is much greater than the center frequency, this will usually not be necessary. tant, but much greater flexibility and better performance will be obtained by using the feedback techniques described in 1.4. 1.6 INPUT IMPEDANCE The input to each filter block is a switched-capacitor circuit as shown in Figure 14 . During the first half of a clock cycle, the input capacitor charges to the input voltage Vin, and during the second half-cycle, its charge is transferred to a feedback capacitor. The input impedance approximates a resistor of value Output Steps Another characteristic of sampled-data circuits is that the output voltage changes only once every clock cycle, resulting in a discontinuous output signal (Figure 15 ). The ‘‘steps’’ are smaller when the clock-to-center-frequency ratio is 100:1 than when the ratio is 50:1. 1 . CinfCLK Cin depends on the value of Q selected by the Q logic pins, and varies from about 1 pF to about 5 pF. For a worst-case calculation of Rin, assume Cin e 5 pF. Thus, Rin j Rin(min) j Clock Frequency Limitations The performance characteristics of a switched-capacitor filter depend on the switching (clock) frequency. At very low clock frequencies (below 10 Hz), the internal capacitors begin to discharge slightly between clock cycles. This is due to very small parasitic leakage currents. At very low clock frequencies, the time between clock cycles is relatively long, allowing the capacitors to discharge enough to affect the filters’ output offset voltage and gain. This effect becomes stronger at elevated operating temperatures. At higher clock frequencies, performance deviations are primarily due to the reduced time available for the internal integrating op amps to settle. For this reason, the clock waveform’s duty cycle should be as close as possible to 50%, especially at higher frequencies. Filter Q shows more variation from the nominal values at higher frequencies, as indicated in the typical performance curves. This is the reason for the different maximum limits on Q accuracy at fCLK e 250 kHz and fCLK e 100 kHz in the table of performance specifications. 1 5 c 10b12fCLK TL/H/8694 – 22 FIGURE 14. Simplified MF8 Input Stage At the maximum clock frequency of 1 MHz, this gives Rin j 200k. Note that Rin increases as fCLK decreases, so the input impedance should never be less than this number. Source impedance should be low enough that the gain isn’t significantly affected. Center Frequency Accuracy Ideally, the ratio fCLK/f0 should be precisely 100 or 50, depending on the logic voltage on pin 10. However, as Table I shows, this ratio will change slightly depending on the Q selected. As the table shows, the largest errors occur at the lowest values of Q. 1.7 OUTPUT DRIVE The filter outputs can typically drive a 5 kX load resistor to over g 4V peak-to-peak. Load resistors smaller than 5 kX should not be used. The operational amplifier can drive the minimum recommended load resistance of 5 kX to at least g 3.5V. 1.8 SAMPLED-DATA SYSTEM CONSIDERATIONS Aliasing The MF8 is a sampled-data filter, and as such, differs in many ways from conventional continuous-time filters. An important characteristic of sampled-data systems is their effect on signals at frequencies greater than one-half the sampling frequency. (The MF8’s sampling frequency is the same as its clock frequency). If a signal with a frequency greater than one-half the sampling frequency is applied to the input of a sampled-data system, it will be ‘‘reflected’’ to a frequency less than one-half the sampling frequency. Thus, an input signal whose frequency is fs/2 a 10 Hz will cause the system to respond as though the input frequency TL/H/8694 – 23 FIGURE 15. Output Waveform of MF8 Showing Sampling Steps 17 2.0 Design Tables for Multiple Feedback Loop Bandpass Filters BUTTERWORTH Order K0 K2 4 6 8 10 *12 2.0000 2.3704 2.9142 3.6340 4.5635 4.0000 2.6667 2.0000 1.6000 1.3333 K3 Order K0 K2 K3 4 6 8 *10 1.9041 1.8277 1.4856 1.0171 3.6339 1.8450 0.9919 0.5740 6.6170 3.1209 1.7484 K4 9.1429 5.8284 4.4112 3.5800 CHEBYSHEV CHEBYSHEV Order K0 K2 4 6 8 *10 1.8644 1.7024 1.2893 0.8163 3.4922 1.6787 0.8707 0.4934 K0 K2 4 6 8 *10 1.8341 1.6183 1.1688 0.7034 3.3871 1.5713 0.7977 0.4467 K4 5.0414 1.2943 K4 4.0779 0.9879 K0 K2 1.8085 1.5535 1.0814 0.6264 3.3009 1.4908 0.7454 0.4139 Order K0 K2 K4 K3 4 6 8 *10 1.7860 1.5002 1.0129 0.5686 3.2268 1.4260 0.7046 0.3888 5.2373 2.2685 1.2072 Order K0 K2 K3 4 6 8 *10 1.7657 1.4548 0.9566 0.5230 3.1612 1.3717 0.6713 0.3685 5.0536 2.1670 1.1467 3.5270 0.8252 K4 5.4548 2.3919 1.2818 CHEBYSHEV K5 K6 KQ 0.4489 0.9438 1.4257 1.8908 4.8814 K5 K6 KQ 0.5393 1.0849 1.6106 2.1179 3.7119 K5 K6 KQ 0.6016 1.1808 1.7362 2.2724 3.0938 RIPPLE 0.04 dB K3 CHEBYSHEV 49.0673 RIPPLE 0.03 dB 5.7231 2.5491 1.3786 4 6 8 *10 KQ 1.4142 1.5000 1.5307 1.5451 1.5529 RIPPLE 0.02 dB K3 Order 27.2014 11.5043 K6 RIPPLE 0.01 dB 6.0772 2.7661 1.5155 CHEBYSHEV K5 14.3145 6.9094 4.3198 K3 CHEBYSHEV Order RIPPLE 3 dB 3.1471 0.7181 K5 K6 KQ 0.6508 1.2560 1.8348 2.3940 2.6883 RIPPLE 0.05 dB K4 2.8609 0.6402 K5 K6 KQ 0.6923 1.3191 1.9175 2.4961 2.3938 RIPPLE 0.06 dB K4 2.6336 0.5800 18 K5 2.1666 K6 KQ 0.7285 1.3741 1.9897 2.5852 2.0 Design Tables for Multiple Feedback Loop Bandpass Filters (Continued) CHEBYSHEV Order K0 K2 4 6 8 *10 1.7471 1.4150 0.9089 0.4856 3.1020 1.3249 0.6431 0.3516 K3 K0 K2 4 6 8 1.7298 1.3795 0.8675 3.0478 1.2837 0.6187 Order K0 K2 4 6 8 1.7136 1.3475 0.8311 2.9978 1.2469 0.5973 K4 4.8943 2.0808 1.0959 CHEBYSHEV Order RIPPLE .07 dB 2.4466 0.5316 K3 K4 4.7534 2.0060 2.2887 CHEBYSHEV RIPPLE .09 dB K3 K4 4.6271 1.9400 2.1529 CHEBYSHEV RIPPLE 0.1 dB K0 K2 4 6 8 1.6983 1.3183 0.7986 2.9512 1.2137 0.5782 Order K0 K2 4 6 8 1.5757 1.1128 0.5891 2.5998 0.9894 0.4551 Order K0 K2 K3 4 6 *8 1.4833 0.9835 0.4732 2.3575 0.8560 0.3861 3.2501 1.2760 0.9885 CHEBYSHEV RIPPLE 0.4 dB K0 K2 4 6 *8 1.4067 0.8888 0.3956 2.1698 0.7618 0.3391 Order K0 K2 4 6 *8 1.3405 0.8143 0.3389 2.0161 0.6897 0.3040 K6 KQ 0.7609 1.4232 2.0543 2.6649 1.9842 RIPPLE .08 dB Order Order K5 K3 K4 4.5125 1.8809 2.0343 CHEBYSHEV RIPPLE 0.2 dB K3 K4 3.7271 1.4954 1.3309 CHEBYSHEV RIPPLE 0.3 dB K4 K3 K4 2.9088 1.1250 0.7792 CHEBYSHEV RIPPLE 0.5 dB K3 K4 2.6447 1.0114 0.6365 19 K5 K6 KQ 0.7905 1.4679 2.1130 K5 K6 KQ 0.8177 1.5090 2.1671 K5 K6 KQ 0.8430 1.5473 2.2176 K5 K6 KQ 1.0378 1.8413 2.6057 K5 K6 KQ 1.1804 2.0568 2.8914 K5 K6 KQ 1.2988 2.2363 3.1299 K5 K6 KQ 1.4029 2.3944 3.3406 2.0 Design Tables for Multiple Feedback Loop Bandpass Filters (Continued) CHEBYSHEV Order K0 K2 4 6 *8 1.2816 0.7530 0.2952 1.8857 0.6316 0.2762 Order K0 K2 4 6 *8 1.2283 0.7012 0.2601 1.7727 0.5834 0.2535 RIPPLE 0.6 dB K3 K4 2.4305 0.9212 0.5326 CHEBYSHEV RIPPLE 0.7 dB K3 K4 2.2515 0.8471 0.4535 CHEBYSHEV RIPPLE 0.8 dB Order K0 K2 4 6 *8 1.1797 0.6564 0.2314 1.6731 0.5424 0.2344 K3 K4 Order K0 K2 K3 4 6 *8 1.1347 0.6171 0.2073 1.5841 0.5068 0.2181 1.9650 0.7309 0.3413 CHEBYSHEV RIPPLE 1.0 dB 2.0983 0.7846 0.3913 CHEBYSHEV RIPPLE 0.9 dB K4 Order K0 K2 4 6 *8 1.0930 0.5822 0.1869 1.5039 0.4756 0.2038 Order K0 K2 K3 4 6 *8 1.0539 0.5509 0.1693 1.4310 0.4479 0.1913 1.7428 0.6426 0.2660 CHEBYSHEV RIPPLE 1.2 dB Order K0 K2 4 6 *8 1.0173 0.5226 0.1540 1.3643 0.4231 0.1801 Order K0 K2 4 6 *8 0.9828 0.4969 0.1406 1.3029 0.4006 0.1701 K3 K4 1.8475 0.6840 0.3002 CHEBYSHEV RIPPLE 1.1 dB K4 K3 K4 1.6487 0.6056 0.2372 CHEBYSHEV RIPPLE 1.3 dB K3 K4 1.5634 0.5724 0.2125 20 K5 K6 KQ 1.4975 2.5385 3.5329 K5 K6 KQ 1.5852 2.6724 3.7119 K5 K6 KQ 1.6678 2.7989 3.8811 K5 K6 KQ 1.7464 2.9194 4.0426 K5 K6 KQ 1.8219 3.0354 4.1981 K5 K6 KQ 1.8949 3.1476 4.3487 K5 K6 KQ 1.9657 3.2567 4.4952 K5 K6 KQ 2.0348 3.3633 4.6385 2.0 Design Tables for Multiple Feedback Loop Bandpass Filters (Continued) CHEBYSHEV Order K0 K2 4 6 0.9501 0.4733 1.2461 0.3803 RIPPLE 1.4 dB K3 K4 K0 K2 4 6 0.9192 0.4515 1.1934 0.3616 Order K0 K2 K3 K4 K3 4 6 0.8897 0.4315 1.1443 0.3445 1.3490 Order K0 K2 K3 4 6 0.8617 0.4128 1.0983 0.3287 1.2883 Order K0 K2 K3 4 6 0.8350 0.3955 1.0553 0.3141 1.2321 Order K0 K2 K3 4 6 0.8095 0.3793 1.0148 0.3005 1.1797 K0 K2 0.7616 0.3498 0.9407 0.2759 K0 K2 4 6 0.7391 0.3364 0.9067 0.2648 K5 K6 KQ 2.2986 3.7717 K4 K5 K6 KQ 2.3624 3.8706 RIPPLE 1.9 dB K4 K5 K6 KQ 2.4255 3.9687 RIPPLE 2.0 dB K3 K4 K5 K6 KQ 2.4881 4.0660 1.1308 RIPPLE 2.1 dB K3 K4 K5 K6 KQ 2.5503 4.1628 1.0850 CHEBYSHEV Order KQ RIPPLE 1.8 dB CHEBYSHEV 4 6 K6 2.2341 3.6717 K4 CHEBYSHEV Order K5 RIPPLE 1.7 dB CHEBYSHEV K2 KQ 2.1688 3.5705 K4 CHEBYSHEV 0.9767 0.2878 K6 RIPPLE 1.6 dB CHEBYSHEV K0 K5 1.4145 CHEBYSHEV 0.7850 0.3641 KQ 2.1024 3.4678 RIPPLE 1.5 dB Order 4 6 K6 1.4857 CHEBYSHEV Order K5 RIPPLE 2.2 dB K3 K4 1.0420 21 K5 K6 KQ 2.6122 4.2591 2.0 Design Tables for Multiple Feedback Loop Bandpass Filters (Continued) CHEBYSHEV Order K0 K2 4 6 0.7176 0.3237 0.8744 0.2544 RIPPLE 2.3 dB K3 K4 K0 K2 4 6 0.6968 0.3118 0.8438 0.2446 K0 K2 4 6 0.6769 0.3005 0.8148 0.2353 K3 K4 K0 K2 4 6 0.6577 0.2897 0.7871 0.2265 K0 K2 4 6 0.6392 0.2796 0.7607 0.2182 K6 KQ 2.7350 4.4507 RIPPLE 2.5 dB K3 K4 K5 K6 KQ 2.7962 4.5462 0.9275 RIPPLE 2.6 dB K3 K4 K5 K6 KQ 2.8573 4.6415 0.8935 CHEBYSHEV Order K5 0.9635 CHEBYSHEV Order KQ 2.6737 4.3550 RIPPLE 2.4 dB CHEBYSHEV Order K6 1.0016 CHEBYSHEV Order K5 RIPPLE 2.7 dB K3 K4 K5 K6 0.8612 CHEBYSHEV KQ 2.9183 4.7368 RIPPLE 2.8 dB Order K0 K2 4 6 0.6213 0.2699 0.7356 0.2104 K3 K4 Order K0 K2 K3 4 6 0.6041 0.2607 0.7116 0.2029 0.8016 Order K0 K2 K3 4 6 0.5875 0.2519 0.6886 0.1959 0.7739 K5 K6 0.8306 CHEBYSHEV KQ 2.9792 4.8322 RIPPLE 2.9 dB K4 CHEBYSHEV K5 K6 KQ 3.0402 4.9276 RIPPLE 3.0 dB K4 K5 K6 KQ 3.1013 5.0231 Note: Multiple feedback loop filters of higher order than those specified in the tables will oscillate due to phase shift at the output of the summing amplifier. This phase shift is not the fault of the MF8; it is inherent in this type of multiple feedback loop topology. In addition, all filters marked with an asterisk (*) will be unstable for Q s 1, due to phase shifts caused by the MF8’s switched-capacitor design approach. 22 Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MF8CCJ NS Package Number J18A 23 MF8 4th-Order Switched Capacitor Bandpass Filter Physical Dimensions inches (millimeters) (Continued) Lit. Ý 108778 Molded Dual-In-Line Package (N) Order Number MF8CCN NS Package Number N18A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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