LM4817 1W Stereo Audio Amplifier Plus Adjustable Output Limiter Plus Adjustable LDO General Description Key Specifications The LM4817 combines a bridge-connected (BTL) stereo audio power amplifier with a low dropout voltage regulator (LDO). The audio amplifier delivers 1.0W to a 8Ω load with a less than 1.0% THD+N while operating on a 5V power supply. With VLIM set to 1.0V, the amplifier outputs are clamped to 6Vp-p, ± 800mV. n n n n n n n n n n n With the LM4817’s adjustable low-dropout (LDO) CMOS linear regulator delivers an output current of up to 300mA, has shutdown mode (1nA, typ) low quiescent current (90µA, typ) and LDO voltage (120mV, typ). The regulator is stable with small ceramic capacitive load (2.2µF, typ). The regulator includes regulation fault detection, a bandgap voltage reference, and constant current limiting. It is designed for low power, low current applications that can take advantage of its 300mA output current capability. The LM4817 features an externally controlled micropower shutdown mode and thermal shutdown protection. It also utilizes circuitry that reduces "clicks and pops" during device turn-on and return from shutdown. Boomer audio power amplifiers are designed specifically to use few external components and provide high quality output power in a surface mount package. PO (BTL): VDD = 5V, THD+N ≤ 1%, RL = 8Ω 1.0W(typ) Power supply range (amplifier) 3.0V to 5.5V Power supply range (LDO) 2.5V to 6.0V Shutdown current 0.07µA (typ) LDO output current 300mA (min) LDO dropout voltage (IOUT = 300mA) 120mV (typ) LDO quiescent supply current 90µA (typ) LDO shutdown supply current 1nA (typ) LDO PSRR 60dB LDO turn-on time 120ms (typ) LDO ouput noise-voltage 37µVRMS (typ) Features n n n n n n n n n Stereo BTL amplifier Adjustable output voltage magnitude limiter Adjustable LDO regulator “Click and pop” suppression circuitry LDO is stable with small-value ceramic output capacitors Unity-gain stable audio amplifiers LDO has over-current protection Thermal shutdown protection circuitry TSSOP (MH) package Applications n Multimedia monitors n Portable and desktop computers n Portable televisions Connection Diagram 20078129 Top View Order Number LM4817MH See NS Package Number MXA28A for TSSOP Boomer ® is a registered trademark of National Semiconductor Corporation. © 2004 National Semiconductor Corporation DS200781 www.national.com LM4817 1W Stereo Audio Amplifier Plus Adjustable Output Limiter Plus Adjustable LDO March 2004 LM4817 Typical Application 20078101 www.national.com 2 −0.3V to 6.5V Fault Sink Current Infrared (15 sec.) 220˚C Thermal Resistance 6.0V LDO-VCC, LDO-OUT, LDO-SHDN, ADJ, CC, FAULT (pins 11-15, 17,19) 215˚C See AN-450 “Surface Mounting and their Effects on Product Reliablilty” for other methods of soldering surface mount devices. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Amplifier Supply Voltage (pins 5, 24) Vapor Phase (60 sec.) θJC (typ) — MXA28A 20˚C/W θJA (typ) — MXA28A (Note 2) 41˚C/W 20mA Storage Temperature Input Voltage Operating Ratings −65˚C to +150˚C −0.3V to VDD +0.3V Power Dissipation (Note 2) Internally limited ESD Susceptibility(Note 3) 2000V ESD Susceptibility (Note 4) Temperature Range TMIN ≤ TA ≤ TMAX 200V Junction Temperature −40˚C ≤ TA ≤ 85˚C Supply Voltage 150˚C Solder Information Pins 5, 24 3.0V ≤ VDD ≤ 5.5V Pin 17 2.5V ≤ VCC ≤ 6.0V Small Outline Package Stereo Amplifier Electrical Characteristics for Entire IC (Notes 1, 5) The following specifications apply for VDD = 5V unless otherwise noted. Limits apply for TA = 25˚C. Symbol VDD Parameter Conditions LM4817 Typical Limit (Note 6) (Note 7) Supply Voltage Units (Limits) 3 V (min) 5.5 V (max) 15 5 mA (max) mA (min) IDD Quiescent Power Supply Current VIN = 0V, IO = 0A (Note 8) ISD Shutdown Current VDD applied to the SHUTDOWN pin 2 µA (min) VIH Shutdown Logic High Input Threshold Voltage 3.0 V (min) VIL Shutdown Logic Low Input Threshold Voltage 1.8 V (max) VOS Output Offset Voltage VIN = 0V 5 50 mV (max) PO Output Power (Note 9) THD+N = 1%, f = 1kHz, RL = 8Ω 1.1 1.0 W (min) THD+N = 10%, f = 1kHz, RL = 8Ω 1.5 W 20Hz ≤ f ≤ 20kHz, AVD = 2 RL = 8Ω, PO = 1W 0.13 % THD+N Total Harmonic Distortion+Noise VLIM Limiter Clamp Voltage PSRR Power Supply Rejection Ratio 8 0.07 VLIM = 1.0V, RL = ∞, VIN = 4VP-P VO P-P = (VOUT+ - VOUT-) 6.0 5.2 6.8 VP-P (min) VP-P (max) VDD = 5V, VRIPPLE = 200mVRMS, RL = 8Ω, CB = 1.0µ, fIN = 1kHz Inputs Floating Inputs terminated with 10Ω 67 45 dB dB XTALK Channel Separation f = 1kHz, CB = 1.0µF 90 dB SNR Signal To Noise Ratio VDD = 5V, PO = 1W, RL = 8Ω 98 dB LDO Electrical Characteristics Unless otherwise specified, all limits guaranteed for VIN = VO +0.5V (Note 10), VSHDN = VIN, CIN = COUT = 2.2µF, CCC = 33nF, TJ = 25˚C. Boldface limits apply for the operating temperature extremes: −40˚C and 85˚C. Symbol VIN Parameter Conditions Min (Note 7) Input Voltage 2.5 3 Typ (Note 6) Max (Note 7) Units 6.0 V www.national.com LM4817 Absolute Maximum Ratings Stereo Amplifier(Notes 1, 5) LM4817 LDO Electrical Characteristics (Continued) Unless otherwise specified, all limits guaranteed for VIN = VO +0.5V (Note 10), VSHDN = VIN, CIN = COUT = 2.2µF, CCC = 33nF, TJ = 25˚C. Boldface limits apply for the operating temperature extremes: −40˚C and 85˚C. Symbol Parameter ∆VO Output Voltage Tolerance VO Output Adjust Range IO Maximum Output Current ILIMIT Output Current Limit IQ Supply Current VDO Conditions Min (Note 7) 100µA ≤ IOUT ≤ 300mA VIN = VO + 0.5V (Note 7) SET = OUT Average DC Current Rating Typ (Note 6) -2.4 +2.4 -3 +3 1.25 6 300 330 770 90 IOUT = 300mA 225 VO = 0V, SHDN = GND Dropout Voltage (Note 10), (Note 11) IOUT = 1mA Units % of VOUT (NOM) V mA IOUT = 0mA Shutdown Supply Current Max (Note 7) 0.001 mA 270 µA 1 µA 220 mV 0.1 %/V 0.4 IOUT = 200mA 80 IOUT = 300mA 120 ∆VO Line Regulation Load Regulation 100µA ≤ IOUT ≤ 300mA 0.002 %/mA en Output Voltage Noise IOUT = 10mA, 10Hz ≤ f ≤ 100kHz 37 µVRMS Output Voltage Noise Density 10Hz ≤ f ≤ 100kHz, COUT = 10µF 190 SHDN Input Threshold VIH, (VO + 0.5V) ≤ VI ≤ 6V (Note 10) VSHDN IOUT = 1mA, (VO + 0.5V) ≤ VI ≤ 6V (Note 10) -0.1 0.01 nV/ 2 V VIL, (VO + 0.5V) ≤ VI ≤ 6V 0.4 ISHDN SHDN Input Bias Current SHDN = GND or IN 0.1 100 nA ISET SET Input Leakage SET = 1.3V 0.1 2.5 nA VFAULT FAULTDetection Voltage VO ≥ 2.5V, IOUT = 200mA (Note 12) 120 280 mV 0.115 0.25 V 0.1 100 nA FAULT Output Low Voltage ISINK = 2mA IFAULT FAULT Off-Leakage Current FAULT = 3.6V, SHDN = 0V TSD Thermal Shutdown Temperature 160 Thermal Shutdown Hysteresis 10 TON Start-Up Time ˚C COUT = 10µF, VO at 90% of Final Value 120 µs Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit is given, however, the typical value is a good indication of device performance. Note 2: The maximum power dissipation is dictated by TJMAX, θJA, and the ambient temperature TA and must be derated at elevated temperatures. The maximum allowable power dissipation is PDMAX = (TJMAX − TA)/θJA. For the LM4817, TJMAX = 150˚C. The θJAfor the LM4817 in the 28-pin MXA28A package, when board mounted and its DAP is soldered to a 2in2 copper heatsink plane, is 41˚C/W. Note 3: Human body model, 100pF discharged through a 1.5kΩ resistor. Note 4: Machine model, 220pF–240pF discharged through all pins. Note 5: All voltages are measured with respect to the ground (GND) pins unless otherwise specified. Note 6: Typicals are measured at 25˚C and represent the parametric norm. Note 7: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Note 8: The quiescent power supply current depends on the offset voltage when a practical load is connected to the amplifier. Note 9: Output power is measured at the device terminals. Note 10: Condition does not apply to input voltages below 2.5V since this is the minimum input operating voltage. Note 11: Dropout voltage is measured by reducing VIN until VO drops 100mV from its nominal value at VIN -VO = 0.5V. Dropout Voltage does not apply to the 1.8 version. Note 12: The FAULT detection voltage is specified for the input to output voltage differential at which the FAULT pin goes active low. www.national.com 4 LM4817 Stereo Amplifier Typical Performance Characteristics THD+N vs Frequency THD+N vs Frequency 20078117 20078124 VDD = 3V, RL = 8Ω, POUT = 150mW VDD = 5V, RL = 8Ω, POUT = 150mW THD+N vs Frequency THD+N vs Output Power 20078120 20078128 VDD = 5.5V, RL = 8Ω, POUT = 150mW VDD = 3V, RL = 8Ω, fIN = 1kHz THD+N vs Output Power THD+N vs Output Power 20078133 VDD = 5V, RL = 8Ω, fIN = 1kHz 20078130 VDD = 5.5V, RL = 8Ω, fIN = 1kHz 5 www.national.com LM4817 Stereo Amplifier Typical Performance Characteristics Output Power vs Supply Voltage (Continued) Output Power vs Load Resistance 20078102 20078137 RL = 8Ω, fIN = 1kHz, at (from top to bottom at 4.5V): THD+N = 10%, THD+N = 1% RL = 8Ω, fIN = 1kHz, at (from top to bottom at 24Ω): THD+N = 10%, THD+N = 1% Power Dissipation vs Load Dissipation Dropout Voltage vs Supply Voltage 20078134 20078115 VDD = 5V, fIN = 1kHz, at (from top to bottom at 0.2W): RL = 8Ω, RL = 16Ω, RL = 32Ω Power Derating Curve Cross Talk 20078104 VDD = 3V, RL = 8Ω, POUT= 150mW, at (from top to bottom at 2kHz): -IN A driven, VOUTB measured; -IN B driven, VOUTA measured 20078116 VDD = 5V, RL = 8Ω, fIN = 1kHz 2in2 copper heatsink area www.national.com 6 Cross Talk LM4817 Stereo Amplifier Typical Performance Characteristics (Continued) Cross Talk 20078107 20078105 VDD = 5V, RL = 8Ω, POUT= 150mW, at (from top to bottom at 2kHz): -IN A driven, VOUTB measured; -IN B driven, VOUTA measured VDD = 5.5V, RL = 8Ω, POUT= 150mW, at (from top to bottom at 2kHz): -IN A driven, VOUTB measured; -IN B driven, VOUTA measured PSRR vs Frequency PSRR vs Frequency 20078110 VRIPPLE 20078108 VDD = 3V, RL = 8Ω, RSOURCE= 10Ω, = 200mVP-P, at (from top to bottom at 500Hz): CBYPASS = 0.1µF, CBYPASS = 1.0µF VRIPPLE PSRR vs Frequency PSRR vs Frequency 20078113 VRIPPLE VDD = 3V, RL = 8Ω, RSOURCE= ∞, = 200mVP-P, at (from top to bottom at 500Hz): CBYPASS = 0.1µF, CBYPASS = 1.0µF 20078111 VDD = 5V, RL = 8Ω, RSOURCE= 10Ω, = 200mVP-P, at (from top to bottom at 500Hz): CBYPASS = 0.1µF, CBYPASS = 1.0µF VRIPPLE 7 VDD = 5V, RL = 8Ω, RSOURCE= ∞, = 200mVP-P, at (from top to bottom at 500Hz): CBYPASS = 0.1µF, CBYPASS = 1.0µF www.national.com LM4817 Stereo Amplifier Typical Performance Characteristics Open Loop Frequency Response (Continued) Power Supply Current vs Power Supply Voltage 20078135 RL = ∞, RSOURCE = 50Ω, VIN = 0V 20078122 THD+N vs Output Power 20078138 VLIM VDD = 5V, RL = 8Ω, fIN = 1kHz, at (from left to right at 7% THD+N): = 2V, 1.9V, 1.8V, 1.7V, 1.6V, 1.5V, 1.0V, 0.5V, 0V www.national.com 8 Unless otherwise specified, VIN = VOUT + 0.5V, CIN = Dropout Voltage vs Load Current (For Different Output Voltages) Dropout Voltage vs Load Current (For Different Output Temperatures) 200781A2 200781A3 FAULT Detect Threshold vs Load Current Supply Current vs Input Voltage 200781A4 200781A5 Supply Current vs Load Current Power Supply Rejection Ratio vs Frequency 200781A6 200781A7 9 www.national.com LM4817 LDO Typical Performance Characteristics COUT = 2.2µF, CCC = 33nF, TJ = 25˚C, VSHDN = VIN. LM4817 LDO Typical Performance Characteristics Unless otherwise specified, VIN = VOUT + 0.5V, CIN = COUT = 2.2µF, CCC = 33nF, TJ = 25˚C, VSHDN = VIN. (Continued) Output Noise Spectral Density Output Noise (10Hz to 100kHz) 200781A9 200781A8 Output Impedance vs Frequency Line Transient Response 200781B1 200781B0 Load Transient Shutdown Response 200781B3 200781B2 www.national.com 10 Power-Up Response Power-Down Response 200781B5 200781B4 External Components Description (Refer to Figure 1 ). Components Functional Description 1. Ri The Inverting input resistance, along with Rf, set the closed-loop gain. Ri, along with Ci, form a high pass filter with fc = 1/(2πRiCi). 2. Ci The input coupling capacitor blocks DC voltage at the amplifier’s input terminals. Ci, along with Ri, create a highpass filter with fc = 1/(2πRiCi). Refer to the section, SELECTING PROPER EXTERNAL COMPONENTS, for an explanation of determining the value of Ci. 3. Rf The feedback resistance, along with Ri, set the closed-loop gain. 4. Cs The supply bypass capacitor. Refer to the POWER SUPPLY BYPASSING section for information about properly placing, and selecting the value of, this capacitor. 5. CB The capacitor, CB, filters the half-supply voltage present on the BYPASS pin. Refer to the SELECTING PROPER EXTERNAL COMPONENTS section for information concerning proper placement and selecting CB’s value. 6. R1 Combined with R2, sets the LDO’s output voltage according to the following equation: R1 = R2 ((VOUT / 1.25V) -1) 7. R2 Combined with R1, sets the LDO’s output voltage according to the following equation: R2 = (1.25V x R1) / (VOUT - 1.25V) 11 www.national.com LM4817 LDO Typical Performance Characteristics Unless otherwise specified, VIN = VOUT + 0.5V, CIN = COUT = 2.2µF, CCC = 33nF, TJ = 25˚C, VSHDN = VIN. (Continued) LM4817 Application Information BRIDGE CONFIGURATION EXPLANATION 20078101 * Refer to the section Proper Selection of External Components, for a detailed discussion of CB size. FIGURE 1. Typical Audio Amplifier Application Circuit Pin out shown for the LLP package. Refer to the Connection Diagrams for the pinout of the TSSOP package. As shown in Figure 1, the LM4817 consists of two pairs of operational amplifiers, forming a two-channel (channel A and channel B) stereo amplifier. (Though the following discusses channel A, it applies equally to channel B.) External resistors Rf and Ri set the closed-loop gain of Amp1A, whereas two internal 20kΩ resistors set Amp2A’s gain at -1. The LM4817 drives a load, such as a speaker, connected between the two amplifier outputs, -OUTA and +OUTA. Figure 1 shows that Amp1A’s output serves as Amp2A’s input. This results in both amplifiers producing signals identical in magnitude, but 180˚ out of phase. Taking advantage of this phase difference, a load is placed between -OUTA and +OUTA and driven differentially (commonly referred to as "bridge mode"). This results in a differential gain of (1) AVD = 2 x (Rf / Ri) Bridge mode amplifiers are different from single-ended amplifiers that drive loads connected between a single amplifier’s output and ground. For a given supply voltage, bridge mode has a distinct advantage over the single-ended configuration: its differential output doubles the voltage swing across the load. This produces four times the output power when compared to a single-ended amplifier under the same conditions. This increase in attainable output power assumes that the amplifier is not current limited or that the www.national.com output signal is not clipped. To ensure minimum output signal clipping when choosing an amplifier’s closed-loop gain, refer to the Audio Power Amplifier Design section. Another advantage of the differential bridge output is no net DC voltage across the load. This is accomplished by biasing channel A’s and channel B’s outputs at half-supply. This eliminates the coupling capacitor that single supply, singleended amplifiers require. Eliminating an output coupling capacitor in a single-ended configuration forces a single-supply amplifier’s half-supply bias voltage across the load. This increases internal IC power dissipation and may permanently damage loads such as speakers. POWER DISSIPATION Power dissipation is a major concern when designing a successful single-ended or bridged amplifier. Equation (2) states the maximum power dissipation point for a singleended amplifier operating at a given supply voltage and driving a specified output load (2) PDMAX = (VDD)2 / (2π2 RL) Single-Ended However, a direct consequence of the increased power delivered to the load by a bridge amplifier is higher internal power dissipation for the same conditions. 12 Without the limiter’s influence (VLIM = 0V), the LM4817’s maximum BTL output swing is nominally (Continued) The LM4817 has two operational amplifiers per channel. The maximum internal power dissipation per channel operating in the bridge mode is four times that of a single-ended amplifier. From Equation (3), assuming a 5V power supply and an 8Ω load, the maximum single channel power dissipation is 0.633W or 1.27W for stereo operation. (3) PDMAX = 4 x (VDD)2 / (2π2 RL) Bridge Mode 2 x VDD When the limiter input voltage is greater than 0V, the BTL output voltage swing is VOUT-BTL = (2 x VDD) - (4 x VLIM) For any given value of VLIM, the actual output swing will be limited to within ± 200mV. The LM4817’s power dissipation is twice that given by Equation (2) or Equation (3) when operating in the single-ended mode or bridge mode, respectively. Twice the maximum power dissipation point given by Equation (3) must not exceed the power dissipation given by Equation (4): (4) PDMAX’ = (TJMAX − TA) / θJA The LM4817’s TJMAX = 150˚C. In the MH package soldered to a DAP pad that expands to a copper area of 2in2 on a PCB , the LM4817’s θJA is 41˚C/W. At any given ambient temperature TJ\A, use Equation (4) to find the maximum internal power dissipation supported by the IC packaging. Rearranging Equation (4) and substituting PDMAX for PDMAX’ results in Equation (5). This equation gives the maximum ambient temperature that still allows maximum stereo power dissipation without violating the LM4817’s maximum junction temperature. (5) TA = TJMAX − 2 x PDMAX θJA For a typical application with a 5V power supply and an 8Ω load, the maximum ambient temperature that allows maximum stereo power dissipation without exceeding the maximum junction temperature is approximately 98˚C for the MH package. (6) TJMAX = PDMAX θJA + TA Equation (6) gives the maximum junction temperature TJMAX. If the result violates the LM4817’s 150˚C, reduce the maximum junction temperature by reducing the power supply voltage or increasing the load resistance. Further allowance should be made for increased ambient temperatures. POWER SUPPLY BYPASSING As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply rejection. Applications that employ a 5V regulator typically use a 10µF in parallel with a 0.1µF filter capacitors to stabilize the regulator’s output, reduce noise on the supply line, and improve the supply’s transient response. However, their presence does not eliminate the need for a local 1.0µF tantalum bypass capacitance connected between the LM4817’s supply pins and ground. Do not substitute a ceramic capacitor for the tantalum. Doing so may cause oscillation in the output signal. Keep the length of leads and traces that connect capacitors between the LM4817’s power supply pin and ground as short as possible. Connecting a 1µF capacitor, CB, between the BYPASS pin and ground improves the internal bias voltage’s stability and improves the amplifier’s PSRR. The PSRR improvements increase as the bypass pin capacitor value increases. Too large, however, increases turn-on time and can compromise amplifier’s click and pop performance. The selection of bypass capacitor values, especially CB, depends on desired PSRR requirements, click and pop performance (as explained in the section, Proper Selection of External Components), system cost, and size constraints. MICRO-POWER SHUTDOWN The voltage applied to the SHUTDOWN pin controls the LM4817’s shutdown function. Activate micro-power shutdown by applying VDD to the SHUTDOWN pin. When active, the LM4817’s micro-power shutdown feature turns off the amplifier’s bias circuitry, reducing the supply current. The logic threshold is typically VDD/2. The low 0.7µA typical shutdown current is achieved by applying a voltage that is as near as VDD as possible to the SHUTDOWN pin. A voltage thrat is less than VDD may increase the shutdown current. There are a few ways to control the micro-power shutdown. These include using a single-pole, single-throw switch, a microprocessor, or a microcontroller. When using a switch, connect an external 10kΩ pull-up resistor between the SHUTDOWN pin and VDD. Connect the switch between the SHUTDOWN pin and ground. Select normal amplifier operation by closing the switch. Opening the switch connects the SHUTDOWN pin to VDD through the pull-up resistor, activating micro-power shutdown. The switch and resistor guarantee that the SHUTDOWN pin will not float. This prevents unwanted state changes. In a system with a microprocessor or a microcontroller, use a digital output to apply the control voltage to the SHUTDOWN pin. Driving the SHUTDOWN pin with active circuitry eliminates the pull up resistor. TABLE 1. LOGIC LEVEL TRUTH TABLE FOR SHUTDOWN OPERATION The above examples assume that a device is a surface mount part operating around the maximum power dissipation point. Since internal power dissipation is a function of output power, higher ambient temperatures are allowed as output power or duty cycle decreases. If twice the value given by Equation (3) exceeds the result of Equation (4), then decrease the supply voltage, increase the load impedance, or reduce the ambient temperature. If these measures are insufficient, a heat sink can be added to reduce θJA. The heat sink can be created using additional copper area around the package, with connections to the ground pin(s), supply pin and amplifier output pins. External, solder attached SMT heatsinks such as the Thermalloy 7106D can also improve power dissipation. When adding a heat sink, the θJA is the sum of θJC, θCS, and θSA. (θJC is the junction−to−case thermal impedance, CS is the case−to−sink thermal impedance, and θSAis the sink−to−ambient thermal impedance.) Refer to the Typical Performance Characteristics curves for power dissipation information at lower output power levels. OUTPUT VOLTAGE LIMITER The LM4817’s adjustable output voltage limiter can be used to set a maximum and minimum output voltage swing magnitude. The voltage applied to the VLIM input (pin 28) controls the amount voltage limit magnitude. 13 SHUTDOWN OPERATIONAL MODE Low Full power, stereo BTL amplifiers High Micro-power Shutdown www.national.com LM4817 Application Information LM4817 Application Information the LM4817 settles to quiescent operation, its value is critical when minimizing turn−on pops. The slower the LM4817’s outputs ramp to their quiescent DC voltage (nominally 1/2 VDD), the smaller the turn−on pop. Choosing CB equal to 1.0µF along with a small value of Ci (in the range of 0.1µF to 0.39µF), produces a click-less and pop-less shutdown function. As discussed above, choosing Ci no larger than necessary for the desired bandwidth helps minimize clicks and pops. (Continued) SELECTING PROPER EXTERNAL COMPONENTS Optimizing the LM4817’s performance requires properly selecting external components. Though the LM4817 operates well when using external components with wide tolerances, best performance is achieved by optimizing component values. The LM4817 is unity-gain stable, giving a designer maximum design flexibility. The gain should be set to no more than a given application requires. This allows the amplifier to achieve minimum THD+N and maximum signal-to-noise ratio. These parameters are compromised as the closed-loop gain increases. However, low gain demands input signals with greater voltage swings to achieve maximum output power. Fortunately, many signal sources such as audio CODECs have outputs of 1VRMS (2.83VP-P). Please refer to the Audio Power Amplifier Design section for more information on selecting the proper gain. OPTIMIZING CLICK AND POP REDUCTION PERFORMANCE The LM4817 contains circuitry to minimize turn-on and shutdown transients or "clicks and pop". For this discussion, turn-on refers to either applying the power supply voltage or when the shutdown mode is deactivated. While the power supply is ramping to its final value, the LM4817’s internal amplifiers are configured as unity gain buffers. An internal current source changes the voltage of the BYPASS pin in a controlled, linear manner. Ideally, the input and outputs track the voltage applied to the BYPASS pin. The gain of the internal amplifiers remains unity until the voltage on the bypass pin reaches 1/2 VDD. As soon as the voltage on the BYPASS pin is stable, the device becomes fully operational. Although the bypass pin current cannot be modified, changing the size of CB alters the device’s turn-on time and the magnitude of "clicks and pops". Increasing the value of CB reduces the magnitude of turn-on pops. However, this presents a tradeoff: as the size of CB increases, the turn-on time increases. There is a linear relationship between the size of CB and the turn-on time. Here are some typical turn-on times for various values of CB: Input Capacitor Value Selection Amplifying the lowest audio frequencies requires high value input coupling capacitor (Ci in Figure 1). A high value capacitor can be expensive and may compromise space efficiency in portable designs. In many cases, however, the speakers used in portable systems, whether internal or external, have little ability to reproduce signals below 150Hz. Applications using speakers with this limited frequency response reap little improvement by using large input capacitor. Besides effecting system cost and size, Ci has an affect on the LM4817’s click and pop performance. When the supply voltage is first applied, a transient (pop) is created as the charge on the input capacitor changes from zero to a quiescent state. The magnitude of the pop is directly proportional to the input capacitor’s size. Higher value capacitors need more time to reach a quiescent DC voltage (usually VDD/2) when charged with a fixed current. The amplifier’s output charges the input capacitor through the feedback resistor, Rf. Thus, pops can be minimized by selecting an input capacitor value that is no higher than necessary to meet the desired -3dB frequency. A shown in Figure 1, the input resistor (RI) and the input capacitor, CI produce a −3dB high pass filter cutoff frequency that is found using Equation (7). CB 20 ms 0.1µF 200 ms 0.22µF 440 ms 0.47µF 940 ms 1.0µF 2 Sec In order eliminate "clicks and pops", all capacitors must be discharged before turn-on. Rapidly switching VDD may not allow the capacitors to fully discharge, which may cause "clicks and pops". NO LOAD STABILITY The LM4817 may exhibit low level oscillation when the load resistance is greater than 10kΩ. This oscillation only occurs as the output signal swings near the supply voltages. Prevent this oscillation by connecting a 5kΩ between the output pins and ground. (7) As an example when using a speaker with a low frequency limit of 150Hz, CI, using Equation (4), is 0.063µF. The 1.0µF CI shown in Figure 1 allows the LM4817 to drive high efficiency, full range speaker whose response extends below 30Hz. Bypass Capacitor Value Selection Besides minimizing the input capacitor size, careful consideration should be paid to value of CB, the capacitor connected to the BYPASS pin. Since CB determines how fast www.national.com TON 0.01µF 14 FH = 20kHzx5 = 100kHz (Continued) As mentioned in the External Components section, Ri and Ci create a highpass filter that sets the amplifier’s lower bandpass frequency limit. Find the coupling capacitor’s value using Equation (14). AUDIO POWER AMPLIFIER DESIGN Audio Amplifier Design: Driving 1W into an 8Ω Load The following are the desired operational parameters: Power Output: Load Impedance: Input Level: Input Impedance: Bandwidth: (13) 1WRMS 8Ω (14) 1VRMS the result is 20kΩ 1/(2π*20kΩ*20Hz) = 0.398µF 100Hz−20 kHz ± 0.25 dB (15) Use a 0.39µF capacitor, the closest standard value. The product of the desired high frequency cutoff (100kHz in this example) and the differential gain, AVD, determines the upper passband response limit. With AVD = 3 and fH = 100kHz, the closed-loop gain bandwidth product (GBWP) is 300kHz. This is less than the LM4817’s 3.5MHz GBWP. With this margin, the amplifier can be used in designs that require more differential gain while avoiding performance-lrestricting bandwidth limitations. The design begins by specifying the minimum supply voltage necessary to obtain the specified output power. One way to find the minimum supply voltage is to use the Output Power vs Supply Voltage curve in the Typical Performance Characteristics section. Another way, using Equation (4), is to calculate the peak output voltage necessary to achieve the desired output power for a given load impedance. To account for the amplifier’s dropout voltage, two additional voltages, based on the Dropout Voltage vs Supply Voltage in the Typical Performance Characteristics curves, must be added to the result obtained by Equation (8). The result in Equation (9). LDO General Information Figure 2 shows the LM4817’s LDO functional block diagram. A 1.25V bandgap reference, an error amplifier and a PMOS pass transistor perform voltage regulation while being supported by shutdown, fault, and the usual Temperature and current protection circuitry The regulator’s topology is the classic type with negative feedback from the output to one of the inputs of the error amplifier. Feedback resistors R1 and R2 are either internal or external to the IC, depending on whether it is the fixed voltage version or the adjustable version. The negative feedback and high open loop gain of the error amplifier cause the two inputs of the error amplifier to be virtually equal in voltage. If the output voltage changes due to load changes, the error amplifier provides the appropriate drive to the pass transistor to maintain the error amplifier’s inputs as virtually equal. In short, the error amplifier keeps the output voltage constant in order to keep its inputs equal. (8) VDD ≥ (VOUTPEAK + (VODTOP + VODBOT)) (9) The Output Power vs Supply Voltage graph for an 8Ω load indicates a minimum supply voltage of 4.6V. This is easily met by the commonly used 5V supply voltage. The additional voltage creates the benefit of headroom, allowing the LM4817 to produce peak output power in excess of 1W without clipping or other audible distortion. The choice of supply voltage must also not create a situation that violates maximum power dissipation as explained above in the Power Dissipation section. After satisfying the LM4817’s power dissipation requirements, the minimum differential gain is found using Equation (10). (10) Thus, a minimum gain of 2.83 allows the LM4817’s to reach full output swing and maintain low noise and THD+N performance. For this example, let AVD = 3. The amplifier’s overall gain is set using the input (Ri) and feedback (Rf) resistors. With the desired input impedance set at 20kΩ, the feedback resistor is found using Equation (11). (11) Rf/Ri = AVD/2 The value of Rf is 30kΩ. The last step in this design example is setting the amplifier’s −3dB frequency bandwidth. To achieve the desired ± 0.25dB pass band magnitude variation limit, the low frequency response must extend to at least one−fifth the lower bandwidth limit and the high frequency response must extend to at least five times the upper bandwidth limit. The gain variation for both response limits is 0.17dB, well within the ± 0.25dB desired limit. The results are an (12) fL = 100Hz/5 = 20Hz and an 200781A0 FIGURE 2. LDO Functional Block Diagram Output Voltage Setting The output voltage is set according to the amount of negative feedback (Note that the pass transistor inverts the feedback signal). Figure 3 simplifies the LDO’s topology. This 15 www.national.com LM4817 Application Information LM4817 Application Information frequency noise filtering. Higher values and other types and of capacitor may be used, but their equivalent series resistance (ESR) should be maintained below 0.5Ω (Continued) type of regulator can be represented as an op amp configured as non-inverting amplifier and a fixed DC Voltage (VREF) for its input signal. The special characteristic of this op amp is its extra-large output transistor that only sources current. In terms of its non-inverting configuration, the output voltage equals VREF times the closed loop gain: Ceramic capacitor of the value required by the LDO are available in the following dielectric types: Z5U, Y5V, X5R and X7R. The Z5U and Y5V types exhibit a 50% or more drop in capacitance value as their temperature increases from 25˚C, an important consideration. The X5R generally maintain their capacitance value within ± 20%. The X7R type are desirable for their tighter tolerance of 10% over temperature. Ceramic capacitors pose a challenge because of their relatively low ESR. Like most other LDOs, the LDO relies on a zero in the frequency response to compensate against excessive phase shift in the regulator’s feedback loop. If the phase shift reaches 360˚ (i.e.; becomes positive), the regulator will oscillate. This compensation usually resides in the zero generated by the combination of the output capacitor with its equivalent series resistance (ESR). The zero is intended to cancel the effects of the pole generated by the load capacitance (CL) combined with the parallel combination of the load resistance (RL) and the output resistance (RO) of the regulator. The challenge posed by low ESR capacitors is that the zero it generates can be too high in frequency for the pole that it’s intended to compensate. The LM4817 overcomes this challenge by internally generating a strategically placed zero. Utilize the following equation for adjusting the output to a particular voltage: Choose R2 = 100k to optimize accuracy, power supply rejection, noise and power consumption. 200781B6 FIGURE 3. Regulator Topology Simplified Similarity in the output capabilities exists between op amps and linear regulators. Just as rail-to-rail output op amps allow their output voltage to approach the supply voltage, low dropout regulators (LDOs) allow their output voltage to operate close to the input voltage. Both achieve this by the configuration of their output transistors. Standard op amps and regulator outputs are at the source (or emitter) of the output transistor. Rail-to-rail op amp and LDO regulator outputs are at the drain (or collector) of the output transistor. This replaces the threshold (or diode drop) limitations on the output with the less restrictive source-to-drain (or VSAT) limitations. There is a trade-off, of course. The output impedance become significantly higher, thus providing a critically lower pole when combined with the capacitive load. That’s why rail-to-rail op amps are usually poor at driving capacitive loads and recommend a series output resistor when doing so. LDOs require the same series resistance except that the internal resistance of the output capacitor will usually suffice. Refer to the output capacitance section for more information. 200781B7 FIGURE 4. Simplified Model of Regulator Loop Gain Components Figure 4 shows a basic model for the linear regulator that helps describe what happens to the output signal as it is processed through its feedback loop; that is, describe its loop gain (LG). The LG includes two main transfer functions: the error amplifier and the load. The error amplifier provides voltage gain and a dominant pole, while the load provides a zero and a pole. The LG of the model in Figure 3 is described by the following equation: Output Capacitance The LDO is specifically designed to employ ceramic output capacitors as low as 2.2µF. Ceramic capacitors below 10µF offer significant cost and space savings, along with high www.national.com The first term of the above equation expresses the voltage gain (numerator) and a single pole role-off (denominator) of 16 Pin 6 directly connects to the high impedance output of the bandgap. The DC leakage of the CC capacitor should be considered; loading down the reference will reduce the output voltage. NPO and COG ceramic capacitors typically offer very low leakage. Polypropylene and polycarbonate film carbonate capacitor offer even lower leakage currents. CC does not affect the transient response; however, it does affect turn-on time. The smaller the CC value, the quicker the turn-on time. (Continued) the error amplifier. The second term expresses the zero (numerator) and pole (denominator) of the load in combination with the RO of the regulator. Figure 5 shows a Bode plot that represents a case where the zero contributed by the load is too high to cancel the effect of the pole contributed by the load and RO. The solid line illustrates the loop gain while the dashed line illustrates the corresponding phase shift. Notice that the phase shift at unity gain is a total 360˚ -the criteria for oscillation. 200781B8 FIGURE 5. Loop Gain Bode Plot Illustrating Inadequately High Zero for Stability Compensation The LDO generates an internal zero that makes up for the inadequately high zero of the low ESR ceramic output capacitor. This internally generated zero is strategically placed to provide positive phase shift near unity gain, thus providing a stable phase margin. No-Load Stability The LM4817 remains stable during no-load conditions, a necessary feature for CMOS RAM keep-alive applications. Input Capacitor The LM4817 requires a minimum input capacitance of about 1µF. The value may be increased indefinitely. The type is not critical to stability. However, instability may occur with bench set-ups where long supply leads are used, particularly at near dropout and high current conditions. This is attributed to the lead inductance coupling to the output through the gate oxide of the pass transistor; thus, forming a pseudo LCR network within the Loop-gain. A 10µF tantalum input capacitor remedies this non-situ condition; its larger ESR acts to dampen the pseudo LCR network. This may only be necessary for some bench setups. 1µF ceramic input capacitor are fine for most end-use applications. If a tantalum input capacitor is intended for the final application, it is important to consider their tendency to fail in short circuit mode, thus potentially damaging the part. Noise Bypass Capacitor The noise bypass capacitor (CC) significantly reduces the LDO’soutput noise. Connect the CC capacitor between pin 6 and ground. The optimum value for CC is 33nF. 17 www.national.com LM4817 Application Information LM4817 Application Information (Continued) Power Dissipation Power dissipation refers to the part’s ability to radiate heat away from the silicon, with packaging being a key factor. A reasonable analogy is the packaging a human being might wear, a jacket for example. A jacket keeps a person comfortable on a cold day, but not so comfortable on a hot day. It would be even worse if the person was exerting power (exercising). This is because the jacket has resistance to heat flow to the outside ambient air, like the IC package has a thermal resistance from its junctions to the ambient (θJA). θJA has a unit of temperature per power and can be used to calculate the IC’s junction temperature as follows: TJ = θJA (PD) + TA TJ is the junction temperature of the IC. θJA is the thermal resistance from the junction to the ambient air outside the package. PD is the power exerted by the IC, and TA is the ambient temperature. 200781B9 FIGURE 6. Power on Delayed Reset Application PD is calculated as follows: PD = IOUT (VIN -VO) θJA for the LM4817 package (MSOP-8) is 223˚C/W with no forced air flow, 182˚C/W with 225 linear feet per minute (LFPM) of air flow, 163˚C/W with 500 LFPM of air flow, and 149˚C/W with 900 LFPM of air flow. θJA can also be decreased (improved) by considering the layout of the PC board: heavy traces (particularly at VIN and the two VOUT pins), large planes, through-holes, etc. Improvements and absolute measurements of the θJA can be estimated by utilizing the thermal shutdown circuitry that is internal to the IC. The thermal shutdown turns off the pass transistor of the device when its junction temperature reaches 160˚C (Typical). The pass transistor doesn’t turn on again until the junction temperature drops about 10˚C (hysteresis). Using the thermal shutdown circuit to estimate , θJA can be done as follows: With a low input to output voltage differential, set the load current to 300mA. Increase the input voltage until the thermal shutdown begins to cycle on and off. Then slowly decrease VIN (100mV increments) until the part stays on. Record the resulting voltage differential (VD) and use it in the following equation: The delay time for the application of Figure 5 is set as follows: The application is set for a reset delay time of 8.8ms. Note that the comparator should have high impedance inputs so as to not load down the VREF at the CC pin of the LM4817. Shutdown The LM4817’s LDO goes into sleep mode when the SHDN pin is in a logic low condition. During this condition, the pass transistor, error amplifier, and bandgap are turned off, reducing the supply current to 1nA typical. The maximum guaranteed voltage for a logic low at the SHDN pin is 0.4V. A minimum guaranteed voltage of 2V at the SHDN pin will turn the LDO back on. The SHDN pin may be directly tied to VIN to keep the part on. The SHDN pin may exceed VIN but not the ABS MAX of 6.5V. Figure 6 shows an application that uses the SHDN pin. It detects when the battery is too low and disconnects the load by turning off the regulator. A micropower comparator (LMC7215) and reference (LM385) are combined with resistors to set the minimum battery voltage. At the minimum battery voltage, the comparator output goes low and tuns off the LDO and corresponding load. Hysteresis is added to the minimum battery threshold to prevent the battery’s recovery voltage from falsely indicating an above minimum condition. When the load is disconnected from the battery, it automatically increases in terminal voltage because of the reduced IR drop across its internal resistance. The Minimum battery detector of figure 6 has a low detection threshold (VLT) of 3.6V that corresponds to the minimum battery voltage. The upper threshold (VUT) is set for 4.6V in order to exceed the recovery voltage of the battery. Fault Detection The LDO provides a FAULT pin that goes low during out of regulation conditions like current limit and thermal shutdown, or when it approaches dropout. The latter monitors the inputto-output voltage differential and compares it against a threshold that is slightly above the dropout voltage. This threshold also tracks the dropout voltage as it varies with load current. Refer to Fault Detect vs. Load Current curve in the typical characteristics section. The FAULT pin requires a pull-up resistor since it is an open-drain output. This resistor should be large in value to reduce energy drain. A 100kΩ pull-up resistor works well for most applications. Figure 6 shows the LDO’s with delay added to the FAULT pin for the reset pin of a microprocessor. The output of the comparator stays low for a preset amount of time after the regulator comes out of a fault condition. www.national.com 18 This circuit board is easy to use. Apply 5V and ground to the board’s VDD and GND pads, respectively. Connect speakers between the board’s -OUTA and +OUTA and OUTB and +OUTB pads. Apply the stereo input signal to the input pins labeled "-INA" and "-INB." The stereo input signal’s ground references are connected to the respective input channel’s "GND" pin, adjacent to the input pins. (Continued) 200781C0 FIGURE 7. Minimum Battery Detector that Disconnects the Load Via the SHDN Pin of the LM4817 Resistor value for VUT and VLT are determined as follows: (The application of Figure 6 used a GT of 5µ mho) 200781D2 FIGURE 8. Recommended MH board layout: component-side silkscreen The above procedure assumes a rail-to-rail output comparator. Essentially, R2 is in parallel with R1 prior to reaching the lower threshold, then R2 becomes parallel with R3 for the upper threshold. Note that the application requires rail-to-rail input as well. The resistor values shown in Figure 7 are the closest practical to calculated values. Fast Start-up The LM4817’s LDO provides fast start-up time for better system efficiency. The start-up speed is maintained when using the optional noise bypass capacitor. An internal 500µA current source charges the capacitor until it reaches about 90% of its final value. 20078145 FIGURE 9. Recommended MHPC board layout: component-side layout RECOMMENDED PRINTED CIRCUIT BOARD LAYOUT Figures 8 through 10 show the recommended two-layer PC board layout that is optimized for the 28-pin MH-packaged LM4817 and associated components. These circuits are designed for use with an external 5V supply and 8Ω (or greater) speakers. 19 www.national.com LM4817 Application Information LM4817 Application Information (Continued) 20078148 FIGURE 10. Recommended MH board layout: bottom-side layout www.national.com 20 inches (millimeters) unless otherwise noted 28-Lead Molded PKG, TSSOP, JEDEC, 4.4mm BODY WIDTH Order Number LM4817MH NS Package Number MXA28A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. 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