9316/DM9316 Synchronous 4-Bit Counters General Description These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The 9316 is a 4-bit binary counter. The carry output is decoded by means of a NOR gate, thus preventing spikes during the normal counting mode of operation. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enables inputs and internal gating. This mode of operating eliminates the output counting spikes which are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable input. Low-to-high transitions at the load input are perfectly acceptable regardless of the logic levels on the clock or enable inputs. The clear function is asynchronous and a low level at the clear input sets of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both countenable inputs (P and T) must be high to count, and input T is fed-forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. Highto-low level transitions at the enable P or T inputs may occur regardless of the logic level in the clock. Features Y Y Y Y Y Y Y Y Internal look-ahead for fast counting Carry output for n-bit cascading Synchronous counting Load control line Diode-clamped inputs Typical clock frequency 35 MHz Pin-for-pin replacements popular 54/74 counters 5416A/7416A (binary) Alternate Military/Aerospace device (9316) is available. Contact a National Semiconductor Sales Office/Distributor for specifications. Connection Diagram Dual-In-Line Package TL/F/6606 – 1 Order Number 9316DMQB, 9316FMQB, DM9316J DM9316W or DM9316N See NS Package Number J16A, N16E or W16A C1995 National Semiconductor Corporation TL/F/6606 RRD-B30M105/Printed in U. S. A. 9316/DM9316 Synchronous 4-Bit Counters June 1989 Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 5.5V Operating Free Air Temperature Range b 55§ C to a 125§ C Military Commercial 0§ C to a 70§ C Storage Temperature Range b 65§ C to a 150§ C Recommended Operating Conditions Symbol VCC VIH Supply Voltage High Level Input Voltage VIL IOH IOL fCLK tW Low Level Input Voltage High Level Output Current Low Level Output Current Clock Frequency (Note 6) Pulse Width Clock (Note 6) Clear tSU Military Parameter Setup Time (Note 6) Min 4.5 2 Nom 5 Data tH TA Free Air Operating Temperature Min 4.75 2 Max 5.25 0.8 0.8 b 0.8 16 25 0 25 20 20 20 20 20 25 20 0 20 25 20 0 b 55 Units Nom 5 b 0.8 16 25 0 25 Enable P Load Clear Any Hold Time (Notes 1 & 6) Commercial Max 5.5 125 V V V mA mA MHz ns ns ns 0 70 §C Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL II IIH IIL IOS ICCH ICCL Parameter Conditions Input Clamp Voltage High Level Output Voltage Low Level Output Voltage Input Current @ Max Input Voltage High Level Input Current VCC e Min, II e b12 mA VCC e Min, IOH e Max VIL e Max, VIH e Min VCC e Min, IOL e Max VIH e Min, VIL e Max VCC e Max, VI e 5.5V Low Level Input Current VCC e Max VI e 0.4V VCC e Max VI e 2.4 V Short Circuit Output Current VCC e Max (Note 3) Supply Current with Outputs High VCC e Max (Note 4) Supply Current with Outputs Low VCC e Max (Note 5) Min Typ (Note 2) 2.4 3.4 Max b 1.5 Units V V 0.2 Clock 0.4 V 1 mA 80 Enable T Other Clock 80 40 b 3.2 mA Enable T Other MIL b 3.2 mA COM MIL b 1.6 b 20 b 57 b 18 b 57 59 85 COM MIL 59 63 94 91 COM 63 101 Note 1: The minimum HOLD time is as specified or as long as the CLOCK input takes to rise from 0.8V to 2V, whichever is longer. Note 2: All typicals are at VCC e 5V, TA e 25§ C. Note 3: Not more than one output should be shorted at a time. Note 4: ICCH is measured with the LOAD input high, then again with the LOAD input low, with all other inputs high and all outputs open. Note 5: ICCL is measured with the CLOCK input high, then again with the CLOCK input low, with all other inputs low and all outputs open. Note 6: TA e 25§ C and VCC e 5V. 2 mA mA mA Switching Characteristics at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load) Symbol Parameter From (Input) To (Output) RL e 400X, CL e 15 pF Min Units Max fMAX Maximum Clock Frequency tPLH Propagation Delay Time Low to High Level Output Clock to RC 25 27 ns tPHL Propagation Delay Time High to Low Level Output Clock to RC 24 ns tPLH Propagation Delay Time Low to High Level Output Clock to Q 20 ns tPHL Propagation Delay Time High to Low Level Output Clock to Q 23 ns tPLH Propagation Delay Time Low to High Level Output Clock to Q 21 ns tPHL Propagation Delay Time High to Low Level Output Clock to Q 25 ns tPLH Propagation Delay Time Low to High Level Output ENT to RC 15 ns tPHL Propagation Delay Time High to Low Level Output ENT to RC 16 ns tPHL Propagation Delay Time High to Low Level Output Clear to Q 36 ns 3 MHz Logic Diagram 9316 TL/F/6606 – 2 4 Timing Diagram 9316 Synchronous Binary Counters Typical Clear, Preset, Count and Inhibit Sequences TL/F/6606 – 3 Sequence: (1) Clear outputs to zero. (2) Preset to binary twelve. (3) Count to thirteen, fourteen, fifteen, zero, one, and two. (4) Inhibit 5 Parameter Measurement Information Switching Time Waveforms TL/F/6606 – 4 Note A: The input pulses are supplied by a generator having the following characteristics: PRR s 1 MHz, duty cycle s 50%, ZOUT & 50X, tr s 10 ns, tf s 10 ns. Vary PRR to measure fMAX. Note B: Outputs QD and carry are tested at tn a 16 for 9316/8316, where tn is the bit time when all outputs are low. Note C: VREF e 1.5V. 6 Parameter Measurement Information (Continued) Switching Time Waveforms TL/F/6606 – 5 Note A: The input pulses are supplied by generators having the following characteristics: PRR s 1 MHz, duty cycle s 50%, ZOUT & 50X, tr s 10 ns, tf s 10 ns. Note B: Enable P and Enable T setup times are measured at tn a 16 for 8316/9316. Note C: VREF e 1.5V. 7 8 Physical Dimensions inches (millimeters) 16-Lead Ceramic Dual-In-Line Package (J) Order Number 9316DMQB or DM9316J NS Package Number J16A 16-Lead Molded Dual-In-Line Package (N) Order Number DM9316N NS Package Number N16E 9 9316/DM9316 Synchronous 4-Bit Counters Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flat Package (W) Order Number 9316FMQB or DM9316W NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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