54LS160A/DM74LS160A, 54LS162A/DM74LS162A Synchronous Presettable BCD Decade Counters General Description Features The ’LS160 and ’LS162 are high speed synchronous decade counters operating in the BCD (8421) sequence. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The ’LS160 has an asynchronous Master Reset input that overrides all other inputs and forces the outputs LOW. The ’LS162 has a Synchronous Reset input that overrides counting and parallel loading and allows all outputs to be simultaneously reset on the rising edge of the clock. Y Y Y Y Synchronous counting and loading High speed synchronous expansion Typical count rate of 35 MHz Fully edge triggered Connection Diagram Dual-In-Line Package TL/F/10177 – 1 *MR for ’LS160 *SR for ’LS162 Order Number 54LS160ADMQB, 54LS160AFMQB, 54LS160ALMQB, 54LS162ADMQB, 54LS162AFMQB, 54LS162ALMQB, DM74LS160AM, DM74LS160AN, DM74LS162AM or DM74LS162AN See NS Package Number E20A, J16A, M16A, N16E or W16A Pin Names CEP CET CP MR (’160) SR (’162) P0 – P3 PE Q0 – Q3 TC Description Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input (Active Rising Edge) Asynchronous Master Reset Input (Active LOW) Synchronous Reset Input (Active LOW) Parallel Data Inputs Parallel Enable Input (Active LOW) Flip-Flop Outputs Terminal Count Output C1995 National Semiconductor Corporation TL/F/10177 Logic Symbol TL/F/10177 – 2 VCC e Pin 16 *MR for ’LS160 GND e Pin 8 *SR for ’LS162 RRD-B30M105/Printed in U. S. A. 54LS160A/DM74LS160A, 54LS162A/DM74LS162A Synchronous Presettable BCD Decade Counters May 1992 Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range b 55§ C to a 125§ C 54LS DM74LS 0§ C to a 70§ C Storage Temperature Range b 65§ C to a 150§ C Recommended Operating Conditions Symbol 54LS160A/162A Parameter DM74LS160A/162A Units Min Nom Max Min Nom Max 4.5 5 5.5 4.75 5 5.25 VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage IOH High Level Output Current IOL Low Level Output Current TA Free Air Operating Temperature ts(H) ts(L) Setup Time, HIGH or LOW Pn to CP 20 20 20 20 ns th(H) th(L) Hold Time, HIGH or LOW Pn to CP 0.0 0.0 0.0 0.0 ns ts(H) ts(L) Setup Time, HIGH or LOW PE to CP 20 20 20 20 ns th(H) th(L) Hold Time, HIGH or LOW PE to CP 0 0 0 0 ns ts(H) ts(L) Setup Time, HIGH or LOW CEP, CET or SR to CP 20 20 20 20 ns th(H) th(L) Hold Time, HIGH or LOW CEP, CET or SR to CP 0 0 0 0 ns tw(H) tw(L) CP Pulse Width, HIGH or LOW 15 25 15 25 ns tw(L) MR Pulse Width LOW (’160) 15 15 ns trec Recovery Time MR to CP (’160) 20 20 ns 2 2 V 0.7 0.8 V b 0.4 b 0.4 mA 8 mA 70 §C 4 b 55 V 125 0 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions Min Typ (Note 1) Max Units b 1.5 V VI Input Clamp Voltage VCC e Min, II e b18 mA VOH High Level Output Voltage VCC e Min, IOH e Max, VIL e Max 54LS 2.5 DM74 2.7 Low Level Output Voltage VCC e Min, IOL e Max, VIH e Min 54LS 0.4 DM74 0.5 IOL e 4 mA, VCC e Min DM74 0.4 VOL Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. 2 V V Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) (Continued) Symbol II Parameter Input Current @ Conditions Max VCC e Max, VI e 7V Input Voltage IIH High Level Input Current IIL Min Low Level Input Current Typ (Note 1) Other 0.1 PE, CET Inputs 0.2 Other 20 PE, CET Inputs 40 VCC e Max, VI e 2.7V VCC e Max, VI e 0.4V Inputs Units mA mA 54LS b 0.4 DM74 b 1.6 PE, CET Inputs IOS Max mA b 0.8 54LS b 20 b 100 DM74 b 20 b 100 mA Short Circuit Output Current VCC e Max (Note 2) ICCH Supply Current with Outputs HIGH VCC e Max, PE e GND CP e L, Other Inputs e 4.5V 31 mA ICCL Supply Current with Outputs LOW VCC e Max, VIN e GND CP e L 31 mA mA Switching Characteristics VCC e a 5.0V, TA e a 25§ C Symbol RL e 2 kX CL e 15 pF Parameter Min Units Max fmax Maximum Clock Frequency tPLH tPHL Propagation Delay CP to TC 25 25 21 MHz ns tPLH tPHL Propagation Delay CP to Qn 24 27 ns tPLH tPHL Propagation Delay CET to TC 14 23 ns tPHL Propagation Delay MR to Qn (’160) 28 ns Functional Description Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. A LOW signal on SR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR (’LS160) or SR (’LS162) HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting. The ’LS160A and ’LS162A use D-type edge-triggered flipflops and changing the SR, PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. The ’LS160 and ’LS162 count modulo-10 in the BCD (8421) sequence. From state 9 (HLLH) they increment to state 0 (LLLL). The ’161 and ’163 count modulo-16 binary sequence. From state 15 (HHHH) they increment to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs (except due to Master Reset of the ’LS160) occur as a result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence: asynchronous reset (’LS160), synchronous reset (’LS162), parallel load, count-up and hold. Five control inputsÐMaster Reset (MR, ’LS160), Synchronous Reset (SR, ’LS162), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET)Ðdetermine the mode of operation, as shown in the 3 Functional Description (Continued) The Terminal Count (TC) output is HIGH when CET is HIGH and the counter is in its maximum count state (9 for the decade counters, 15 for the binary counters). To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. These two schemes are shown in the 9310 data sheet. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, counters or registers. In the decade counters of the ’LS160, ’LS162, the TC output is fully decoded and can only be HIGH in state 9. LOGIC EQUATIONS: Count Enable e CEP # CET # PE Mode Select Table *SR PE CET CEP L H H H H X L H H H X X H L X X X H X L *For the ’LS162 H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial TC e Q0 # Q1 # Q2 # Q3 # CET State Diagrams ’LS160, ’LS162 TL/F/10177 – 5 4 Action on the Rising Clock Edge (L ) RESET (Clear) LOAD (Pn x Qn) COUNT (Increment) NO CHANGE (Hold) NO CHANGE (Hold) Logic Diagrams ’LS160 TL/F/10177 – 3 ’LS162 TL/F/10177 – 4 5 Physical Dimensions inches (millimeters) Ceramic Leadless Chip Carrier Package (E) Order Number 54LS160ALMQB or 54LS162ALMQB NS Package Number E20A Ceramic Dual-In-Line Package (J) Order Number 54LS160ADMQB or 54LS162ADMQB NS Package Number J16A 6 Physical Dimensions inches (millimeters) (Continued) 16-Lead Small Outline Molded Package (M) Order Number DM74LS160AM DM74LS162AM NS Package Number M16A 16-Lead Molded Dual-In-Line Package (N) Order Number DM74LS160AN or DM74LS162AN NS Package Number N16E 7 54LS160A/DM74LS160A, 54LS162A/DM74LS162A Synchronous Presettable BCD Decade Counters Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flat Package (W) Order Number 54LS160AFMQB or 54LS162AFMQB NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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