NSC PC87306

November 1995
PC87306 SuperI/O TM Enhanced Sidewinder Lite
Floppy Disk Controller, Keyboard Controller,
Real-Time Clock, Dual UARTs, Infrared Interface,
IEEE 1284 Parallel Port, and IDE Interface
General Description
Features
The PC87306 is a single chip solution incorporating a Keyboard and PS/2É Mouse Controller (KBC), Real Time Clock
(RTC) and most commonly used I/O peripherals in ISA,
EISA and MicroChannelÉ based computers. In addition to
the KBC and RTC, a Floppy Disk Controller (FDC), two full
featured UARTs, an IEEE 1284 compatible parallel port and
all the necessary control logic for an IDE interface provides
support for most commonly used I/O peripherals. Standard
PC-ATÉ address decoding for all the peripherals, a set of
configuration registers, and two user selectable chip selects
are also implemented in this highly integrated member of
the SuperI/O family. The advanced features and high integration of the PC87306 result in several benefits for low
cost, high performance systems. Printed circuit board space
savings, fewer components on the motherboard and compatibility with the latest industry standard peripherals are
only a few of the benefits of using a PC87306.
The KBC is fully software compatible with the 8042AH microcontroller. It contains system timing, control logic, custom ROM program memory, RAM data memory and 18 programmable I/O lines necessary to implement dedicated
control functions. It is an efficient controller which uses predominantly single byte instructions with support for binary and
BCD arithmetic and extensive bit handling capabilities.
(Continued)
Y
Y
Floppy Disk Controller:
Ð Software compatible with the DP8477, the 765A and
the N82077
Ð 16-byte FIFO (disabled by default)
Ð Burst and Non-Burst modes
Ð Perpendicular recording drive support
Ð High performance internal analog data separator
(no external filter components required)
Ð Low power CMOS with power-down mode
Ð Automatic media-sense support with full IBM TDR
(Tape Drive Register) implementation for PC-AT and
PS/2 floppy drive types
Keyboard Controller:
Ð 8042AH and PC87911 software compatible
Ð 8-bit Microcomputer with 2 kBytes custom ROM and
256 Bytes data RAM
Ð Asynchronous access to two data registers and one
status register during normal operation
Ð Dedicated open drain outputs for keyboard controller
application
Ð Supports both interrupt and polling
Ð 10 programmable I/O pins
Ð 4 dedicated open-drain bidirectional pins
Ð 8-bit Timer/Counter
Ð Binary and BCD arithmetic
(Continued)
Block Diagram
TL/C/12379 – 1
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
SuperI/OTM is a trademark of National Semiconductor Corporation.
MicroChannelÉ, PC-ATÉ and PS/2É are registered trademarks of International Business Machines Corporation.
C1995 National Semiconductor Corporation
TL/C/12379
RRD-B30M115/Printed in U. S. A.
PC87306 SuperI/O Enhanced Sidewinder Lite Floppy Disk Controller, Keyboard Controller,
Real-Time Clock, Dual UARTs, Infrared Interface, IEEE 1284 Parallel Port, and IDE Interface
PRELIMINARY
General Description (Continued)
Features (Continued)
The RTC is a low-power design that provides a time-of-day
clock, a 100-year calendar, several alarm features and 242
bytes of general purpose RAM. An external battery is used
to maintain the time and contents of the general purpose
RAM, when power is removed from the PC87306. The
PC87306 RTC is compatible with the DS1287 and
MC146818 RTC devices.
The PC87306 FDC uses a high performance analog data
separator eliminating need for any external filter components. The FDC is fully compatible with the PC8477 and
incorporates a superset of DP8473, NEC mPD765 and
N82077 floppy disk controller function. All popular 5.25×
and 3.5× floppy drives, including 2.88 MB 3.5× floppy drive,
are supported. Full TDR support for PC-AT and PS/2 floppy
drive types is also provided.
The two UARTs are fully NS16450 and NS16550 compatible.
The parallel port is fully IEEE 1284 level 2 compatible. The
SPP (Standard Parallel Port) is fully compatible with ISA,
EISA and MicroChannel parallel ports. In addition to the
SPP, EPP (Enhanced Parallel Port) and ECP (Extended Capabilities Port) modes are supported by the parallel port.
All IDE control signals with DMA support, including support
for Type F DMA are provided by the PC87306. Only external
signal buffers are required to implement a complete IDE
interface.
A set of fourteen configuration registers are provided to
control various functions of the PC87306. These registers
are accessed using two 8-bit wide index and data registers.
The ISA I/O address of the register pair can be relocated
using a power-up strapping option.
Two general purpose user programmable chip selects are
available. These chip selects can be used to decode game
port addresses.
Y
Y
Y
Y
Y
Y
Y
Y
2
Real-Time Clock:
Ð DS1287, MC146818 and PC87911 compatible
Ð 242 Bytes battery backed-up CMOS RAM in two
banks
Ð Selective lock mechanism locks any half of the RTC
RAM
Ð Calendar in days, day of the week, months and
years with automatic leap-year adjustment
Ð Time of day in seconds, minutes and hours:
Ð12 or 24 hour format
Ð Optional daylight savings adjustment
Ð BCD or binary format for time keeping
Ð Three individually maskable interrupt event flags:
ÐPeriodic rates from 122 ms to 500 ms
ÐTime-of-day alarm once per second to once per
day
Ð Separate battery pin, 2.4V operation
Ð 2 mA typical power consumption
Ð Double buffer time registers
UARTs:
Ð Software compatible with the PC16550A and
NS16450
Ð IrDA Infrared, and HP SIR Interface using UART2
with dedicated pins
Parallel Port:
Ð EPP, ECP compatible with ECP level 2 support
Ð Bi-directional data transfer under software or
hardware control
Ð Includes protection circuit to prevent damage to the
parallel port when a connected printer is powered up
or is operated at a higher voltage
IDE Control Logic:
Ð All IDE control signals, with DMA and support for
Type F DMA. Only external signal buffers are
required to implement the full IDE interface
General Purpose Pins:
Ð Separate pins for two user programmable chip select
decoders provide ability to control a game port
Ð 16 additional general purpose I/O ports
Address Decoder:
Ð Provides selection of all primary and secondary ISA
addresses including COM1 – 4
Plug and Play:
Ð Flexible IRQs and DMAs to meet the Plug and Play
requirements of Microsoft’s PC ’95 Hardware Design
Guide
Ð Multi-programmable parallel port base address
General:
Ð ISA, EISA and MicroChannel compatible architecture
Ð Low power CMOS technology
Ð Ability to stop clocks to all modules
Ð The PC87323, which includes RAM KBC, can be
used as a development platform for KBC code for
the PC87306
Ð Reduced pin leakage current
Ð Special configuration register for power-down
Ð Disable bit for RTC
Ð 160-pin PQFP package
Table of Contents
3.0 FDC REGISTER DESCRIPTION (Continued)
1.0 PIN DESCRIPTION
3.2.3 Status Register 2 (ST2)
2.0 CONFIGURATION REGISTERS
3.2.4 Status Register 3 (ST3)
2.1 Overview
4.0 FDC COMMAND SET DESCRIPTION
2.2 Software Configuration
4.1 Command Descriptions
2.3 Hardware Configuration
4.1.1 Configure Command
4.1.2 Dumpreg Command
4.1.3 Format Track Command
4.1.4 Invalid Command
4.1.5 Lock Command
4.1.6 Mode Command
4.1.7 NSC Command
4.1.8 Perpendicular Mode Command
4.1.9 Read Data Command
4.1.10 Read Deleted Data Command
4.1.11 Read ID Command
4.1.12 Read A Track Command
4.1.13 Recalibrate Command
4.1.14 Relative Seek Command
4.1.15 Scan Commands
4.1.16 Seek Command
4.1.17 Sense Drive Status Command
4.1.18 Sense Interrupt Command
4.1.19 Set Track Command
4.1.20 Specify Command
4.1.21 Verify Command
4.1.22 Version Command
4.1.23 Write Data Command
4.1.24 Write Deleted Data Command
2.4 Index and Data Registers
2.5 Base Configuration Registers
2.5.1
2.5.2
2.5.3
2.5.4
2.5.5
2.5.6
2.5.7
2.5.8
Function Enable Register
Function Address Register
Power and Test Register
Function Control Register
Printer Control Register
KBC and RTC Control Register
Power Management Control Register
Tape, UARTs and Parallel Port Configuration
Register
2.5.9 SuperI/O Identification Register
2.5.10 Advanced SuperI/O Configuration Register
2.5.11 Chip Select 0 Low Address
2.5.12 Chip Select 0 High Address
2.5.13 Chip Select 0 Configuration Register
2.5.14
2.5.15
2.5.16
2.5.17
2.5.18
2.5.19
2.5.20
2.5.21
2.5.22
2.5.23
Chip Select 1 Low Address
Chip Select 1 High Address
Chip Select 1 Configuration Register
InfraRed Configuration Register
General Purpose I/O Port Base Address
Configuration Register
SuperI/O Configuration Register 0
SuperI/O Configuration Register 1
LPT Base Address Register
Plug and Play Configuration 0 Register
Plug and Play Configuration 1 Register
4.2 Command Set Summary
4.3 Mnemonic Definitions for FDC Commands
5.0 FDC FUNCTIONAL DESCRIPTION
2.6 Power-Down Options
5.1 Microprocessor Interface
2.7 Power-Up Procedure and Considerations
5.2 Modes of Operation
2.7.1 UART Power-Up
2.7.2 FDC Power-Up
5.3 Controller Phases
5.3.1 Command Phase
5.3.2 Execution Phase
5.3.2.1 DMA ModeÐFIFO Disabled
5.3.2.2 DMA ModeÐFIFO Enabled
5.3.2.3 Interrupt ModeÐFIFO Disabled
5.3.2.4 Interrupt ModeÐFIFO Enabled
5.3.2.5 Software Polling
3.0 FDC REGISTER DESCRIPTION
3.1 FDC Control Registers
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
3.1.7
3.1.8
3.1.9
Status Register A (SRA) Read Only
Status Register B (SRB) Read Only
Digital Output Register (DOR) Read/Write
Tape Drive Register (TDR) Read/Write
Main Status Register (MSR) Read Only
Data Rate Select Register (DSR) Write Only
Data Register (FIFO) Read/Write
Digital Input Register (DIR) Read Only
Configuration Control Register (CCR)
Write Only
5.3.3 Result Phase
5.3.4 Idle Phase
5.3.5 Drive Polling Phase
5.4 Data Separator
5.5 Crystal Oscillator
5.6 Perpendicular Recording Mode
3.2 Result Phase Status Registers
5.7 Data Rate Selection
3.2.1 Status Register 0 (ST0)
3.2.2 Status Register 1 (ST1)
5.8 Write Precompensation
3
Table of Contents (Continued)
5.0 FDC FUNCTIONAL DESCRIPTION (Continued)
10.0 KEYBOARD CONTROLLER AND REAL-TIME
CLOCK (Continued)
5.9 FDC Low Power Mode Logic
10.1.6 Interrupts
10.1.7 Oscillator and Instruction Timing
5.10 Reset Operation
6.0 SERIAL PORTS
10.2 Real-Time Clock Function
6.1 Serial Port Registers
10.2.1
10.2.2
10.2.3
10.2.4
10.2.5
10.2.6
10.2.7
Memory Map
Bus Interface
Time Generation
Time Keeping
RAM
Power Management
System Bus Lock Out and Power-Up
Detection
10.2.8 Oscillator
10.2.9 Interrupt Handling
10.2.10 Control Registers
6.2 Line Control Register (LCR) Read/Write
6.3 Programmable Baud Rate Generator
6.4 Line Status Register (LSR)
6.5 FIFO Control Register (FCR)
6.6 Interrupt Identification Register (IIR)
6.7 Interrupt Enable Register (IER)
6.8 MODEM Control Register (MCR)
6.9 MODEM Status Register (MSR)
6.10 Scratchpad Register (SCR)
7.0 SERIAL INFRARED WIRELESS COMMUNICATION
PORT
11.0 GENERAL PURPOSE INPUT AND OUTPUT (GPIO)
PORTS
8.0 PARALLEL PORT
12.0 ELECTRICAL CHARACTERISTICS
8.1 Introduction
12.1 DC Electrical Characteristics
8.2 Data Register (DTR)
12.1.1 Microprocessor, Parallel Port, and
IDE Interface Pins
12.1.2 Disk Interface Pins
12.1.3 Oscillator Pin
12.1.4 Parallel Port Pins
12.1.5 GPIO Pins
12.1.6 Keyboard Controller and Real-Time Clock
Pins
8.3 Status Register (STR)
8.4 Control Register (CTR)
8.5 Enhanced Parallel Port Operation
8.6 Extended Capabilities Parallel Port (ECP)
8.6.1 Introduction
8.6.2 Software Operation
8.7 Register Definitions
12.2 AC Electrical Characteristics
8.8 Software Controlled Data Transfer
12.2.1
12.2.2
12.2.3
12.2.4
12.2.5
12.2.6
12.2.7
12.2.8
8.9 Automatic Data Transfer
8.9.1
8.9.2
8.9.3
8.9.4
Forward Direction
ECP Forward Write Cycle
Backward Direction
ECP Backward Read Cycle
8.10 FIFO Test Access
8.11 Configuration Registers Access
8.12 Interrupt Generation
9.0 INTEGRATED DEVICE ELECTRONICS INTERFACE
(IDE)
12.2.9 Reset Timing
12.2.10 FDC Write Data Timing
12.2.11 FDC Read Data Timing
12.2.12 Drive Control Timing
12.2.13 IDE Timing
12.2.14 Parallel Port Timing
12.2.15 Enhanced Parallel Port Timing
12.2.16 Extended Capabilities Port Timing
12.2.16.1 Forward
12.2.16.2 Backward
9.1 Introduction
9.2 IDE Signals
10.0 KEYBOARD CONTROLLER AND REAL-TIME
CLOCK
10.1 PC87306 KBC Function
10.1.1
10.1.2
10.1.3
10.1.4
10.1.5
AC Test Conditions
Clock Timing
Microprocessor Interface Timing
Baud Out Timing
Transmitter Timing
Receiver Timing
MODEM Control Timing
DMA Timing
12.2.8.1 FDC
12.2.8.2 ECP
Host System Interface
Program Memory
Data Memory and Registers
I/O Interface
Timer/Counter
12.2.17 GPIO Write Timing
12.2.18 RTC
12.2.19 Programmable Chip Select Timing
4
List of Figures
FIGURE 1-1
Pins Which Utilize the Strap Function during Reset
FIGURE 1-2
Multi-Function Pins
FIGURE 2-1
FIGURE 2-2
FIGURE 3-1
FIGURE 4-1
FIGURE 4-2
FIGURE 5-1
FIGURE 5-2
FIGURE 5-3
FIGURE 5-4
FIGURE 6-1
FIGURE 6-2
FIGURE 7-1
FIGURE 8-1
FIGURE 8-2
FIGURE 8-3
FIGURE 8-4
FIGURE 8-5
FIGURE 8-6
FIGURE 8-7
FIGURE 9-1
FIGURE 10-1
FIGURE 10-2
FIGURE 10-3
FIGURE 10-4
FIGURE 10-5
FIGURE 10-7
FIGURE 10-6
FIGURE 10-8
FIGURE 10-9
FIGURE 10-10
FIGURE 10-11
FIGURE 10-12
FIGURE 10-13
FIGURE 10-14
FIGURE 10-15
FIGURE 10-16
FIGURE 11-1
FIGURE 12-1
FIGURE 12-2
FIGURE 12-3
FIGURE 12-4
FIGURE 12-5
FIGURE 12-6
FIGURE 12-7
FIGURE 12-8
FIGURE 12-9
FIGURE 12-10
FIGURE 12-11
FIGURE 12-12
FIGURE 12-13
FIGURE 12-14
PC87306 Configuration Registers
PC87306 Four Floppy Drive Circuit
FDC Functional Block Diagram
FDC Command Structure
IBM, Perpendicular, and ISO Formats Supported by the Format Command
FDC Data Separator Block Diagram
PC87306 Dynamic Window Margin Performance
Read Data AlgorithmÐState Diagram
Perpendicular Recording Drive R/W Head and Pre-Erase Head
PC87306 Composite Serial Data
Receiver FIFO Trigger Level
UART2 Serial and IR Interface Block Diagram
EPP 1.7 Address Write
EPP 1.7 Address Read
EPP Write with ZWS
EPP 1.9 Address Write
EPP 1.9 Address Read
ECP Forward Write Cycle
ECP Backward Read Cycle
IDE Interface Signal Equations (Non-DMA)
Keyboard Controller Functional Block Diagram
Keyboard Controller to Host System Interface
Status Register
Fast IRQ Latching and Clearing
Keyboard Controller Data Memory Map
PSW Register Bits
Keyboard Controller Stack Organization
Active Pull-Up I/O Port Structure
Using Port Pins as Inputs
Timing Generation and Timer Circuit
External Clock Connection
Instruction Cycle Timing
Oscillator Internal and External Circuitry
Interrupt/Status Timing
Typical Battery Configuration
Typical Battery Current during Battery Backed Mode
General Purpose I/O (GPIO) Ports
Clock Timing
Microprocessor Read Timing
Microprocessor Write Timing
Read after Write Operation to All Registers and RAM Timing
Baud Out Timing
Transmitter Timing
Receiver Timing
FIFO Mode Receiver Timing
Timeout Receiver Timing
MODEM Control Timing
FDC DMA Timing
ECP DMA Timing
Reset Timing
Write Data Timing
5
List of Figures (Continued)
FIGURE 12-15
Read Data Timing
FIGURE 12-16
Drive Control Timing
FIGURE 12-17
FIGURE 12-18
FIGURE 12-19
FIGURE 12-20
FIGURE 12-21
FIGURE 12-22
FIGURE 12-23
FIGURE 12-24
FIGURE 12-25
FIGURE 12-26
FIGURE 12-27
IDE Timing
Compatible Mode Parallel Port Interrupt Timing
Extended Mode Parallel Port Interrupt Timing
Typical Parallel Port Data Exchange
Enhanced Parallel Port Timing
ECP Parallel Port Forward Timing Diagram
ECP Parallel Port Backward Timing Diagram
GPIO Write Timing
IRQ Release Delay
MR Timing
Chip Select Timing
List of Tables
TABLE 1-1
TABLE 2-1
TABLE 2-2
TABLE 2-3
TABLE 2-4
TABLE 2-5
TABLE 2-6
TABLE 2-7
TABLE 2-8
TABLE 2-9
TABLE 2-10
TABLE 2-11
TABLE 3-1
TABLE 3-2
TABLE 3-3
TABLE 3-4
TABLE 3-5
TABLE 3-6
TABLE 3-7
TABLE 3-8
TABLE 4-1
TABLE 4-2
TABLE 4-3
TABLE 4-4
TABLE 4-5
TABLE 4-6
TABLE 4-7
TABLE 4-8
TABLE 4-9
TABLE 4-10
TABLE 4-11
TABLE 4-12
TABLE 4-13
TABLE 4-14
TABLE 4-15
TABLE 4-16
TABLE 4-17
Pin Descriptions (Alphabetical)
Default Configurations Controlled by Hardware on Reset
Index and Data Register Optional Locations
Encoded Drive and Motor Pin Information (FER 4 e 1)
Primary and Secondary Drive Address Selection
Parallel Port Addresses
COM Port Selection for UART1
COM Port Selection for UART2
Address Selection for COM3 and COM4
TRI-STATE Conditions of IRQ5 and IRQ7
TRI-STATE Conditions of IRQ3 and IRQ4
Parallel Port Mode
Register Description and Addresses
Drive Enable Values
TDR Operation Modes
Media ID Bits Functions
Tape Drive Assignment Values
Write Precompensation Delays
Default Precompensation Delays
Data Rate Select Encoding
Typical Format GAP3 Length Values Based on Drive Data Rate
Typical Format GAP3 Length Values Based on PC Compatible Diskette Media
DENSEL Default Encoding
DENSEL Encoding
Head Settle Time Calculation
Effect of Drive Mode and Data Rate on Format and Write Commands
Effect of GAP and WG on Format and Write Commands
Sector Size Selection
SK Effect on the Read Data Command
Result Phase Termination Values with No Error
SK Effect on the Read Deleted Data Command
Maximum Recalibrate
Scan Command Termination Values
Status Register 0 Termination Codes
Set Track Register Address
Step Rate Time (SRT) Values
Motor Off Time (MFT) Values
6
List of Tables (Continued)
TABLE 4-18
Motor On Time (MNT) Values
TABLE 4-19
Verify Command Result Phase
TABLE 6-1
TABLE 6-2
TABLE 6-3
TABLE 6-4
TABLE 6-5
TABLE 8-1
TABLE 8-2
TABLE 8-3
TABLE 8-4
TABLE 8-5
TABLE 8-6
TABLE 8-7
TABLE 9-1
TABLE 10-1
TABLE 10-2
TABLE 12-1
TABLE 12-2
PC87306 UART
PC87306 Register Summary for an Individual UART Channel
PC87306 UART Reset Configuration
PC87306 UART Divisors, Baud Rates and Clock Frequencies
PC87306 Interrupt Control Functions
Parallel Interface
Standard Parallel Port
SPP Data Register Read and Write Modes
Parallel Port Reset States
EPP Register Addresses
Parallel Port Pin Out
ECP Registers
IDE Registers and Their ISA Addresses
Summary of System Interface Operations
RTC Memory Map
Nominal tICP, tDRP Values
Minimum tWDW Values
7
Basic Configuration
TL/C/12379 – 2
8
Connection Diagram
Plastic Quad Flatpak
TL/C/12379 – 3
Note: Do not connect pins marked Reserved.
Order Number PC87306VUL
See NS Package Number VUL160A
9
1.0 Pin Description
TABLE 1-1. Pin Descriptions (Alphabetical)
Symbol
Pin
I/O
61 – 59, 56–46,
12 – 11
I
Address. These address lines from the microprocessor determine which internal register is
accessed. A0–A10 are don’t cares during an DMA transfer. A10 is used only during ECP
operations.
ACK
127
I
Parallel Port Acknowledge. This input is pulsed low by a connected printer to indicate that it
has received data from the parallel port. This pin has a nominal 25 kX pull-up resistor
attached to it. (See DR1 and Table 7-5 for further information.)
AFD
119
I/O
Parallel Port Automatic Feed. When this signal is low the printer should automatically line
feed after each line is printed. This pin is in a TRI-STATEÉ condition 10 ns after a 0 is loaded
into the corresponding Control Register bit. The system should pull this pin high using a 4.7
kX resistor. (See DSTRB and Table 8-5 for further information.)
AEN
45
I
Address Enable. This input disables function selection via A15 – A0 when it is high. Access
during DMA transfer is NOT affected by this pin.
ASTRB
123
O
Address Strobe. This signal is used in Enhanced Parallel Port (EPP) mode as an address
strobe. It is active low. (See SLIN and Table 8-5 for further information.)
BADDR0,1
109, 108
I
Base Address. These CMOS inputs are sensed during reset to determine one of four base
addresses from which the Index and Data Registers are offset (see Table 2-2). An internal
pull-down resistor of 30 kX is present on this pin. Use a 10 kX resistor to pull this pin to VDD.
(See RTS1, SOUT1, and BOUT1 for further information.)
BOUT1,2
108, 98
O
BAUD Output. This multi-function pin provides the associated serial channel Baud Rate
generator output signal when test mode is selected in the Power and Test Configuration
Register and the DLAB bit (LCR7) is set. After a Master Reset, this pin provides the Serial
Output (SOUT) function. (See SOUT and BADDR1 for further information.)
126
I
Parallel Port Busy. This pin is set high by a connected printer when it cannot accept another
character. It has a nominal 25 kX pull-down resistor attached to it. (See WAIT and Table 8-5
for further information.)
84, 106
I
Configuration on Power-Up. These CMOS inputs select 1 of 4 default configurations in
which the PC87306 powers-up (see Table 2-1). They are provided with CMOS input buffers.
An internal pull-down resistor of 30 kX is present on each pin. Use a 10 kX resistor to pull
these pins to VDD.
CS0, 1
6, 23
O
Programmable Chip Select. CS0, 1 are programmable chip select and/or latch enable and/
or output enable signals that can be used for a game port, I/O port expander or other add-on
peripheral. The decoded address and the assertion conditions are configured via the
PC87306 configuration registers, 0Ah – 0Dh and 10h – 11h.
CTS1,2
107, 97
I
Clear to Send. When low, this indicates that the MODEM or data set is ready to exchange
data. The CTS signal is a MODEM status input whose condition the CPU can test by reading
bit 4 (CTS) of the MODEM Status Register (MSR) for the appropriate serial channel. Bit 4 is
the complement of the CTS signal. Bit 0 (DCTS) of the MSR indicates whether the CTS input
has changed state since the previous reading of the MSR. CTS has no effect on the
transmitter.
33 – 39, 42
I/O
DCD1,2
112, 104
I
DENSEL
77
O
A0 – A15
BUSY
CFG0, 1
Function
Note: Whenever the DCTS bit of the MSR is set an interrupt is generated if MODEM Status interrupts are enabled.
D7 – 0
Data. Bi-directional data lines to the microprocessor. D0 is the LSB and D7 is the MSB.
These signals all have 24 mA (sink) buffered outputs.
UARTs Data Carrier Detect. When low, this signal indicates that the MODEM or data set
has detected the data carrier. The DCD signal is a MODEM status input whose condition the
CPU can test by reading bit 7 (DCD) of the MODEM Status Register (MSR) for the
appropriate serial channel. Bit 7 is the complement of the DCD signal. Bit 3 (DDCD) of the
MSR indicates whether the DCD input has changed state since the previous reading of the
MSR.
Note: Whenever the DDCD bit of the MSR is set, an interrupt is generated if MODEM Status interrupts are enabled.
FDC Density Select. Indicates that a high FDC density data rate (500 kbps or 1 Mbps) or a
low density data rate (250 kbps or 300 kbps) is selected. DENSEL’s polarity is controlled by
bit 6 of the ASC register.
10
1.0 Pin Description (Continued)
TABLE 1-1. Pin Descriptions (Alphabetical) (Continued)
Symbol
Pin
I/O
Function
69
O
FDC Direction. This output determines the direction of the floppy disk drive (FDD) head
movement (active e step in, inactive e step out) during a seek operation. During reads or writes,
DIR is inactive.
DR0, 1
73, 74
O
FDC Drive Select 0, 1. These are the decoded Drive Select outputs that are controlled by the
Digital Output Register bits D0, D1. The Drive Select outputs are gated with DOR bits 4 – 7. These
are active low outputs. They are encoded with information to control four FDDs when bit 4 of the
Function Enable Register (FER) is set. (See MTR0, 1 for more information.)
DRATE0, 1
82, 81
O
FDC Data Rate 0, 1. These outputs reflect the currently selected FDC data rate (bits 0 and 1 in
the Configuration Control Register (CCR) or the Data Rate Select Register (DSR), whichever was
written to last). These pins are totem-pole buffered outputs (6 mA sink, 6 mA source).
DSKCHG
71
I
FDC Disk Change. This input indicates if the drive door has been opened. The state of this pin is
available from the Digital Input register. This pin can also be configured as the Read Gate
(RGATE) data separator diagnostic input via the Mode command (see Section 4.2.6).
DSR1, 2
111, 103
I
UARTs Data Set Ready. When low, this signal indicates that the data set or MODEM is ready to
establish a communications link. The DSR signal is a MODEM status input whose condition the
CPU can test by reading bit 5 (DSR) of the MODEM Status Register (MSR) for the appropriate
channel. Bit 5 is the complement of the DSR signal. Bit 1 (DDSR) of the MSR indicates whether
the DSR input has changed state since the previous reading of the MSR.
DSTRB
119
O
Data Strobe. This signal is used in EPP mode as a data strobe. It is active low. (See AFD and
Table 8-5 for further information.)
DTR1, 2
106, 96
O
UARTs Data Terminal Ready. When low, this output indicates to the MODEM or data set that
the UART is ready to establish a communications link. The DTR signal can be set to an active low
by programming bit 0 (DTR) of the MODEM Control Register to a high level. A Master Reset
operation sets this signal to its inactive (high) state. Loop mode operation holds this signal to its
inactive state. (See CFG0, 1 for further information.)
ERR
120
I
Error. A connected printer sets this input low when it has detected an error. This pin has a
nominal 25 kX pull-up resistor attached to it.
FDACK
28
I
FDC DMA Acknowledge. Active low input to acknowledge the FDC DMA request and enable the
RD and WR inputs during a DMA transfer. When in PC-AT or Model 30 mode, this signal is
enabled by bit D3 of the Digital Output Register (DOR). When in PS/2 mode, FDACK is always
enabled, and bit D3 of the DOR is reserved. FDACK should be held high during I/O accesses.
FDRQ
27
O
DMA Request. Active high output to signal the DMA controller that a FDC data transfer is
needed. When in PC-AT or Model 30 mode, this signal is enabled by bit D3 of the DOR. When in
PS/2 mode, FDRQ is always enabled, and bit D3 of the DOR is reserved.
GPIO10–17
3-1,
158–154
I/O
General Purpose I/O10 – 17. General purpose I/O pins of I/O port 1.
GPIO20–27
153–150,
118–115
I/O
General Purpose I/O20 – 27. General purpose I/O pins of I/O port 2.
HCS0
87
O
Hard Drive Chip Select 0. This output is active in the PC-AT mode when 1) the hard drive
registers from 1F0– 1F7h are selected and the primary address is used or 2) when the hard drive
registers from 170– 177h are selected and the secondary address is used. This output is inactive
if the IDE interface is disabled via the Configuration Register. HCS0 is multiplexed with SELCS
strap input. A 40 kX internal pull-up resistor is, therefore, used on this pin during reset. (See
SELCS for further information.)
HCS1
86
O
Hard Drive Chip Select 1. This output is active in the PC-AT mode when 1) the hard drive
registers from 3F6– 7 are selected and the primary address is used or 2) the hard drive registers
from 376–377 are selected and the secondary address is used. This output is also inactive, if the
IDE interface is disabled via the Configuration Register.
DIR
Note: Whenever the DDSR bit of the MSR is set, an interrupt is generated if MODEM Status interrupts are enabled.
11
1.0 Pin Description (Continued)
TABLE 1-1. Pin Descriptions (Alphabetical) (Continued)
Pin
I/O
HDSEL
Symbol
62
O
FDC Head Select. This output determines which side of the FDD is accessed. When Active, the head
selects side 1. When inactive, the head selects side 0.
IDEACK
83
I
IDE DMA Acknowledge. This is the IDE DMA acknowledge input pin when bit 1 of FCR is 1.
IDED7
89
I/O
IDEHI
85
O
IDE High Byte. This output enables the high byte data latch during a read or write to the hard drive if
the hard drive returns IOCS16. This output is inactive if the IDE interface is disabled via the
Configuration Register.
IDELO
84
O
IDE Low Byte. This output enables the low byte data latch during a read or write to the hard drive. This
output is inactive if the IDE interface is disabled via the Configuration Register. (See CFG0 for further
information.)
INDEX
76
I
FDC Index. This input signals the beginning of a FDD track.
INIT
122
I/O
IOCHRDY
22
O
I/O Channel Ready. This is the I/O Channel Ready open drain output. When IOCHRDY is driven low,
the EPP extends the host cycle.
IOCS16
88
I
I/O Chip Select 16-Bit. This input is driven by a connected peripheral device which can accommodate
a 16-bit access. This pin is configured when bit 2 of ASC is 0.
IRRX
113
I
Infrared Receiver.
IRTX
114
O
Infrared Transmitter.
IRQ1
5
I/O
19, 18
O
IRQ3, 4
Function
IDE Bit 7. This pin provides the data bus bit 7 signal to the IDE hard drive during accesses in the
address range 1F0–1F7h, 170–177h, 3F6h and 376h. This pin is TRI-STATE during read or write
accesses to 3F7h and 377h.
Initialize. When this signal is low it causes a connected printer to be initialized. This pin is in a TRISTATE condition 10 ns after a 1 is loaded into the corresponding Control Register bit. The system
should pull this pin high using a 4.7 kX resistor.
Interrupt 1. KBC’s keyboard interrupt generated from internal P24 of the KBC.
Interrupt 3 and 4. These are active high interrupts associated with the serial ports. When bit 0 of the
Plug and Play register (PNP1) is 0, IRQ3 presents the signal if the serial channel has been designated
as COM2 or COM4 and IRQ4 presents the signal if the serial port is designated as COM1 or COM3.
The appropriate interrupt goes active whenever it is enabled via the Interrupt Enable Register (IER),
the associated Interrupt Enable bit (Modem Control Register bit 3, MCR3), and any of the following
conditions are active: Receiver Error, Receive Data available, Transmitter Holding Register Empty, or a
Modem Status Flag is set. The interrupt signal is reset low (inactive) after the appropriate interrupt
service routine is executed, after being disabled via the IER, or after a Master Reset.
Either interrupt can be disabled, putting it into TRI-STATE, by setting the MCR3 bit low. When bit 0 of
the PNP1 register is 1, IRQ3 and IRQ4 are selected according to bits 2 amd 6 of the PNP1 register.
See Table 2-10 for IRQ3 and IRQ4 TRI-STATE conditions.
IRQ5
16
I/O
Interrupt 5. Active high output that indicates a parallel port interrupt. When enabled this bit follows the
ACK signal input. When bit 4 in the parallel port Control Register is set and the parallel port address is
designated as shown in Table 2-5, this interrupt is enabled. When it is not enabled this signal is
TRI-STATE.
This pin is I/O only when ECP is enabled, IRQ5 is configured, and bit 6 of PCR is 1. When bit 4 of the
PNP0 register is 1, IRQ5 and IRQ7 are selected according to bit 5 of the PNP0 register. See Table 2-9
for IRQ5 and IRQ7 TRI-STATE conditions.
IRQ6
15
O
IRQ7
14
I/O
Interrupt 6. Active high output to signal the completion of the execution phase for certain FDC
commands. Also used to signal when a data transfer is ready during a Non-DMA operation. When in
PC-AT or Model 30 mode, this signal is enabled by bit D3 of the DOR. When in PS/2 mode, IRQ6 is
always enabled, and bit D3 of the DOR is reserved.
Interrupt 7. Active high output that indicates a parallel port interrupt. When enabled this bit follows the
ACK signal input. When bit 4 in the parallel port Control Register is set and the parallel port address is
designated as shown in Table 2-5, this interrupt is enabled. When it is not enabled this signal is
TRI-STATE.
This pin is I/O only when ECP is enabled, IRQ7 is configured, and bit 6 of PCR is 1. For ECP operation,
refer to the interrupt ECP Section 7.11.1
12
1.0 Pin Description (Continued)
TABLE 1-1. Pin Descriptions (Alphabetical) (Continued)
Pin
I/O
IRQ8
Symbol
13
O
Function
IRQ12
4
I/O
Interrupt 12. KBC’s mouse interrupt generated from internal P25 of the KBC.
Interrupt 8. Real-Time Clock interrupt request output. This is an open-drain output.
KBCLK
94
I/O
Keyboard Clock output. Connected internally to KBC’s T0.
KBDAT
93
I/O
Keyboard Data output. Connected internally to KBC’s P10.
MCLK
91
I/O
Mouse Clock output. Connected internally to KBC’s T1.
MDAT
92
I/O
Mouse Data output. Connected internally to KBC’s P11.
MR
20
I
Master Reset. Active high input that resets the controller to the idle state, and resets all disk
interface outputs to their inactive states. The DOR, DSR, CCR, Mode command, Configure
command, and Lock command parameters are cleared to their default values. The Specify
command parameters are not affected. The Configuration Registers are set to their selected
default values.
MSEN0,1
79, 78
I
Media Sense. These pins are Media Sense input pins when bit 0 of FCR is 0. Each pin has a
40 kX internal pull-up resistor.
MTR0, 1
75, 72
O
FDC Motor Select 0, 1. These are the motor enable lines for drives 0 and 1, and are controlled by
bits D7–D4 of the Digital Output register. They are active low outputs. They are encoded with
information to control four FDDs when bit 4 of the Function Enable Register (FER) is set. MTR0
exchanges logical motor values with MTR1 when bit 4 of FCR is set. (See DR0,1.)
P12 – P17
141–146
I/O
KBC I/O Port. Quasi-bidirectional port for general purpose input and output.
P20, 21
147, 148
I/O
KBC I/O Port. Open-drain port for general purpose input and output.
PD0 – 7
136–133,
131–128
I/O
Parallel Port Data. These bidirectional pins transfer data to and from the peripheral data bus and
the parallel port Data Register. These pins have high current drive capability. (See DC Electrical
Characteristics.)
PDACK0, 1
26, 138
I
Parallel Port DMA Acknowledge. Active low input to acknowledge a connected printer’s DMA
request, and enable the RD and WR inputs during a DMA transfer. These inputs are valid only in
Enhanced Capabilities Port (ECP) mode. At any given moment, one of these two pins is
connected. The pin which is not selected is ignored. See bit 3 of SCF1 for pin selection.
PDRQ0, 1
25, 70
O
Parallel Port DMA Request. Active high output which signals the DMA controller that a printer
data transfer is required. These outputs are valid only in ECP mode. These pins are in TRI-STATE
when not selected. At any given moment, one of these two pins is connected. See bit 3 of SCF1
for pin selection.
PE
125
I
Parallel Port Paper End. This input is set high by a connected printer which is out of paper. This
pin has a nominal 25 kX pull-down resistor attached to it.
RD
44
I
Read. Active low input to signal a data read by the microprocessor.
RDATA
63
I
FDC Read Data. This input is the raw serial data read from the floppy disk drive.
105, 95
I
Ring Indicator. When low this indicates that a telephone ring signal has been received by the
MODEM. The RI signal is a MODEM status input whose condition the CPU can test by reading bit
6 (RI) of the MODEM Status Register (MSR) for the appropriate serial channel. Bit 6 is the
complement of the RI signal. Bit 2 (TERI) of the MSR indicates whether the RI input has changed
from low to high since the previous reading of the MSR.
RI1, 2
Note: When the TERI bit of the MSR is set, an interrupt is generated if MODEM Status interrupts are enabled.
RTS1, 2
109, 101
O
Request to Send. When low, this output indicates to the MODEM or data set that the UART is
ready to exchange data. The RTS signal can be set to an active low by programming bit 1 (RTS)
of the MODEM Control Register to a high level. A Master Reset operation sets this signal to its
inactive (high) state. Loop mode operation holds this signal to its inactive state. (See BADDR0 for
further information.)
SELCS
87
I
National Strap Pin. A 40 kX internal pull-up resistor. Do not pull this pin low during reset. (See
CS0CF bit 7.)
13
1.0 Pin Description (Continued)
TABLE 1-1. Pin Descriptions (Alphabetical) (Continued)
Symbol
Pin
I/O
Function
110, 102
I
Serial Input. This input receives composite serial data from the communications link (e.g. peripheral
device, MODEM, or data set).
SLCT
124
I
Select. When a printer is connected, it sets this input high. This pin has a nominal 25 kX pull-down
resistor attached to it.
SLIN
123
I/O
Select Input. When this signal is low it selects the printer. This pin is a TRI-STATE condition 10 ns
after a 0 is loaded into the corresponding Control Register bit. The system should pull this pin high
using a 4.7 kX resistor.
108, 98
O
STB
137
I/O
STEP
68
O
Step. This output signal issues pulses to the disk drive at a software programmable rate to move
the head during a seek operation.
SIN1, 2
SOUT1, 2
Serial Output. This output sends composite serial data to the communications link (peripheral
device, MODEM, or data set). The SOUT signal is set to a marking state (logic 1) after a Master
Reset operation. (See BOUT and BADDR1 for further information.)
Data Strobe. This output indicates to the printer that valid data is available at the printer port. This
pin is in a TRI-STATE condition 10 ns after a zero is loaded into the corresponding Control Register
bit. The system should pull this pin high using a 4.7 kX resistor. (See WRITE for further information.)
SYSCLK
21
I
System Clock. This input is used as the KBC input clock when bit 7 of KRR is 1.
TC
29
I
Terminal Count. Control signal from the DMA controller to indicate the termination of a DMA
transfer. TC is accepted only when FDACK or PDACK is active. TC is active high in PC-AT mode
and active low in PS/2 mode.
TRK0
65
I
Track 0. This input indicates to the controller that the head of the selected floppy disk drive is at
track zero.
VBAT
7
VDD
160, 140,
99, 57,
41, 17
Battery. Real-Time Clock battery pin.
Digital Supply. This is the 5V supply voltage for the digital circuitry.
VSS
159, 149,
139, 132,
121, 100,
90, 80,
58, 40,
32, 10
Digital Ground. This is the ground for the digital circuitry.
WAIT
126
I
Wait. This signal is used, in EPP mode, by the parallel port device to extend its access cycle. It is
active low. (See BUSY and Table 8-5 for further information.)
WR
43
I
Write. Active low input to signal to indicate a write from the microprocessor to the controller.
WDATA
67
O
Write Data. This output is the write precompensated serial data that is written to the selected floppy
disk drive. Precompensation is software selectable.
WGATE
66
O
Write Gate. This output signal enables the write circuitry of the selected disk drive. WGATE has
been designed to prevent glitches during power up and power-down. This prevents writing to the
disk when power is cycled.
WP
64
I
Write Protect. This input indicates that the floppy disk in the selected drive is write protected.
WRITE
137
O
Write Strobe. This signal is used in EPP mode as a write strobe. It is active low. (See STB and
Table 8-5 for further information.)
X1
30
I
Clock Oscillator. A TTL or CMOS compatible 24 MHz clock is connected to this pin.
X1C
8
I
Crystal1 Slow. Input for the internal Real-Time Clock crystal oscillator amplifier.
14
1.0 Pin Description (Continued)
TABLE 1-1. Pin Descriptions (Alphabetical) (Continued)
Pin
I/O
X2C
Symbol
9
O
Crystal2 Slow. Output for the internal Real-Time Clock crystal oscillator amplifier.
Function
ZWS
24
O
Zero Wait State. This pin is the Zero Wait State open drain output pin. ZWS is driven low when the EPP,
or the ECP, is written, and the access can be shortened.
Reserved
31
Reserved. This pin must be left unconnected.
FIGURE 1-1. Pins Which Utilize the Strap Function During Reset
Pin
Symbols
84
IDEL0/CFG0
87
HCS0/SELCS
106
DTR1/CFG1
108
SOUT1/BOUT1/BADDR1
109
RTS1/BADDR0
FIGURE 1-2. Multi-Function Pins
Pin
Symbols
98
SOUT2/BOUT2
108
SOUT1/BOUT1
119
AFD/DSTRB
123
SLIN/ASTRB
126
BUSY/WAIT
137
STB/WRITE
15
2.0 Configuration Registers
2.1 OVERVIEW
2.2 SOFTWARE CONFIGURATION
Eighteen registers constitute the Base Configuration Register set, and control the PC87306 setup. In general, these
registers control the enabling of major functions (FDC,
UARTs, parallel port, pin functionalty etc.), the I/O addresses of these functions, and whether they power-down via
hardware control or not. These registers are the Function
Enable Register (FER), the Function Address Register
(FAR), the Power and Test Register (PTR), the Function
Control Register (FCR), the Printer Control Register (PCR),
the Keyboard and Real-Time Clock Control Register (KRR),
the Power Management Control Register (PMC), the Tape,
UARTs and Parallel Port Register (TUP), the SuperI/O Identification Register (SID), the Advanced SIO Configuration
Register (ASC), the Chip Select 0 Address Low Register
(CS0LA), the Chip Select 0 High Address Register (CS0HA),
the Chip Select 0 Configuraton Register (CS0CF), the Chip
Select 1 Low Address Register (CS1LA), the Chip Select 1
High Address Register (CS1HA), the Chip Select 1 Configuration Register (CS1CF), the Infrared Configuration Register
(IRC), the General Purpose I/O Port Base Address Configuration Register (GPBA), and the SuperI/O Configuration
Register 0 (SCF0).
The FER, FAR, PTR, KRR, and SCF0 registers can be accessed via hardware or software. During reset, the PC87306
loads a set of default values, selected by a hardware strapping option, into the FER, FAR, and PTR Configuration Registers. The remaining 13 registers can only be accessed by
software.
An index and data register pair are used to read and write
these registers. Each Configuration Register is pointed to by
the value loaded into the Index Register. The data to be
written into the Configuration Register is transferred via the
Data register. A Configuration Register is read in a similar
way (i.e., by pointing to it via the Index Register and then
reading its contents via the Data Register).
Accessing the Configuration Registers in this way requires
only two system I/O addresses. Since that I/O space is
shared by other devices the Index and Data Registers can
still be inadvertantly accessed. To reduce the chances of an
inadvertant access, a simple procedure (see Section 2.2)
has been developed.
To maintain compatibility with other SuperI/O chips, register
bits with reserved values may not be altered. Use a readmodify-write procedure.
If the system requires access to the Configuration Registers
after reset, the following procedure must be used to change
data in the registers.
1. Determine the PC87306 Index Register’s default location.
Check the four possible locations (see Table 2-1) by
reading them twice. The first byte is the ID byte 88h. The
second byte read is always 00h, but read after write always brings the value of the written byte. Compare the
data read with the ID byte and then 00h. A match occurs
at the correct location. Note that the ID byte is only issued from the Index Register during the first read after a
reset. Subsequent reads return the value loaded into the
Index Register. Bits 5 – 7 are reserved and always read 0.
2. Load the Configuration Registers.
A. Disable CPU interrupts.
B. Write the index of the Configuration Register (00h –
0Dh) to the Index Register one time.
C. Write the correct data for the Configuration Register in
two consecutive write accesses to the Data Register.
D. Enable CPU interrupts.
3. Load the Configuration Registers (read-modify-write).
A. Disable CPU interrupts.
B. Write the index of the Configuration Register (00h –
0Dh) to the Index Register one time.
C. Read the configuration data in that register via the
Data Register.
D. Modify the configuration data.
E. Write the changed data for the Configuration Register
in two consecutive writes to the Data Register. The
register updates on the second consecutive write.
F. Enable CPU interrupts.
A single read access to the Index and Data Registers can
be done at any time without disabling CPU interrupts. When
the Index Register is read, the last value loaded into the
Index Register is returned. When the Data Register is read,
the Configuration Register data pointed to by the Index Register is returned.
16
2.0 Configuration Registers (Continued)
TL/C/12379 – 4
TL/C/12379 – 5
TL/C/12379 – 6
TL/C/12379 – 7
TL/C/12379 – 9
TL/C/12379 – 8
TL/C/12379 – 11
TL/C/12379 – 10
TL/C/12379 – 13
TL/C/12379 – 12
FIGURE 2-1. PC87306 Configuration Registers
17
2.0 Configuration Registers (Continued)
TL/C/12379–14
TL/C/12379 – 19
TL/C/12379–15
TL/C/12379 – 20
TL/C/12379–16
TL/C/12379 – 21
TL/C/12379–17
TL/C/12379 – 22
TL/C/12379–18
TL/C/12379 – 97
FIGURE 2-1. PC87306 Configuration Registers (Continued)
18
2.0 Configuration Registers (Continued)
TL/C/12379 – 23
TL/C/12379 – 25
TL/C/12379 – 24
FIGURE 2-1. PC87306 Configuration Registers (Continued)
allows the registers to avoid conflicts with other adapters in
the I/O address space. Table 2-2 shows the address options.
2.3 HARDWARE CONFIGURATION
During reset, 1 of 4 possible sets of default values are loaded into the first five Configuration Registers. A strapping
option on two pins (CFG0, 1) selects the set of values that is
loaded. This allows for automatic configuration without software intervention. Table 2-1 shows the 4 possible default
configurations. The default configuration can be modified by
software at any time after reset by using the access procedure described in the Software Configuration Section.
TABLE 2-2. Index and Data Register
Optional Locations
BADDR1
BADDR0
Index Addr.
0
0
398
399
0
1
26E
26F
1
0
15C
15D
1
1
2E
2F
2.4 INDEX AND DATA REGISTERS
Another general aspect of the Configuration Registers is
that the Index and the Data Register pair can be relocated
to any one of two locations. This is controlled through a
hardware strapping option on two pins (BADDR0,1) and it
Data Addr.
TABLE 2-1. Default Configurations Controlled by Hardware on Reset
Configuration
Pins
Configuration Register Reset Values (Binary)
Activated Functions
on Reset
CFG1
CFG0
FER
FAR
PTR
KRR
SCF0
0
0
01001011
00000001
00000x00
0x001101
0x110000
PRI (FDC), PRI (IDE),
LPTA, COM1, GPIO
KBC, RTC
0
1
1
0
00001111
00010001
00000x00
0x001101
0x000000
PRI (FDC), LPTA, COM1,
COM2 (non-IR), KBC, RTC
1
1
00000000
00010000
00000x00
0x000001
0x000000
All Modules Disabled
(powered-down), except KBC
Reserved Mode
Where:
PRI
is the PRImary floppy or IDE address; 3F0 – 7h or
1F0–7, 3F6, 3F7h)
COM1 is the UART address at 3F8–3FFh
COM2 is the UART address at 2F8–2FFh
LPTA is the Parallel Port address at 3BC–3BEh
Reserved Mode
GPIO
KBC
RTC
19
is the General Purpose I/O ports 1 and 2 addresses
at 78h and 79h
is the Keyboard Controller function, using an
X1 d 3 clock
is the Real-Time Clock function
2.0 Configuration Registers (Continued)
2.5 BASE CONFIGURATION REGISTERS
2.5.1 Function Enable Register (FER, Index 00h)
This register enables and disables major chip functions. Disabled functions have their clocks automatically powered
down, but the data in their registers remains intact. It also
selects whether the FDC and the IDE controller is located at
their primary or secondary address. See Table 2-1 for the
FER reset value.
Bit 0 When this bit is one the parallel port can be accessed
at the address specified in the FAR.
Bit 1 When this bit is one, UART1 can be accessed at the
address specified in the FAR. When this bit is zero,
access to UART1 is blocked and it is in power-down
mode. The UART1 registers retain all data in power
down mode.
Caution: Any UART1 interrupt that is enabled and
active or becomes active after UART1 is disabled asserts the associated IRQ pin when UART1 is disabled. If disabling UART1 via software, clear the IRQ
Enable bit (MCR3) to zero before clearing FER 1.
This is not an issue after reset because MCR3 is zero
until it is written.
Bit 2 When this bit is one, UART2 can be accessed at the
address specified in the FAR. When this bit is zero,
access to UART2 is blocked and it is in power-down
mode. The UART2 registers retain all data in power
down mode.
Caution: Any UART2 interrupt that is enabled and
active or becomes active after UART2 is disabled asserts the associated IRQ pin when UART1 is disabled
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
If disabling UART2 via software, clear the IRQ Enable bit (MCR3) to zero before clearing FER1. This is
not an issue after reset because MCR3 is zero until it
is written.
When this bit is one, the FDC can be accessed at the
address specified in the FER bits. When this bit is
zero access to the FDC is blocked and it is in powerdown mode. The FDC registers retain all data in power down mode.
When this bit is zero the PC87306 can control two
floppy disk drives directly without an external decoder. When this bit is one the two drive select signals
and two motor enable signals from the FDC are encoded so that four floppy disk drives can be controlled (see Table 2-3 and Figure 2-2 ). Controlling
four FDDs requires an external decoder. The pin
states shown in Table 2-3 are a direct result of the bit
patterns shown. All other bit patterns produce pin
states that should not be decoded to enable any
drive or motor.
This bit selects the primary or secondary FDC address. (See Table 2-4.)
When this bit is a one the IDE drive interface can be
accessed at the address specified by FER bit 7.
When it is zero, bit 0 of PMC determines whether the
HCS0,1 pins are inactive, or in TRI-STATE. IDEHI
and IDEHLO are inactive and IDED7 is in TRISTATE.
This bit selects the primary or secondary IDE address. (See Table 2-4).
TABLE 2-3. Encoded Drive and Motor Pin Information (FER 4 e 1)
7
X
X
X
1
X
X
X
0
6
X
X
1
X
X
X
0
X
Digital Output Register
5
4
3
2
X
1
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
0
X
X
X
X
X
X
X
X
X
X
X
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
MTR1
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
Drive Control Pins
MTR0
DR1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
DR0
0
1
0
1
0
1
0
1
Decoded Functions
Activate Drive 0 and Motor 0
Activate Drive 1 and Motor 1
Activate Drive 2 and Motor 2
Activate Drive 3 and Motor 3
Activate Drive 0 and Deactivate Motor 0
Activate Drive 1 and Deactivate Motor 1
Activate Drive 2 and Deactivate Motor 2
Activate Drive 3 and Deactivate Motor 3
Note: When FER4 e 1, MTR1 presents a pulse that is the inverted image of the IOW strobe. This inverted pulse is active whenever an I/O write to address 3F2h or
372h takes place. This pulse is delayed by 25 ns–80 ns after the leading edge of IOW and its leading edge can be used to clock data into an external latch (e.g.,
74LS175). Address 3F2h is used if the FDC is located at the primary address (FER5 e 0) and address 372h is used if the FDC is located at the secondary address
(FER5 e 1).
Hex Buffers
ICC e 40 mA
open collector
FIGURE 2-2. PC87306 Four Floppy Drive Circuit
20
TL/C/12379 – 26
2.0 Configuration Registers (Continued)
Bits 2–5 These bits determine which ISA I/O address
range is associated with each UART (see Tables
2-6, 2-7 and 2-9).
TABLE 2-4. Primary and Secondary
Drive Address Selection
Bit 5
Bit 7
Drive
PC-AT Mode
0
X
FDC
Primary,
3F0– 7h
1
X
FDC
Secondary,
3F0– 7h
X
0
IDE
Primary,
1F0–7, 3F6, 3F7h
X
1
IDE
TABLE 2-6. COM Port Selection for UART1
FAR
Bit 2
0
0
1 (3F8-F)
0
1
2 (2F8-F)
1
0
3 (Table 2-8)*
1
1
4 (Table 2-8)*
Secondary
170–7, 376, 7h
2.5.2 Function Address Register (FAR, Index e 01h)
This register selects the ISA I/O address range to which
each peripheral function responds. See Table 2-1 for its reset value.
UART1
Bit 3
COMÝ
*Note: COM3 and COM4 addresses are determined by Bits 6 and 7.
TABLE 2-7. COM Port Selection for UART2
FAR
UART2
Bits 0,1 These bits select the parallel port address as
shown in Table 2-5 and Table 2-9:
Bit 5
Bit 4
COMÝ
TABLE 2-5. Parallel Port Addresses
0
0
1 (3F8-F)
0
1
2 (2F8-F)
1
0
3 (Table 2-8)*
1
1
4 (Table 2-8)*
PNP0 PNP0 FAR FAR
Bit 4 Bit 5 Bit 1 Bit 0
0
X
0
0
Parallel
Port
Address
LPTB (378–37F)
0
X
0
1
LPTA (3BC–3BE)
(Note 2)
0
X
1
0
LPTC (278–27F)
0
X
1
1
Reserved
1
1
0
1
X
X
X
X
PC-AT
Interrupt
IRQ5
(Note 1)
*Note: COM3 and COM4 addresses are determined by Bits 6 and 7.
IRQ7
Bits 6, 7 These bits select the addresses that are used for
COM3 and COM4 (see Table 2-8).
IRQ5
TABLE 2-8. Address Selection for COM3 and COM4
TRI-STATE
(CTR4 e 0)
LPTB (378–37F)
(Note 2)
LTPC (278–27F)
(Note 2)
IRQ5
IRQ7
Bit 7
Bit 6
COM3 IRQ4
COM4 IRQ3
0
0
3E8 –Fh
2E8 –Fh
0
1
338 –Fh
238 –Fh
1
0
2E8 –Fh
2E0 –7h
1
1
220 –7h
228 –Fh
Note 1: The interrupt assigned to this address can be changed to IRQ7 by
setting Bit 3 of the power and test register.
Note 2: The parallel port address is selected according to bits 0 and 1 of
FAR or bit 6 of PNP0.
TABLE 2-9. TRI-STATE Conditions of IRQ5 and IRQ7
Bit 4 of PNP0 e 0
Bit 4 of PNP0 e 1
IRQ5
((FAR.bit1 e 0) and (FAR.bit0 e 1)) or
((FAR.bit1 e 0) and (FAR.bit0 e 0)) and
(PTR.bit3 e 1)) or
(CTR.bit4 e 0 and PCR.bit2 e 0)
(PNP0.bit5 e 1) or
(FER.bit0 e 0) or
(CTR.bit4 e 0 and PCR.bit2 e 0)
IRQ7
((FAR.bit1 e 0) and (FAR.bit0 e 0)) and
(PTR.bit3 e 0)) or
((FAR.bit1 e 1) and (FAR.bit0 e 0)) or
(CTR.bit4 e 0 and PCR.bit2 e 0)
(PNP0.bit5 e 0) or
(FER.bit0 e 0) or
(CTR.bit4 e 0 and PCR.bit2 e 0)
21
2.0 Configuration Registers (Continued)
Set this bit to 0 for Compatible mode, Pulse Interrupt. Set this bit to 1 for Extended mode, Level Interrupt.
TABLE 2-10. TRI-STATE Conditions of IRQ3 and IRQ4
IRQ3
IRQ4
Bit 0 of PNP1 e 0
Bit 0 of PNP1 e 1
According to FAR
selection and
bits 3, 4 of MCR
[(PNP1.bit2 e 1) or
(FER.bit1 e 0) or
(MCR1.bit3 e 0) or
(MCR1.bit4 e 1)]
and
[(PNP1.bit6 e 1) or
(FER.bit2 e 0) or
(MCR2.bit3 e 0) or
(MCR2.bit4 e 1)]
According to FAR
selection and
bits 3, 4 of MCR
Note: Parallel port interrupt (Pulse/Level) in EPP and ECP
modes is always pulse.
This bit is ignored in ECP and EPP modes.
2.5.4 Function Control Register (FCR, Index e 03h)
This register enables the ZWS option when in Enhanced
Parallel Port mode.
On reset the FCR is initialized to X00XXX01.
Bit 0
TDR Mode Select bit. This bit selects the TDR
mode when ASC2 e 0 as follows:
0: Automatic Media Sense TDR (PC87322 type).
1: PC-AT Compatible TDR (PC87312 type).
This bit is ignored when ASC2 e 1. See ASC bit 2
for complete TDR mode selection.
Bit 1
IDE DMA Enable Bit. When this bit is 0, the IDE
DMA is disabled. When this bit is 1, the IDE DMA is
enabled.
Bit 2
Reserved.
Bit 3
Reserved.
Bit 4
Reserved.
[(PNP1.bit2 e 0) or
(FER.bit1 e 0) or
(MCR1.bit3 e 0) or
(MCR1.bit4 e 1)]
and
[(PNP1.bit6 e 0) or
(FER.bit2 e 0) or
(MCR2.bit3 e 0) or
(MCR2.bit4 e 1)]
2.5.3 Power and Test Register (PTR, Index e 02h)
This register determines several power-down features: the
power-down method used when the power-down pin
(PWDN) is asserted (crystal and clocks vs clocks only),
whether hardware power-down is enabled, and provides a
bit for software power-down of all enabled functions. It selects whether IRQ7 or IRQ5 is associated with LPTB. It puts
the enabled UARTs into their test mode. See Table 2-1 for
its reset value.
Independent of this register the floppy disk controller can
enter low power mode via the Mode Command or the Data
Rate Select Register.
Bit 0 Setting this bit causes all enabled functions to be
powered down.
Bit 1 Reserved.
Bit 2 Reserved.
Bit 3 Setting this bit associates the parallel port with IRQ7
when the address for the parallel port is 378–37Fh
(LPTB). This bit is a ‘‘don’t care’’ when the parallel
port address is 3BC–3BEh (LPTA) or 278–27Fh
(LPTC).
When bit 4 of PNP0 is 1, this bit is ignored.
Bit 4 Setting this bit puts UART1 into a test mode, which
causes its Baud Out clock to be present on its SOUT1
pin if the Line Control Register bit 7 is set to 1.
Bit 5 Setting this bit puts UART2 into a test mode, which
causes its Baud Out clock to be present on its SOUT2
pin if the Line Control Register bit 7 is set to 1.
Bit 6 Setting this bit to a 1 prevents all further write accesses to the Configuration Registers. Once it is set by
software it can only be cleared by a hardware reset.
Bit 7 When not in EPP or ECP modes, this bit controls
Compatible/Extended mode, thus controlling Pulse/
Level interrupt.
Zero Wait State enable bit. If this bit is 1, ZWS is
driven low when the Enhanced Parallel Port
(EPP), or the ECP, can accept a short host read/
write-cycle, otherwise the ZWS open drain output
is not driven. EPP ZWS operation should be configured when the system’s device is fast enough
to support it.
Bits 6, 7 Reserved. Use Read Modified Write to change the
FCR register.
Bit 5
2.5.5 Printer Control Register (PCR, Index e 04h)
This register enables the EPP and ECP version modes, and
interrupt options. It also enables the RTC RAM write mask
bit. On reset the PCR bits are cleared to 0.
The parallel port mode is software configurable as shown in
Table 2-11.
TABLE 2-11. Parallel Port Mode
Operation
Mode
FER
Bit 0
PTR
Bit 7
PCR
Bit 0
PCR
Bit 2
None
0
X
X
X
Compatible
1
0
0
0
Extended
1
1
0
0
EPP
1
X
1
0
ECP
1
X
0
1
Bit 0
Bit 1
22
EPP enable bit. When this bit is 0, the EPP is disabled, and the EPP registers are not accessible
(access ignored).
When this bit is 1, and bit 2 of PCR is 0, the EPP is
enabled. Note that the EPP should not be configured with base address 3BCh.
For further information refer to bit 5 of FCR.
EPP version select bit. When this bit is 0, Version
1.7 is supported, and STB, AFD, INIT, and SLIN
are open drain outputs.
2.0 Configuration Registers (Continued)
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
When this bit is 1, Version 1.9 is supported (IEEE
1284), and STB, AFD, INIT, and SLIN are push-pull
outputs. This bit has the same affect on the output
buffers in ECP modes 0 and 2.
ECP enabIe bit. When this bit is 0 the ECP is disabled and in power-down mode. The ECP registers
are not accessible (access ignored) and the ECP
interrupt and DMA are inactive. When this bit is 1
the ECP is enabled. The software should change
this bit to 1 only when bits 0, 1, and 2 of the existing CTR are 1, 0 and 0 respectively.
ECP clock freeze control bit. In power-down
modes 2 and 3: When this bit is 0, the clock provided to the ECP is stopped; and
When this bit is 1, the clock provided to the ECP is
not stopped.
Reserved. This bit must be set to 0.
Parallel port interrupt (IRQ5 or IRQ7) polarity control bit. When this bit is 0 the interrupt polarity is
level high or negative pulse. When this bit is 1 the
interrupt polarity is inverted.
Parallel port interrupt (IRQ5 or IRQ7) open drain
control bit. When this bit is 0 the configured interrupt line (IRQ5 or IRQ7) has a totem-pole output.
When this bit is 1 the configured interrupt line has
an open drain output (drive low, no drive high, no
internal pullup).
RTC RAM write mask bit. When this bit is 0, the
RTC RAM is writeable. When this bit is 1, the RTC
RAM is not writeable, and writes are ignored.
Bit 7
KBC clock source select bit. When this bit is 0 the
KBC uses the X1 clock source. When this bit is 1
the KBC uses the SYSCLK clock source. This bit
enables the KBC to operate in power-down mode,
even when the X1 clock is frozen. It may be modified only when the KBC is disabled via bit 0 of
KRR. See Table 2-1.
2.5.7 Power Management Control Register
(PMC, Index e 06h)
This register controls the TRI-STATE and input pins. The
PMC register is accessed through Index 06h. The PMC Register is cleared to X00XX000 on reset.
Bit 0
IDE TRI-STATE Control bit
0: When this bit is 0, it does not affect the IDE
pins.
1: IDE7 and HCS0,1 are in TRI-STATE, IDEHI and
IDELO are inactive when either the IDE is disabled or the chip is in power-down mode.
Bit 1
FDC TRI-STATE Control bit.
0: When this bit is 0, it does not affect the FDC
pins.
1: The FDC outputs, except IRQ6, are in
TRI-STATE when either the FDC is disabled or
the chip is in power down mode.
Bit 2
UART TRI-STATE Control bit.
0: When this bit is 0, it does not affect the UART’s
pins.
1: The outputs of any UART, except IRQ4 and
IRQ3, are in TRI-STATE when that UART is disabled or the chip is in power-down.
Bits 3, 4 Reserved.
Bit 5
Selective Lock bit. Unlike bit 6 of PTR, which locks
all configuration bits, this bit only enables locking
of the following:
Bit 5 of PMC, bit 4 of FER, bits 0 – 7 of FAR, bits 2,
3 of PTR, bit 1 of FCR, and bit 5 of KRR. Once this
bit has been set by software, it can only be cleared
by a hardware reset. It should be used instead of
bit 6 of PTR if a configration bit should be dynamically modified by software (e.g., PMC bits).
0: No lock, except via bit 6 of PTR.
1: Any write to the above configuration bits is ignored (until a hardware reset, which clears this
bit).
Bit 6
Parallel Port TRI-STATE Control bit.
0: When this bit is 0, it does not affect the parallel
port pins.
1: The parallel port outputs, except the configured
IRQ line (IRQ5 or IRQ7), are in TRI-STATE
when either the parallel port is disabled or the
chip is in power-down mode.
Bit 7
Reserved.
2.5.6 KBC and RTC Control Register
(KRR, Index e 05h)
This register enables and disables the keyboard controller
(KBC) and the Real-Time Clock (RTC). It selects the clock
source and operating mode of the KBC, selects different
banks of CMOS RAM in the RTC, and selects the RTC test
mode. When MR is high, KRR is initialized to 0X00XX01.
Bits 2 and 3 are initialized according to CFG0. See Table
2-1 for initialization values upon reset.
Bit 0
KBC Enable bit. When this bit is zero the KBC
clock is frozen and the state of its dedicated pins
cannot be altered. When this bit is one the KBC is
functional. See Bit 2.
Bit 1
KBC Speed control bit. Controls the KBC speed
when X1 clock source is selected (KRR7 is 0). This
bit is ignored when SYSCLK clock source is selected (KRR7 is 1).
When this bit is 0 the KBC clock is the X1 frequency divided by three (typically 8 MHz). When this bit
is 1 the KBC clock is the X1 frequency divided by
two (typically 12 MHz).
Bit 2
Reserved. This bit must be set to 1, otherwise the
KBC will not be functional.
Bit 3
RTC Enable bit. When this bit is 0 the RTC is disabled and IRQ8 is in TRI-STATE. When this bit is 1
the RTC is enabled.
Bit 4
Reserved.
Bit 5
RAMSREL. RTC CMOS RAM bank select. When
this bit is 1 it selects the upper 128 bytes of CMOS
RAM. When this bit is 0 it selects the lower
128 bytes of CMOS RAM.
Bit 6
Reserved.
2.5.8 Tape, UARTs and Parallel Port Configuration
Register (TUP, Index e 07h)
The TUP Register is cleared to XXXXX0XX on reset.
Bit 1
Reserved.
23
2.0 Configuration Registers (Continued)
Bit 2
EPP Timeout Interrupt Enable bit.
2.5.13 Chip Select 0 Configuration Register (CS0CF,
Index e 0Bh)
This register controls the behavior of the CS0 pin. CS0 is
asserted on non-DMA PIO cycles, when RD or WR is asserted. CS0 can be asserted three ways: 1) only on reads,
2) only on writes or 3) on all cycles. The register is initialized
to 1X000XXX during reset.
Bits 0 – 2 Reserved.
Bit 3
Chip Select 0 Decode
0: Decode 16-bit
1: Decode address bits 15 – 12 (HA15 – HA12 of
CS0HA) and CS0LA are ignored.
Bit 4
0: Disable CS0 assertion on write cycles.
When this bit is 0, the EPP timeout interrupt is
masked.
When this bit is 1, the EPP timeout interrupt is
generated on the selected IRQ line (IRQ5 or
IRQ7), according to bits [4:6] of PCR.
Bits 3 – 7 Reserved.
2.5.9 SuperI/O Identification Register
(SID, Index e 08h)
The SID Register is accessed, like the other configuration
registers, through the Index Register. This read-only register
is used to identify the PC87306 chip.
Bit 5
TL/C/12379–27
Bit 6
Bit 7
2.5.10 Advanced SuperI/O Configuration Register
(ASC, Index e 09h)
During reset bits 0 –2 and bit 5 are initialzed to 0, and bits 6–
7 are initialized to 1.
Bit 0, 1
VLD0, 1. These bits determine the state of bit 5
in the FDC Tape Drive Register (TDR) when either Automatic Media Sense TDR or Enhanced
TDR is configured (FCR0 e 0 or ASC2 e 1). For
more details see the TDR description.
Bit 2
Enhanced TDR support.
0: PC-AT Compatible TDR or Automatic Media
Sense TDR; selected by FCR0.
1: Enhanced TDR.
Bit 3
Reserved bit. On ASC writes, this bit must be
written with a 0. On ASC reads, the value is undefined.
Bit 4
Reserved.
Bit 5
The value of this pin is reflected on bit 3 of
CNFGA ECP register.
Bit 6
DENSEL’s polarity control bit.
0: DENSEL is active low for 500 kbps or 1 Mbps
data rates.
1: DENSEL is active high for 500 kbps or 1 Mbps
data rates.
Bit 7
System Operation Mode. The PC87306 can be
configured to either PC-AT or PS/2 modes.
0: PS/2 mode
1: PC-AT mode
Upon reset, this bit is initialized to 1; thus selecting PC-AT mode.
1: Enable CS0 assertion on write cycles.
0: Disable CS0 assertion on read cycles.
1: Enable CS0 assertion on read cycles.
Reserved.
CS0 pin enable.
0: Reserved for National use.
1: CS0 pin is enabled.
2.5.14 Chip Select 1 Low Address (CS1LA, Index e 0Ch)
This register holds the low address bits of the monitored I/O
address. Bit 0 holds A0. Upon reset this register is set to 0.
See CS1CF for a description of CS1 enable on read and
write cycles.
2.5.15 Chip Select 1 High Address (CS1HA, Index e
11h)
This register holds the high address bits of the monitored
I/O address. Bit 0 holds A8. Upon reset this register is set to
0.
See CS1CF for a description of CS1 enable on read and
write cycles.
2.5.16 Chip Select 1 Configuration Register (CS1CF,
Index e 0Dh)
This register controls the behavior of the CS1 pin. CS1 is
asserted on non-DMA PIO cycles, when RD or WR is asserted. CS1 can be asserted three ways: 1) only on reads,
2) only on writes or 3) on all cycles. The register is initialized
to XX00XXXX during reset.
Bits 0 – 2 Reserved.
Bit 3
Chip Select Decode.
0: Decode 16-bit (CS1LA and CS1HA).
1: Decode address bits 15 – 2. CS1LA bits 0 and
1 are ignored.
Bit 4
Enable CS1 assertion on write cycles.
Bit 5
Enable CS1 assertion on read cycles.
Bits 6 – 7 Reserved.
2.5.11 Chip Select 0 Low Address (CS0LA, Index e 0Ah)
This register holds the low address bits of the monitored I/O
address. Bit 0 holds A0. Upon reset this register is set to 0.
See CS0CF for a description of CS0 enable on read and
write cycles.
2.5.17 InfraRed Configuration Register (IRC, Index e
0Eh)
After reset, the register holds the value XX00XX00.
Bit 0 UART2 Interface Mode. This bit is used for run time
selection of either Normal (MODEM) Mode or IR
Mode.
0: Normal (MODEM) Mode
1: InfraRed (IR) Mode.
Bit 1 IR Half/Full Duplex configuration bit.
0: Full Duplex. Both transmitter and receiver are enabled simultaneously.
2.5.12 Chip Select 0 High Address (CS0HA, Index e
10h)
This register holds the high address bits of the monitored
I/O address. Bit 0 holds A8. Upon reset this register is set to
0.
See CS0CF for a description of CS0 enable on read and
write cycles.
24
2.0 Configuration Registers (Continued)
UART2 is disabled or the PC87306 is in powerdown mode.
1: Half Duplex. The receiver input is blocked to 1
while the transmitter is busy; from the beginning of the start bit till the end of the stop
bit(s).
Bits 2 – 3 Reserved.
Bit 4
Encoded IR transmitter drive control bit.
0: When IRTX is active, it is active for 1.6 ms.
1: When IRTX is active, it is active for 3/16 baud.
In Normal (MODEM) Mode and in Non Encoded
IR mode this bit is ignored.
Bit 5
Encoded/Non Encoded IR mode.
0: Encoded Mode. UART2’s SOUT is encoded
and routed to the IRTX pin and the IRRX pin is
decoded and routed to UART2’s SIN.
1: Non Encoded Mode. UART2’s SOUT is inverted and routed to the IRTX pin and the IRRX is
routed to UART2’s SIN.
In Normal (MODEM) Mode this bit is ignored.
Bits 6 – 7 Reserved.
See Section 7 for further information.
General Purpose I/O Port 1 (GPIO10 – 17) Enable.
0: GPIO Port 1 Disabled. Accesses to GPIO Port
1 is ignored.
1: GPIO Port 1 Enabled. GPIO Port 1 responds to
non DMA read and write accesses.
Bit 5
General Purpose I/O Port 2 (GPIO20 – 27) Enable.
0: GPIO Port 2 Disabled. Accesses to GPIO Port
2 is ignored.
1: GPIO Port 2 Enabled. GPIO Port 2 responds to
non DMA read and write accesses.
Bit 6
Reserved.
Bit 7
Reserved.
Upon reset the non reserved bits of SCF0 are initialized to
either 0x000000 or 0x110000 according to the CFG1 strap
pin.
Bit 4
2.5.18 General Purpose I/O Port Base Address
Configuration Register (GPBA, Index e 0Fh)
2.5.20 SuperI/O Configuration Register 1 (SCF1,
Index e 18h)
Upon reset the implemented bits are initialized to 0.
Bit 0
Reserved.
Bits 1, 2 Reported ECP DMA number, as reflected on bits
0 and 1 of the CNFGB ECP register. Bit 2 of
SCF1 is reflected on bit 1 of CNFGB and bit 1 of
SCF1 on bit 0 of CNFGB. Microsoft’s ECP Protocol and ISA Interface Standard defines these bits
as follows (bit 1 of CNFGB is MSB):
00: Jumpered 8-bit DMA.
01: DMA channel 1 selected.
10: DMA channel 2 selected.
11: DMA channel 3 selected.
Bit 3
Selected ECP DMA pins.
0: PDRQ0 and PDACK0 pins are used for ECP
DMA.
1: PDRQ1 and PDACK1 pins are used for ECP
DMA.
This register holds address bits A2–9 of the GPIO Ports
base address. Bit 0 holds A2.
The other 8 bits of the 16-bit base address are 0. The base
address is therefore composed as follows:
A15
A10
0
A9
A2
GPBA
A1
A0
0
GPIO Port 1 is at the base address and GPIO Port 2 at the
base address a 1.
Upon reset GPBA is initialized to 00011110, thus dictating
base address e 78h.
2.5.19 SuperI/O Configuration Register 0 (SCF0,
Index e 12h)
See Table 2-1 for reset value.
Bit 0
RTC RAM lock bit. Once this bit is set to 1, it can
only be cleared by a hardware reset.
0: Read and write access to locations 38 – 3Fh of
the RTC RAM is not blocked.
1: Read and write access to locations 38 – 3Fh of
the RTC RAM is blocked. Writes are ignored
and reads return FFh.
Note that bit 7 of the PCR register also affects
RTC RAM locking, even when this bit is 0.
Bit 1
IRQ1 and IRQ12 latch enable.
0: Hardware latching is disabled (8042 compatible mode).
1: Hardware latching is enabled (IRQ latching
mode).
Bit 2
IRQ12 TRI-STATE control bit.
0: IRQ12 is driven with quasi-bidirectional buffer.
1: IRQ12 output is in TRI-STATE mode and
IRQ12 input is masked to 1.
Bit 3
UART2 TRI-STATE control bit. UART2 and IR
outputs, except IRQ3 and IRQ4 pins, are in TRISTATE and the inputs are blocked to reduce
their leakage current when this bit is 1 and either
Note: (For bits 1–3.) It is the (PnP BIOS) softwares responsibility to match the DMA channel number, as reflected in
the CNFGB register, to the selected channel (for the
given wiring of those pins to the host DMA channel
pins), i.e., to match the value written in bits 2–1 to the
value of bit 3 according to the PC87306 wiring.
Bits 4, 5
Bits 6, 7
Reserved.
These bits are general purpose scratch bits.
When bit 3 of the FCR is 0, the bits are read/
write bits. When bit 3 of the FCR is 1, the bits are
read-only. After reset they are read/write bits.
Once the bits are changed to be read-only, they
can be changed back to be read/write bits only
by assertion of reset.
2.5.21 LPT Base Address Register (LPTBA, Index e
19h)
This register holds address bits A2 – 9 of the parallel port
base address when LPTA is selected via bits 0, 1 of FAR,
i.e., when bit 1 of FAR is 0 and bit 0 of FAR is 1. Bit 0 of
LPTBA holds A2. The other eight bits of the 16-bit base
address (i.e., A0 – 1 and A10 – 15) are 0. The base address is
therefore composed as follows:
25
2.0 Configuration Registers (Continued)
A15
A10
0
A9
A2
LPTBA
A1
0: UART1’s interrupt, i.e., IRQ3 or IRQ4, is selected via bits 2 and 3 of FAR register.
A0
0
UART2’s interrupt, i.e., IRQ3 or IRQ4, is selected via bits 4 and 5 of FAR register.
The selection is dependent on the base I/O
address selection.
This is the backward-compatible mode with
previous SIOs.
1: UART1’s interrupt, i.e., IRQ3 or IRQ4, is selected via bit 2 of PNP1 register.
UART2’s interrupt, i.e., IRQ3 or IRQ4, is selected via bit 6 of PNP1 register.
The selection is independent of the base I/O
address.
Bit 1
Reserved.
Bit 2
UART1 interrupt mapping. UART1’s interrupt is
routed to the following ISA interrupt:
0: IRQ3
1: IRQ4
When bit 0 of PNP1 register is 0 this bit is ignored, i.e., it does not determine UART1 interrupt
mapping.
Bits 3 – 5 Reserved.
Bit 6
UART2 interrupt mapping. UART2’s interrupt is
routed to the following ISA interrupt:
0: IRQ3
1: IRQ4
When bit 0 of PNP1 register is ‘‘0’’ this bit is ignored, i.e., it does not determine UART2 interrupt
mapping.
Bit 7
Reserved.
It is the software’s responsibility to route UART1’s and
UART2’s interrupts onto the ISA interrupts correctly.
When bit 6 of PNP0 is 0, this register is read only and is
forced to EFh. This register may be modified only when the
parallel port is disabled. Bit 0 (holding A2) must be 0 when
EPP is enabled and bit 6 of PNP0 is 1.
Undefined results occur if a parallel port register is located
at the same address as an enabled SIO register due to
LPTBA configuration.
Note: To modify LPTA base address, first disable the parallel port, then set
bit 6 of PNP0 to 1, then update LPTBA, and then enable the parallel
port.
2.5.22 Plug and Play Configuration 0 Register (PNP0,
Index e 1Bh)
Upon reset the implemented bits are initialized to 0.
Bits 0 – 3 Reserved.
Bit 4
Parallel Ports’ interrupt selection control.
0: Parallel Port’s interrupt, i.e., IRQ5 or IRQ7, is
selected via bits 0 and 1 of FAR register and
bit 3 of PTR register, i.e., the selection is dependent on the base I/O address selection.
This is the backward-compatible mode with
previous SIOs.
1: Parallel Port’s interrupt, i.e., IRQ5 or IRQ7, is
selected via bit 5 of PNP0 register.
The selection is independent of the base I/O
address.
Bit 5
Parallel Port interrupt mapping. The parallel
port’s interrupt is routed to the following ISA interrupt:
0: IRQ5
1: IRQ7
When bit 4 of PNP0 register is ‘‘0’’ this bit is ignored, i.e., it does not determine Parallel Port interrupt mapping.
Bit 6
Parallel Port’s LPTA base address selection control.
This bit enables software configuration of LPTA
base address via LPTBA configuration register.
LPTA base address is selected when FAR.bit1 e
0 and FAR.bit0 e 1.
There is no change in selection of LPTB and
LPTC via bits 0–1 of FAR.
This bit is initialized to 0 during reset.
0: LPTA is always 3BCh.
This is the backward compatible mode with
previous SIOs.
1: LPTA base address is selected via LPTBA
configuration register.
Bit 7
Reserved.
2.6 POWER-DOWN OPTIONS
There are two methods for entering the power-down mode.
Both methods result in one of the two possible modes. This
section associates the methods of entering power-down
with the resulting mode.
Mode 1: The internal clock stops for a specific function (i.e.,
UART1 and/or UART2 and/or FDC).
This mode is entered by any of the following actions:
1. Clear the FER bit for the specific function that is powered
down. See Section 2.5.1 FER bits 1 – 3.
2. During reset, set certain CFG 0 – 4 pins. See Table 2-1.
3. Execute the FDC Mode Command with PTR bit 1 e 0
(XTAL/CLK). See Section 4.2.6 LOW PWR.
4. Set Data Rate Select Register bit 6, in the FDC, high,
with PTR bit 1 e 0. See Section 3.6 bit 6.
Mode 2: The internal clocks are stopped for all enabled
functions.
Note: Clocks to disabled functions are always inactive.
2.5.23 Plug and Play Configuration 1 Register (PNP1,
Index e 1Ch)
This mode is entered by any of the following actions:
1. Clear all FER bits for any enabled function. See Section
2.5.1 FER bits 1 – 3.
2. Clear PTR bits 1 (XTAL/CLK) and 2 (CSOUT/PWDN select). Then assert the PWDN signal low. See Section
2.5.3 PTR bits 1,2 and Section 1.0 PWDN pin.
Upon reset the implemented bits are initialized to 0.
Bit 0
UART1’s and UART2’s interrupt selection control.
26
2.0 Configuration Registers (Continued)
3.0 FDC Register Description
3. Clear PTR bit 1 and then set PTR bit 0 (power-down)
high. See Section 2.5.3 PTR bits 0 and 1.
The floppy disk controller is suitable for all PC-AT, EISA,
PS/2, and general purpose applications. The operational
mode (PC-AT, PS/2, and Model 30) of the FDC is determined by bits 7, 6 of ASC register. AT mode is the default.
DP8473 and N82077 software compatibility is provided. Key
features include a 16-byte FIFO, PS/2 diagnostic register
support, perpendicular recording mode, CMOS disk interface, and a high performance analog data separator. See
Figure 3-1 .
The FDC supports the standard PC data rate drives of 250/
500 kbps, 300/500 kbps, and 1 Mbps in MFM-encoded data
mode, but is no longer guaranteed through functional testing to support the older FM encoded data mode. References to the older FM mode remain in this document to
clarify the true functional operation of the device.
The 1 Mbps data rate is used by the high performance tape
and floppy drives. The FDC supports these floppy drives
which utilize high density media, and require the perpendicular recording mode format. When used with the 1 Mbps
data rate, this new format allows the use of 4 MB floppy
drives which format Extra Density (ED) media to 2.88 MB
capacity.
The high performance internal analog data separator needs
no external components. It improves on the window margin
performance standards of the DP8473, and is compatible
with the strict data separator requirements of floppy disk
and floppy-tape drives.
The FDC contains write precompensation circuitry that defaults to 125 ns for 250 kbps, 300 kbps, and 500 kbps and
to 41.67 ns for 1 Mbps. These values can be overridden in
software to disable write precompensationn or to provide
levels of precompensation up to 250 ns.
2.7 POWER-UP PROCEDURE AND CONSIDERATIONS
2.7.1 UART Power-Up
The clock signal to the UARTs is controlled through the
Configuration Registers (FER, PTR). In order to restore the
clock signal to one or both UARTs the following conditions
must exist:
1. The appropriate enable bit (FER 1,2) for the UART(s)
must be set
2. and the power-down bit (PTR 0) must not be set.
2.7.2 FDC Power-Up
The clock signal to the FDC is controlled through the Configuration Registers, the FDC Mode Command and the Data
Rate Select Register. In order to restore the clock signal to
the FDC the following conditions must exist:
1. The appropriate enable bit (FER 3) must be set
2. and the power-down bit (PTR 0) must not be set.
In addition to these conditions, one of the following must be
done to initiate the recovery from power-down mode:
1. Read the Main Status Register until the RQM bit (MSR7)
is set or
2. Write to the Data Rate Select Register and set the Software Reset bit (DSR7) or
3. Write to the Digital Output Register, clear and then set
the Reset bit (DOR2) or
4. Read the Data Register and the Main Status Register
until the RQM bit is set.
If the crystal has been stopped, read the RQM bit in the
Main Status Register until it is set. The RQM bit is not set
until the crystal has stabilized.
TL/C/12379 – 28
FIGURE 3-1. FDC Functional Block Diagram
27
3.0 FDC Register Description (Continued)
The FDC has internal 24 mA data bus buffers which allow
direct connection to the system bus. The internal 40 mA
totem-pole disk interface buffers are compatible with both
CMOS drive inputs and 150X resistor terminated disk drive
inputs.
D1
D0
3.1.2 Status Register B (SRB)
Read Only
This read-only diagnostic register is part of the PS/2 floppy
controller register set, and is enabled when in the PS/2
mode. The SRB can be read at any time when in PS/2
mode. In the PC-AT mode, D7 – D0 are TRI-STATE during a
mP read.
3.1 FDC CONTROL REGISTERS
The following FDC registers are mapped into the addresses
shown in Table 3-1 and described in the following sections.
The base address range is provided by the on-chip address
decoder pin. For PC-AT or PS/2 applications, the diskette
controller primary address range is 3F0 to 3F7h, and the
secondary address range is 370 to 377h. The FDC supports
three different register modes: the PC-AT mode, PS/2
mode (Micro Channel systems), and the Model 30 mode
(Model 30). See Section 5.2 for more details on how each
register mode is enabled. When applicable, the register definition for each mode of operation is given. If no special
notes are made, then the register is valid for all three register modes.
SRBÐPS/2 Mode
DESC
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
0
1
1
1
0
1
0
1
0
0
1
0
1
1
0
0
X
X
X
X
X
X
X
X
R
R
R/W
R/W
R
W
R/W
X
R
W
D7
D6
D5
Register
Status Register A*
SRA
Status Register B*
SRB
Digital Output Register
DOR
Tape Drive Register
TDR
Main Status Register
MSR
Data Rate Select Register
DSR
Data Register (FIFO)
FIFO
None (Bus TRI-STATE)
Digital Input Register
DIR
Configuration Control Register CCR
D4
D3
D2
D1
*Note: SRA and SRB are enabled by IDENT e 0 during a chip reset only.
3.1.1 Status Register A (SRA)
Read Only
This is a read-only diagnostic register that is part of the
PS/2 floppy controller register set, and is enabled when in
the PS/2 mode. This register monitors the state of the IRQ6
pin and some of the disk interface signals. The SRA can be
read at any time when in PS/2 mode. In the PC-AT mode,
D7 – D0 are TRI-STATE during a mP read.
D0
RESET
COND
D7
D6
D5
D4
D3
D2
D7
D6
D5
D4
D3
D2
D1
D0
IRQ6
PEND
RES
STEP
TRK0
HDSEL
INDX
WP
DIR
0
N/A
0
N/A
0
N/A
N/A
0
D6
1
1
D5
D4
D3
D2
D1
D0
DR0 WDATA RDATA WGATE MTR1 MTR0
0
0
0
0
0
0
Reserved: Always 1.
Reserved: Always 1.
Drive Select 0: Reflects the status of the Drive Select 0 bit in the DOR (address 2, bit 0). It is cleared
after a hardware reset, not a software reset.
Write Data: Every inactive edge transition of the
WDATA disk interface output causes this bit to
change states.
Read Data: Every inactive edge transition of the
RDATA disk interface output causes this bit to
change states.
Write Gate: Active high status of the WGATE disk
interface output.
Motor Enable 1: Active high status of the MTR1
disk interface output. Low after a hardware reset,
unaffected by a software reset.
Motor Enable 0: Active high status of the MTR0
disk interface output. Low after a hardware reset,
unaffected by a software reset.
3.1.3 Digital Output Register (DOR)
Read/Write
The DOR controls the drive select and motor enable disk
interface outputs, enables the DMA logic, and contains a
software reset bit. The contents of the DOR is set to 00h
after a hardware reset, and is unaffected by a software reset. The DOR can be written to at any time.
SRAÐPS/2 Mode
DESC
D7
RESET
N/A N/A
COND
TABLE 3-1. Register Description and Addresses
A2 A1 A0 IDENT R/W
Write Protect: Active low status of the WP disk interface input.
Direction: Active high status of the DIR disk interface output.
DOR
D7
DESC
Interrupt Pending: This active high bit reflects the
state of the IRQ6 pin.
Reserved.
Step: Active high status of the STEP disk interface
output.
Track 0: Active low status of the TRK0 disk interface input.
Head Select: Active high status of the HDSEL disk
interface output.
Index: Active low status of the INDEX disk interface
input.
RESET
COND
D7
D6
D5
D4
28
D6
D5
D4
D3
D2
D1
D0
DRIVE DRIVE
MTR3 MTR2 MTR1 MTR0 DMAEN RESET
SEL 1 SEL 0
0
0
0
0
0
0
0
0
Motor Enable 3: This bit controls the MTR3 disk
interface output. A 1 in this bit causes the MTR3 pin
to go active.
Motor Enable 2: Same function as D7 except for
MTR2.
Motor Enable 1: Same function as D7 except for
MTR1. (See bit 4 of FCR for further information.)
Motor Enable 0: Same function as D7 except for
MTR0. (See bit 4 of FCR for further information.)
3.0 FDC Register Description (Continued)
D3
DMA Enable: This bit has two modes of operation.
3.1.4 Tape Drive Register (TDR)
PC-AT mode: Writing a 1 to this bit enables the
FDRQ, FDACK, TC, and IRQ6 pins. Writing a 0 to
this bit disables the FDACK and TC pins and TRISTATE the FDRQ and the IRQ6 pins. This bit is a 0
after a reset when in these modes.
The TDR register is the Tape Drive Register and the floppy
disk controller media and drive type register. The register
has three modes of operation (see Table 3-3):
PC-AT Compatible mode. The register is used to assign a
particular drive number to the tape drive support mode of
the data separator. All other logical drives can be assigned
as floppy drive support. Bits 2 – 7 are TRI-STATE during
read.
Automatic Media Sense mode. Bits 5 – 7 are implemented,
in addition to the bits of the Compatible PC-AT TDR mode.
Bits 2 – 4 are reserved.
Enhanced mode. This is the PS/2 TDR mode. It uses all
the register’s bits for operation with PS/2 floppy drives.
The use of the TDR bits, for each of these modes, is shown
in Table 3-3.
D7
Extra Density: When bit 5 is 0, this media id bit is
used with bit 6 to indicate the type of media currently in the active floppy drive. If bit 5 is 1, it is invalid.
This bit holds MSEN1 pin value. See Table 3-4 for
details regarding bits 5 – 7.
D6
High Density: When bit 5 is 0, this media id bit is
used with bit 7 to indicate the type of media currently in the active floppy drive. If bit 5 is 1, it is invalid.
This bit holds MSEN0 pin value. See Table 3-4 for
details regarding bits 5 – 7.
PS/2 mode: This bit is reserved, and the FDRQ,
FDACK, TC, and IRQ6 pins are always enabled. During a reset, the FDRQ, FDACK, TC, and IRQ6 lines
remain enabled, and D3 is 0.
D2
Reset Controller: Writing a 0 to this bit resets the
controller. It remains in the reset condition until a 1
is written to this bit. A software reset does not affect
the DSR, CCR, and other bits of the DOR. A software reset affects the Configure and Mode command bits (see Section 4.0 FDC Command Set Description). The minimum time that this bit must be
low is 100 ns. Thus, toggling the Reset Controller bit
during consecutive writes to the DOR is an acceptable method of issuing a software reset.
D1, 0 Drive Select: These two bits are binary encoded for
the four drive selects DR0–DR3, so that only one
drive select output is active at a time. (See bit 4 of
FCR for further information.)
It is common programming practice to enable both the motor enable and drive select outputs for a particular drive.
Table 3-2 shows the DOR values to enable each of the four
drives.
Read/Write
TABLE 3-2. Drive Enable Values
Drive
DOR Value
0
1Ch
1
2D
2
4E
3
8F
Note: The MTR3, MTR2, DRV3, DRV2 pins are only available in four-drive
mode (bit 4 of FER is 1) and require external logic.
TABLE 3-3. TDR Operation Modes
Mode
PC-AT Compatible
Automatic Media Sense
Enhanced
FCR
Bit 0
1
0
0
or
1
ASC
Bit 2
Bit
D7
D6
D5
D4
D3
D2
D1
D0
DESC
X
X
X
X
X
X
TAPE
SEL 1
TAPE
SEL 0
RESET
COND
N/A
N/A
N/A
N/A
N/A
N/A
0
0
DESC
ED
HD
VALID
DATA
X
X
X
TAPE
SEL 1
TAPE
SEL 0
RESET
COND
N/A
N/A
N/A
N/A
N/A
N/A
0
0
DESC
ED
HD
VALID
DATA
X
SWP1
SWP0
TAPE
SEL 1
TAPE
SEL 0
RESET
COND
N/A
N/A
N/A
1
0
0
0
0
0
0
1
29
3.0 FDC Register Description (Continued)
D5
Valid Data:
3.1.5 Main Status Register (MSR)
Automatic Media Sense mode: The state of bit 5
is determined by the state of the VLD0,1 bits in the
ASC Configuration Register. If this bit is 0, there is
valid media id sense data in bits 7 and 6 of this
register. Bit 5 holds VLD0 when drive 0 is accessed,
and media sense is configurfed. It holds VLD1 when
drive 1 is accessed, and media sense is configured.
Otherwise, it is set to 1 to indicate that media information is not available. Valid data should be used
only when accessing drives 0 and 1. See Table 3-4
for details regarding bits 5–7.
PC-AT Compatible mode: When four drive encoding is used (FER4 e 1), this bit is set to 1.
The read-only Main Status Register indicates the current
status of the disk controller. The Main Status Register is
always available to be read. One of its functions is to control
the flow of data to and from the Data Register (FIFO). The
Main Status Register indicates when the disk controller is
ready to send or receive data through the Data Register. It
should be read before each byte is transferred to or from
the Data Register except during a DMA transfer. No delay is
required when reading this register after a data transfer.
After a hardware or software reset, or recovery from a power-down state, the Main Status Register is immediately
available to be read by the mP. It contains a value of 00h
until the oscillator circuit has stabilized, and the internal registers have been initialized. When the FDC is ready to receive a new command, it reports an 80h to the mP. The
system software can poll the MSR until it is ready. The worst
case time allowed for the MSR to report an 80h value (RQM
set) is 2.5 ms after reset or power up.
TABLE 3-4. Media ID Bits Functions
Bit 7
Bit 6
Bit 5
Media Type
X
X
1
Invalid Data
0
0
0
5.25×
0
1
0
2.88M
1
0
0
1.44M
1
D4
D3, 2
D1, 0
1
0
MSR
720k
Reserved.
Bits 3 and 2 are read/write bits that control bits control logical drive exchange.
When working with four drives encoding (bit 4 of
FER is 1) the logical drive exchange is not performed.
00: No logical drive exchange.
01: Logical drive exchange between drives 0 and 1.
DR1 internal signal to DR0 pin.
D7
D6
D5
D4
D3
D2
D1
D0
DESC
RQM
DIO
NON
DMA
CMD
PROG
DRV3
BUSY
DRV2
BUSY
DRV1
BUSY
DRV0
BUSY
RESET
COND
0
0
0
0
0
0
0
0
D7
MTR1 internal signal to MTR0 pin.
DR0 internal signal to DR1 pin.
MTR0 internal signal to MTR1 pin.
10: Logical drive exchange between drives 0 and 2.
The DR0 and MTR0 pins function is exchanged
as follows:
DR2 internal signal to DR0 pin.
D6
MTR2 internal signal to MTR0 pin.
11: Reserved. Unpredictable results when 11 is
configured.
Tape Select 1, 0: These bits assign a logical drive
number to a tape drive. Drive 0 is not available as a
tape drive and is reserved as the floppy disk boot
drive. See Table 3-5 for the tape drive assignment
values.
D4
D5
D3
TABLE 3-5. Tape Drive Assignment Values
TAPESEL1
TAPESEL0
Drive
Selected
0
0
None
0
1
1
1
0
2
1
1
3
Read Only
D2
D1
D0
30
Request for Master: Indicates that the controller is
ready to send or receive data from the mP through
the FIFO. This bit is cleared immediately after a byte
transfer and is set again as soon as the disk controller is ready for the next byte. During a Non-DMA
Execution phase, the RQM indicates the status of
the interrupt pin.
Data I/O (Direction): Indicates whether the controller is expecting a byte to be written to (0) or read
from (1) the Data Register.
Non-DMA Execution: Indicates that the controller
is in the Execution Phase of a byte transfer operation in the Non-DMA mode. This mode can be used
for multiple byte transfers by the mP in the Execution Phase via interrupts or software polling.
Command in Progress: This bit is set after the first
byte of the Command Phase is written. This bit is
cleared after the last byte of the Result Phase is
read. If there is no Result Phase in a command, the
bit is cleared after the last byte of the Command
Phase is written.
Drive 3 Busy: Set after the last byte of the Command Phase of a Seek or Recalibrate command is
issued for drive 3. Cleared after reading the first
byte in the Result Phase of the Sense Interrupt
Command for this drive.
Drive 2 Busy: Same as above, but for drive 2.
Drive 1 Busy: Same as above, but for drive 1.
Drive 0 Busy: Same as above, but for drive 0.
3.0 FDC Register Description (Continued)
3.1.6 Data Rate Select Register (DSR)
TABLE 3-7. Default Precompensation Delays
Write Only
This write-only register is used to program the data rate,
amount of write precompensation, power-down mode, and
software reset. The data rate is programmed via the CCR,
not the DSR, for PC-AT and PS/2 Model 30 and MicroChannel applications. Other applications can set the data rate in
the DSR. The data rate of the floppy controller is determined by the most recent write to either the DSR or CCR.
The DSR is unaffected by a software reset. A hardware reset sets the DSR to 02h, which corresponds to the default
precompensation setting and 250 kbps.
Data Rate
1 Mbps
41.7 ns
500 kbps
125.0 ns
300 kbps
125.0 ns
250 kbps
125.0 ns
Data Rate Select 1,0: These bits determine the
data rate for the floppy controller. See Table 3-8 for
the corresponding data rate for each value of D1,
D0. The data rate select bits are unaffected by a
software reset, and are set to 250 kbps after a hardware reset.
D1, 0
DSR
D7
RESET
COND
D7
D6
D5
D4 – 2
D6
D5
D4
D3
D2
D1
D0
S/W
LOW
PREPREPRE0
DRATE1 DRATE0
RESET POWER
COMP2 COMP1 COMP0
DESC
Precompensation Delay
TABLE 3-8. Data Rate Select Encoding
0
0
0
0
0
0
1
0
Data Rate Select
Software Reset: This bit has the same function as
the DOR RESET (D2) except that this software reset is self-clearing.
Low Power: A 1 to this bit puts the controller into
the Manual Low Power mode. The oscillator and
data separator circuits are turned off. Manual Low
Power can also be accessed via the Mode command. The chip comes out of low power after a software reset, or access to the Data Register or Main
Status Register.
Undefined. Should be set to 0.
Precompensation Select: These three bits select
the amount of write precompensation the floppy
controller uses on the WDATA disk interface output.
Table 3-6 shows the amount of precompensation
used for each bit pattern. In most cases, the default
values (Table 3-7) can be used; however, alternate
values can be chosen for specific types of drives
and media. Track 0 is the default starting track number for precompensation. The starting track number
can be changed in the Configure command.
0.0 ns
001
41.7 ns
010
83.3 ns
011
125.0 ns
100
166.7 ns
101
208.3 ns
110
250.0 ns
000
DEFAULT
MFM
1
1
1 Mbps
FM
0
0
500 kbps
250 kbps
0
1
300 kbps
150 kbps
1
0
250 kbps
125 kbps
Illegal
3.1.7 Data Register (FIFO)
Read/Write
The FIFO (read/write) is used to transfer all commands,
data, and status between the mP and the FDC. During the
Command Phase, the mP writes the command bytes into the
FIFO after polling the RQM and DIO bits in the MSR. During
the Result Phase, the mP reads the result bytes from the
FIFO after polling the RQM and DIO bits in the MSR.
Enabling the FIFO, and setting the FIFO threshold, is done
via the Configure command. If the FIFO is enabled, only the
Execution Phase byte transfers use the 16 byte FIFO. The
FIFO is always disabled during the Command and Result
Phases of a controller operation. A software reset will not
disable enabled FIFO if the LOCK bit is set in the Lock
Command. After a hardware reset, the FIFO is disabled to
maintain compatibility with PC-AT systems.
The 16-byte FIFO can be used for DMA, Interrupt, or software polling type transfers during the execution of a read,
write, format, or scan command. In addition, the FIFO can
be put into a Burst or Non-Burst mode with the Mode command. In the Burst mode, FDRQ or IRQ6 remains active
until all of the bytes have been transferred to or from the
FIFO. In the Non-Burst mode, FDRQ or IRQ6 is deasserted
for 350 ns to allow higher priority transfer requests to be
serviced. The Mode command can also disable the FIFO for
either reads or writes separately. The FIFO allows the system a larger latency without causing a disk overrun/underrun error. The FIFO is typically used with multitasking operating systems and/or when running systems at
or above a 1 Mbps data rate. In its default state, the FIFO is
disabled and contains a zero threshold. The default state is
entered after a hardware reset.
Precompensation Delay
111
0
Note: FM mode is not guaranteed by functional testing.
TABLE 3-6. Write Precompensation Delays
Bits 4, 3, 2
Data Rate
1
31
3.0 FDC Register Description (Continued)
DIRÐPS/2 Mode
Data Register (FIFO)
D7
D6
D5
D4
D3
DESC
Data [7:0]
RESET
COND
Byte Mode
D2
D1
D0
D7
During the Execution Phase of a command involving data
transfer to/from the FIFO, the system must respond to a
data transfer service request based on the following formula:
RESET
COND
N/A
D0
D7
D6
D5
D4
D3
D2
D1
DSKCHG
X
X
X
X
X
X
X
RESET
COND
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
D4
1
D3
1
1
N/A N/A N/A N/A
D2
D1
D0
HIGH
DRATE1 DRATE0
DEN
N/A
N/A
1
Disk Changed: Active high status of DSKCHG disk
interface input. During power-down this bit is invalid,
if it is read by the software.
Reserved: Always 1.
Data Rate Select 1,0: These bits indicate the
status of the DRATE1 – 0 bits programmed through
the DSR or CCR.
High Density: This bit is low when the 1 Mbps or
500 kbps data rate is chosen, and high when the
300 kbps or 250 kbps data rate is chosen. This bit is
independent of the IDENT value.
CCRÐPC-AT and PS/2 Modes
D7
D6
D5
D4
D3
D2
D1
D0
DESC
0
0
0
0
0
0
DRATE1
DRATE0
RESET
COND
N/A
N/A
N/A
N/A
N/A
N/A
1
0
D7 – 2
D1, 0
Reserved: Should be set to 0.
Data Rate Select 1,0: These bits determine the
data rate of the floppy controller. See Table 3-8 for
the appropriate values.
3.2 RESULT PHASE STATUS REGISTERS
The Result Phase of a command contains bytes that hold
status information. The format of these bytes is described
below. Do not confuse these status bytes with the Main
Status Register, which is a read only register that is always
valid. The Result Phase status registers are read from the
Data Register (FIFO) only during the Result Phase of certain
commands (see Section 4.1 Command Set Summary). The
status of each register bit is indicated when the bit is a 1.
DIRÐPC-AT Mode
DESC
D5
3.1.9 Configuration Control Register (CCR) Write Only
This is the write-only data rate register commonly used in
PC-AT applications. This register is not affected by a software reset, and is set to 250 kbps after a hardware reset.
The data rate of the floppy controller is determined by the
last write to either the CCR or DSR.
3.1.8 Digital Input Register (DIR)
Read Only
This diagnostic register is used to detect the state of the
DSKCHG disk interface input and some diagnostic signals.
The function of this register depends on its mode of operation. When in the PC-AT mode, the D6–D0 are TRI-STATE
to avoid conflict with the fixed disk status register at the
same address. DIR is unaffected by a software reset.
D6 – 0
DSKCHG
D6 – 3
D2, 1
This formula is good for all data rates with the FIFO enabled
or disabled. THRESH is a four bit value programmed in the
Configure command, which sets the FIFO threshold. If the
FIFO is disabled, THRESH is zero in the above formula. The
last term of the formula, (16 c tICP) is an inherent delay due
to the microcode overhead required by the FDC. This delay
is also data rate dependent. See Table 9-1 for the tDRP and
tICP times. See Section 12.2.2 for a description of tDRP and
tICP.
The programmable FIFO threshold (THRESH) is useful in
adjusting the floppy controller to the speed of the system. In
other words, a slow system with a sluggish DMA transfer
capability uses a high value of THRESH, giving the system
more time to respond to a data transfer service request
(FDRQ for DMA mode or IRQ6 for Interrupt mode). Conversely, a fast system with quick response to a data transfer
service request would use a low value of THRESH.
D7
DESC
D7
Maximum Allowable Data Transfer Service Time
[(THRESH a 1) c 8 c tDRP] b (16 c tICP)
D6
D0
Disk Changed: Active high status of DSKCHG disk
interface input. During power-down this bit is invalid,
if it is read by the software.
Unused by the FDC (at TRI-STATE). The bits are
used by the Hard Disk Controller Status Register.
32
3.0 FDC Register Description (Continued)
D4
3.2.1 Status Register 0 (ST0)
D7
D6
D5
D4
D3
D2
D1
D0
DESC
IC
IC
SE
EC
0
HDS
DS1
DS0
RESET
COND
0
0
0
0
0
0
0
0
D7, 6
D5
D4
D3
D2
D1, 0
D3
D2
Interrupt Code:
00 e Normal Termination of Command.
01 e Abnormal Termination of Command. Execution of command was started, but was not
successfully completed.
10 e Invalid Command Issued. Command issued
was not recognized as a valid command.
11 e Internal drive ready status changed state during the drive polling mode. Only occurs after
a hardware or software reset.
Seek End: Seek, Relative Seek, or Recalibrate
command completed by the controller. (Used during
a Sense Interrupt command.)
Equipment Check: After a Recalibrate command,
Track 0 signal failed to occur. (Used during Sense
Interrupt command.)
Not Used. Always 0.
Head Select: Indicates the active high status of the
HDSEL pin at the end of the Execution Phase.
Drive Select 1,0: These two binary encoded bits
indicate the logical drive selected at the end of the
Execution Phase.
00 e Drive 0 selected.
D1
D0
3.2.3 Status Register 2 (ST2)
D7
D6
D5
D4
D3
D2
D1
D0
DESC
0
CM
CD
WT
SEH
SNS
BT
MD
RESET
COND
0
0
0
0
0
0
0
0
D7
D6
01 e Drive 1 selected.
10 e Drive 2 selected.
11 e Drive 3 selected.
3.2.2 Status Register 1 (ST1)
D7
D6
D5
D4
D3
D2
D1
D0
DESC
ET
0
CE
OR
0
ND
NW
MA
RESET
COND
0
0
0
0
0
0
0
0
D7
D6
D5
Overrun: Controller was not serviced by the mP
soon enough during a data transfer in the Execution
Phase. For read operations, indicates a data overrun. For write operations, indicates a data underrun.
Not Used. Always 0.
No Data: Three possible problems:
1. Controller cannot find the sector specified in the
Command Phase during the execution of a
Read, Write, Scan, or Verify command. An address mark was found however, so it is not a
blank disk.
2. Controller cannot read any Address Fields without a CRC error during a Read ID command.
3. Controller cannot find starting sector during execution of Read A Track command.
Not Writable: Write Protect pin is active when a
Write or Format command is issued.
Missing Address Mark: If bit 0 of ST2 is clear then
the controller cannot detect any Address Field Address Mark after two disk revolutions. If bit 0 of ST2
is set then the controller cannot detect the Data
Field Address Mark after finding the correct Address Field.
D5
D4
End of Track: Controller transferred the last byte of
the last sector without the TC pin becoming active.
The last sector is the End of Track sector number
programmed in the Command Phase.
Not Used. Always 0.
CRC Error: If this bit is set and bit 5 of ST2 is clear,
then there was a CRC error in the Address Field of
the correct sector. If bit 5 of ST2 is also set, then
there was a CRC error in the Data Field.
D3
D2
D1
33
Not Used. Always 0.
Control Mark: Controller tried to read a sector
which contained a deleted data address mark during execution of Read Data or Scan commands. Or,
if a Read Deleted Data command was executed, a
regular address mark was detected.
CRC Error in Data Field: Controller detected a
CRC error in the Data Field. Bit 5 of ST1 is also set.
Wrong Track: Only set if desired sector is not
found, and the track number recorded on any sector
of the current track is different from the track address specified in the Command Phase.
Scan Equal Hit: ‘‘Equal’’ condition satisfied during
any Scan command.
Scan Not Satisfied: Controller cannot find a sector
on the track which meets the desired condition during any Scan command.
Bad Track: Only set if the desired sector is not
found, the track number recorded on any sector on
the track is FFh indicating a hard error in IBM format, and is different from the track address specified in the Command Phase.
Command Phase:
3.0 FDC Register Description (Continued)
D0
Missing Address Mark in Data Field: Controller
cannot find the Data Field AM during a Read, Scan,
or Verify command. Bit 0 of ST1 is also set.
3.2.4 Status Register 3 (ST3)
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
EIS
FIFO
POLL
THRESH
PRETRK
D7
D6
D5
D4
D3
D2
D1
D0
DESC
0
WP
1
TK0
1
HDS
DS1
DS0
RESET
COND
0
0
1
0
1
0
0
0
Execution Phase: Internal registers written.
Result Phase: None.
EIS: Enable Implied Seeks. Default after a software reset.
# 0 e Implied seeks disabled through Configure comNot Used. Always 0.
Write Protect: Indicates active high status of the WP
pin.
D5
Not Used. Always 1.
D4
Track 0: Indicates active high status of the TRK0 pin.
D3
Not Used. Always 1.
D2
Head Select: Indicates the active high status of the
HD bit in the Command Phase.
D1, 0 Drive Select 1,0: These two binary encoded bits indicate the DS1–DS0 bits in the Command Phase.
D7
D6
mand. Implied seeks can still be enabled through
the Mode command when EIS e 0.
1 e Implied seeks enabled for a read, write, scan, or
verify operation. A seek and sense interrupt operation is performed prior to the execution of the
read, write, scan, or verify operation. The IPS bit
does not need to be set.
FIFO: Enable FIFO for Execution Phase data transfers. Default after a software reset if the LOCK bit is 0. If the
LOCK bit is 1, then the FIFO bit retains its previous
value after a software reset.
0 e FIFO enabled for both reads and writes.
4.0 FDC Command Set Description
# 1 e FIFO disabled.
POLL: Disable for Drive Polling Mode. Default after a software reset.
This section presents the FDC command setÐfull description in Section 4.1 and a working summary in Section 4.2.
Each command contains a unique first command byte, the
opcode byte, which tells the controller how many (0 or
more) command bytes to expect. The information for each
command is displayed using the structure shown in Figure
4-1 .
If an invalid command byte is issued to the controller, it
immediately enters the Result Phase and the status is 80h
signifying an Invalid Command.
# 0 e Enable drive polling mode. An interrupt is generated after a reset.
1 e Disable drive polling mode. If the Configure
command is issued within 500 ms of a hardware or software reset, then an interrupt is not
generated. In addition, the use of the four
Sense Interrupt commands to clear the ‘‘Ready
Changed State’’ of the four logical drives is not
required.
THRESH: The FIFO threshold in the Execution Phase of
read and write data transfers. Programmable
from 00h to 0Fh. Defaults to 00h after a software
reset if the LOCK bit is 0. If the LOCK bit is 1,
THRESH retains its value. A high value of
THRESH is suited for slow response systems,
and a low value of THRESH is better for fast
response systems.
PRETRK: Starting track number for write precompensation.
Programmable from track 0 (‘‘00’’) to track 255
(‘‘FF’’). Defaults to track 0 (‘‘00’’) after a software reset if the LOCK bit is 0. If the LOCK bit is
1, then PRETRK retains its value.
I/O Operation
Opcode
Command Byte 1
Command Byte 2
.
.
.
Command Byte n
FIGURE 4-1. FDC Command Structure
4.1 COMMAND DESCRIPTIONS
4.1.1 Configure Command
The Configure Command controls some operation modes of
the controller. It should be issued during the initialization of
the FDC after power-up. These bits are set to their default
values after a hardware reset. The value of each bit after a
software reset is explained. The default value of each bit is
denoted by a ‘‘bullet’’ to the left of each item.
4.1.2 Dumpreg Command
The Dumpreg command is designed to support system runtime diagnostics, application software development and debug. This command has a one-byte command phase and a
10-byte result phase. The Result Phase returns the values
of parameters set in other commands. That is, the PTR
(Present Track Register) contains the least significant byte
of the track the microcode has stored for each drive. The
Step Rate Time, Motor Off and Motor On Times, and the
DMA bit are all set in the Specify command.
34
4.0 FDC Command Set Description (Continued)
4. The Bytes per Sector code, which determines the sector
size.
The sixth byte of the result phase varies depending on what
commands have been previously executed. If a format command has previously been issued, and no reads or writes
have been issued since then, this byte contains the Sectors
per track value. If a read or a write command has been
executed more recently than a format command, this byte
contains the End of Track value. The LOCK bit is set in the
Lock command. The eighth result byte also contains the bits
programmed in the Perpendicular Mode command. The last
two bytes of the Dumpreg Result Phase are set in the Configure command. After a hardware or software reset, the
parameters in the result bytes are set to their appropriate
default values.
5. The Sector per Track parameter, which determines how
many sectors are formatted on the track.
6. The Data Pattern byte, which is used as the filler byte in
the Data Field of each sector.
Command Phase:
0
MFM
0
0
1
1
0
1
X
X
X
X
X
HD
DR1
DR0
Bytes per Sector
Sectors per Track
Note: Some of these parameters are unaffected by a software reset, depending on the state of the LOCK bit. See the Lock Command for
further information.
Format Gap
Data Pattern
Command Phase:
0
0
0
0
1
1
1
Execution Phase: System transfers four ID bytes (track,
head, sector, bytes/sector) per sector to the floppy controller via DMA or Non-DMA modes. The entire track is formatted. The data block in the Data Field of each sector is filled
with the data pattern byte.
0
Execution Phase: Internal registers read.
Result Phase:
Result Phase:
PTR Drive 0
PTR Drive 1
Status Register 0
PTR Drive 2
Status Register 1
Status Register 2
PTR Drive 3
Step Rate Time
Undefined
Motor Off Time
Motor On Time
Undefined
DMA
Undefined
Sector per Track/End of Track (Note)
LOCK
0
DC3
DC2
0
EIS
FIFO
POLL
DC1
DC0
GAP
Undefined
WG
THRESH
To allow for flexible formatting, the mP must supply the four
Address Field bytes (track, head, sector, bytes per sector
code) for each sector formatted during the Execution
Phase. This allows for non-sequential sector interleaving.
This transfer of bytes from the mP to the controller can be
done in the DMA or Non-DMA mode, with the FIFO enabled
or disabled.
The Format Gap byte in the Command Phase is dependent
on the data rate and type of disk drive, and controls the
length of GAP3. Some typical values for the programmable
GAP3 are given in Table 4-1. Figure 4-2 shows the track
format for each of the formats recognized by the format
command. Table 4-2 shows some typical values for the Format GAP3 based on media type. The Format command terminates when the index hole is detected a second time, at
which point an interrupt is generated. Only the first three
status bytes in the Result Phase are significant.
PRETRK
Note: Sectors per Track parameter returned if last command issued was
Format. End of Track parameter returned if last command issued was
Read or Write.
4.1.3 Format Track Command
This command formats one track on the disk in IBM, ISO, or
Perpendicular format. After the index hole is detected, data
patterns are written on the disk including all gaps, Address
Marks, Address Fields, and Data Fields. The exact format is
determined by the following parameters:
1. The MFM bit in the Opcode (first command) byte, which
determines the format of the Address Marks and the encoding scheme.
2. The IAF bit in the Mode command, which selects between IBM and ISO format.
3. The WGATE and GAP bits in the Perpendicular Mode
command, which select between the conventional and
Toshiba Perpendicular format.
35
4.0 FDC Command Set Description (Continued)
TABLE 4-1. Typical Format GAP3 Length Values Based on Drive Data Rate
Sector
Size
(Decimal)
Sector
Code
(Hex)
EOT
(Hex)
Sector
Gap
(Hex) (Note 1)
Format
GAP3
(Hex) (Note 2)
250 kbps
MFM
256
256
512
512
1024
2048
4096
01
01
02
02
03
04
05
12
10
08
09
04
02
01
0A
20
2A
2A
80
C8
C8
0C
32
50
50
F0
FF
FF
500 kbps
MFM
256
512
512
1024
2048
4096
8192
01
02
02
03
04
05
06
1A
0F
12
08
04
02
01
0E
1B
1B
35
99
C8
C8
36
54
6C
74
FF
FF
FF
Mode
Note 1: Sector Gap refers to the Intersector Gap Length parameter specified in the Command Phase of the Read, Write, Scan, and Verify commands. Although
this is the recommended value, the FDC treats this byte as a don’t care in the Read, Write, Scan, and Verify commands.
Note 2: Format Gap is the suggested value to use in the Format Gap parameter of the Format command. This is the programmable GAP3 as shown in Figure 4-1 .
TABLE 4-2. Typical Format GAP3 Length Values Based on PC Compatible Diskette Media
Media
Type
Sector
Size
(Decimal)
Sector
Code
(Hex)
EOT
(Hex
Sector
Gap
(Hex)
Format
GAP3
(Hex)
360k
1.2M
720k
1.44M
2.88M (Note 3)
512
512
512
512
512
02
02
02
02
02
09
0F
09
12
24
2A
1B
1B
1B
1B
50
54
50
6C
53
Note 3: The 2.88M diskette media is a Barium Ferrite media intended for use in Perpendicular Recording drives at data rates up to 1 Mbps.
36
4.0 FDC Command Set Description (Continued)
Notes:
TL/C/12379 – 29
CRC uses standard polynomial x16 a x12 a x5 a 1
A1* e Data Pattern of A1, Clock Pattern of 0A
C2* e Data Pattern of C2, Clock Pattern of 14
Perpendicular Format GAP2 e 41 bytes for 1 Mbps and 2 Mbps.
All byte counts in decimal
All other data rates use GAP2 e 22 bytes
All byte values in hex
FIGURE 4-2. IBM, Perpendicular, and ISO Formats Supported by the Format Command
ful if the system designer wishes to keep the FIFO enabled
and retain the other FIFO parameter values (such as
THRESH) after a software reset.
After the command byte is written, the result byte must be
read before continuing to the next command. The execution
of the Lock command is not performed until the result byte
is read by the mP. If the part is reset after the command byte
is written but before the result byte is read, then the Lock
command execution is not performed. This is done to prevent accidental execution of the Lock command.
4.1.4 Invalid Command
If an invalid command (illegal Opcode byte in the Command
Phase) is received by the controller, the controller responds
with ST0 in the Result Phase. The controller does not generate an interrupt during this condition. Bits 6 and 7 in the
MSR are both set to a 1, indicating to the mP that the controller is in the Result Phase and the contents of ST0 must
be read. The system reads an 80h value from ST0 indicating
an invalid command was received.
Command Phase:
Command Phase:
Invalid Op Codes
LOCK
0
0
1
0
1
0
0
Execution Phase: None.
Execution Phase: Internal Lock register is written.
Result Phase:
Result Phase:
Status Register 0 (80h)
0
4.1.5 Lock Command
The Lock command allows the user full control of the FIFO
parameters after a software reset. If the LOCK bit is set to 1,
then the FIFO, THRESH, and PRETRK bits in the Configure
command are not affected by a software reset. In addition,
the FWR, FRD, and BST bits in the Mode command are
unaffected by a software reset. If the LOCK is 0 (default
after a hardware reset), then the above bits are set to their
default values after a software reset. This command is use-
0
0
LOCK
0
0
0
0
4.1.6 Mode Command
This command is used to select the special features of the
controller. The bits for the Command Phase bytes are
shown in Section 4.1, Command Set Summary, and their
function is described below. These bits are set to their default values after a hardware reset. The default value of
each bit is denoted by a ‘‘bullet’’ to the left of each item. The
value of each parameter after a software reset is explained.
37
4.0 FDC Command Set Description (Continued)
# 0 e Enable FIFO. mP write transfers druing the Exe-
Command Phase:
0
0
0
0
0
TMR
IAF
IPS
0
FWR
FRD
BST
R255
BFR
WLD
0
0
DENSEL
0
0
0
0
1
LOW PWR
1
ETR
0
0
0
0
cution Phase use the internal FIFO.
1 e Disable FIFO. All write data transfers take place
without the FIFO.
FRD: FIFO Read Disable for mP read transfers from controller. Default after a software reset if LOCK is 0. If
LOCK is 1, FRD retains its value after a software reset.
Head Settle
0
RG
0
PU
Execution Phase: Internal registers are written.
Note: This bit is only valid if the FIFO is enabled in the Configure
command. If the FIFO is not enabled in the Configure command, then this bit is a don’t care.
Result Phase: None.
TMR: Motor Timer mode. Default after a software reset.
# 0 e Enable FIFO. mP read transfers during the Exe-
# 0 e Timers for motor on and motor off are defined
cution Phase use the internal FIFO.
1 e Disable FIFO. All read data transfers take place
without the FIFO.
BST: Burst Mode Disable. Default after a software reset if
LOCK is 0. If LOCK is 1, BST retains its value after a
software reset.
for Mode 1. (See Specify command.)
1 e Timers for motor on and motor off are defined
for Mode 2. (See Specify command.)
IAF: Index Address Format. Default after a software reset.
# 0 e The controller formats tracks with the Index Address Field included. (IBM and Perpendicular format.)
Note: This bit is only valid if the FIFO is enabled in the Configure
command. If the FIFO is not enabled in the Configure command, then this bit is a don’t care.
1 e The controller formats tracks without including
the Index Address Field. (ISO format.)
IPS: Implied Seek. Default after a software reset.
# 0 e Burst mode enabled for FIFO Execution Phase
data transfers.
1 e Non-Burst mode enabled. The DRQ or IRQ6 pin
is strobed once for each byte to be transferred
while the FIFO is enabled.
R255: Recalibrate Step Pulses. The bit determines the
maximum number of recalibrate step pulses the controller issues before terminating with an error. Default after a software reset.
# 0 e The implied seek bit in the command byte of a
read, write, scan, or verify is ignored. Implied
seeks could still be enabled by the EIS bit in the
Configure command.
1 e The IPS bit in the command byte of a read, write,
scan, or verify is enabled so that if it is set, the
controller performs seek and sense interrupt operations before executing the command.
# 0 e Maximum of 85 recalibrate step pulses. If ETR
e 1, controller issues 3925 recalibrate step
pulses maximum.
LOW
PWR: Low Power mode. Default after a software reset.
1 e Maximum of 255 recalibrate step pulses. If ETR
e 1, controller issues 4095 maximum recalibrate step pulses.
DENSEL: Density Select Pin Configuration. This 2-bit value
configures the Density Select output to one of
three possible modes. The default mode configures the DENSEL pin according to the state of bit
6 of ASC after a data rate has been selected.
That is, if ASC6 is high, the DENSEL pin is active
high for the 500 kbps and 1 Mbps data rates. If
ASC6 is low, the DENSEL pin is active low for the
500 kbps and 1 Mbps data rates. See Table 4-3.
In addition to these modes, the DENSEL output
can be set to always low or always high, as
shown in Table 4-4. This allows the user more
flexibility with new drive types.
# 00 e Completely disable the low power mode.
01 e Automatic low power. For 500 kbps operation,
go into low power mode 512 ms after the head
unload timer times out. For 250 kbps operation
the timeout period is doubled to 1s.
10 e Manual low power. Go into low power mode
now.
11 e Not used.
ETR: Extended Track Range. Default after a software reset.
# 0 e Track number is stored as a standard 8-bit value
compatible with the IBM, ISO, and Perpendicular
formats. This allows access of up to 256 tracks
during a seek operation.
1 e Track number is stored as a 12-bit value. The
upper four bits of the track value are stored in
the upper four bits of the head number in the
sector Address Field. This allows access of up to
4096 tracks during a seek operation. With this bit
set, an extra byte is required in the Seek Command Phase and Sense Interrupt Result Phase.
FWR: FIFO Write Disable for mP write transfers to controller. Default after a software reset if LOCK is 0. If
LOCK is 1, FWR retains its value after a software
reset.
TABLE 4-3. DENSEL Default Encoding
Data Rate
250 kbps
300 kbps
500 kbps
1 Mbps*
DENSEL Pin Definition
ASC6 e 1
ASC6 e 0
Low
Low
High
High
High
High
Low
Low
*When TUP bit 1 e 0, a Data Rate of 1 Mbps is selected.
Note: This bit is only valid if the FIFO is enabled in the Configure
command. If the FIFO is not enabled in the Configure command, then this bit is a don’t care.
38
4.0 FDC Command Set Description (Continued)
4.1.7 NSC Command
TABLE 4-4. DENSEL Encoding
Mode Command
Bit 1
Bit 0
DENSEL
Pin Definition
0
0
1
1
0
1
0
1
Pin Low
Pin High
Undefined
DEFAULT
The NSC command can be used to distinguish between the
FDC versions and the 82077. The Result Phase byte
uniquely identifies the floppy controller as a PC87306, which
returns a value of 73h. The 82077 and DP8473 return a
value of 80h, signifying an invalid command. The lower four
bits of this result byte are subject to change by National,
and reflects the particular version of the floppy disk controller part.
Command Phase:
BFR: CMOS Disk Interface Buffer Enable.
# 0 e Drive output signals configured as standard 4 mA
push-pull outputs (actually 40 mA sink, 4 mA
source).
1 e Drive output signals configured as 40 mA opendrain outputs.
WLD: Scan Wild Card.
0
0
Head
Settle: Time allowed for read/write head to settle after a
seek during an Implied Seek operation. This is controlled as shown in Table 4-5 by loading a 4-bit value
for N. (The default value for N is 8.)
TABLE 4-5. Head Settle Time Calculation
250
300
500
1000
Nc8
N c 6.666
Nc4
Nc2
0–120
0–100
0 – 60
0 – 30
1
0
0
0
1
1
1
0
0
1
1
4.1.8 Perpendicular Mode Command
The Perpendicular Mode command is designed to support
the unique Format and Write Data requirements of Perpendicular (Vertical) Recording disk drives (4 Mbyte unformatted capacity). The Perpendicular Mode command configures each of the four logical drives as a perpendicular or
conventional disk drive. Configuration of the four logical disk
drives is done via the D3 – 0 bits, or with the GAP and WG
control bits. This command should be issued during the initialization of the floppy controller.
1 e The Scan commands do not recognize FFh as a
wildcard character.
Head Settle
Time (ms)
1
Result Phase:
Scan command is interpreted as a wildcard
character that always matches true.
Multiplier
(4 Bit Value)
0
Execution Phase: None.
# 0 e An FFh from either the mP or the disk during a
Data Rate
(kbps)
0
Command Phase:
0
0
0
1
0
0
1
0
OW
0
DC3
DC2
DC1
DC0
GAP
WG
Execution Phase: Internal registers are written.
Result Phase: None.
Perpendicular Recording drives operate in ‘‘Extra High Density’’ mode at 1 Mbps and are downward compatible with
1.44 Mbyte and 720 kbyte drives at 500 kbps (High Density)
and 250 kbps (Double Density) respectively. If perpendicular
drives are present in the system, this command should be
issued during initialization of the floppy controller, which
configures each drive as perpendicular or conventional.
Then, when a drive is accessed for a Format or Write Data
command, the floppy controller adjusts the Format or Write
Data parameters based on the data rate selected (see Table 4-6).
RG: Read Gate Diagnostic.
# 0 e Enable DSKCHG disk interface input for normal
operation.
1 e Enable DSKCHG to act as an external Read Gate
input signal to the Data Separator. This is intended as a test mode to aid in evaluation of the Data
Separator.
PU: PUMP Pulse Output Diagnostic.
# 0 e Enable MFM output pin for normal operation.
1 e Enable the MFM output to act as the active low
output of the Data Separator charge pump. This
signal consists of a series of pulses indicating
when the phase comparator is making a phase
correction. This Pump output is active low for a
pump up or pump down signal from the phase
comparator, and is intended as a test mode to aid
in the evaluation of the Data Separator.
39
4.0 FDC Command Set Description (Continued)
TABLE 4-6. Effect of Drive Mode and Data Rate on Format and Write Commands
Drive
Mode
GAP2 Length
Written during
Format
Portion of GAP2
Re-Written by
Write Data Command
250 kbps/300 kbps/500 kbps
Conventional
Perpendicular
22 Bytes
22 Bytes
0 Bytes
19 Bytes
1 Mbps
Conventional
Perpendicular
22 Bytes
41 Bytes
0 Bytes
38 Bytes
Data Rate
TABLE 4-7. Effect of GAP and WG on Format and Write Commands
Mode
Description
GAP2 Length
Written during
Format
0
Conventional
22 Bytes
0 Bytes
1
Perpendicular
(500 kbps)
22 Bytes
19 Bytes
1
0
Reserved
(Conventional)
22 Bytes
0 Bytes
1
1
Perpendicular
(1 Mbps)
41 Bytes
38 Bytes
GAP
WG
0
0
Portion of GAP2
Re-Written by
Write Data Command
Format in Table 4-1.) This GAP2 length of 41 bytes (at
1 Mbps) ensures that the Preamble in the Data Field is completely ‘‘pre-erased’’ by the Pre-Erase Head. Also, during
Write Data operations to a perpendicular drive, a portion of
GAP2 must be rewritten by the controller to guarantee that
the Data Field Preamble has been pre-erased (see Table
4-6).
Looking at the second command byte, DC3–0 corresponds
to the four logical drives.
A 0 written to DCn sets drive n to conventional mode, and a
1 sets drive n to perpendicular mode. The OW (Overwrite)
bit offers additional control. When OW e 1, the values of
DC3 – 0 (drive configuration bits) are changeable. When OW
e 0, the internal values of DC3–0 are unaffected, regardless of what is written to DC3–0.
The function of the DCn bits must also be qualified by setting both WG and GAP to 0. If WG and GAP are used (i.e.,
not set to 00), they override whatever is programmed in the
DCn bits. Table 4-7 indicates the operation of the FDC
based on the values of GAP and WG. Note that when GAP
and WG are both 0, the DCn bits are used to configure each
logical drive as conventional or perpendicular. DC3–0 is unaffected by a software reset, but WG and GAP are both
cleared to 0 after a software reset. A hardware reset resets
all the bits to zero (conventional mode for all drives). The
Perpendicular Mode command bits may be rewritten at any
time.
4.1.9 Read Data Command
The Read Data command reads logical sectors containing a
Normal Data Address Mark (AM) from the selected drive
and makes the data available to the host mP. After the last
Command Phase byte is written, the controller simulates the
Motor On time for the selected drive internally. The user
must turn on the drive motor directly by enabling the appropriate drive and motor select disk interface outputs with the
Digital Output Register (DOR).
If Implied Seeks are enabled, the controller performs a Seek
operation to the track number specified in the Command
Phase. The controller also issues a Sense Interrupt for the
seek and waits the Head Settle time specified in the Mode
command.
The correct ID information (track, head, sector, bytes per
sector) for the desired sector must be specified in the command bytes. SeeTable4-8SectorSizeSelectionfordetailson
the bytes per sector code. In addition, the End of Track
Sector Number (EOT) should be specified, allowing the controller to read multiple sectors. The Data Length byte is a
don’t care and should be set to FFh.
Note: When in the Perpendicular Mode for any drive at any data rate selected by the DC3–0 bits, write precompensation is set to zero.
Perpendicular Recording type disk drives have a Pre-Erase
Head which leads the Read/Write Head by 200 mm, which
translates to 38 bytes at the 1 Mbps data transfer rate (19
bytes at 500 kbps). The increased spacing between the two
heads requires a larger GAP2 between the Address Field
and Data Field of a sector at 1 Mbps. (See Perpendicular
40
4.0 FDC Command Set Description (Continued)
Having finished reading the sector, the controller continues
reading the next logical sector unless one or more of the
following termination conditions occurred:
1. The DMA controller asserted TC. The IC bits in ST0 are
set to Normal Termination.
2. The last sector address (of side 1 if MT was set) was
equal to EOT. The EOT bit in ST1 is set. The IC bits in
ST0 are set to Abnormal Termination. This is the expected condition during Non-DMA transfers.
3. Overrun error. The OR bit in ST1 is set. The IC bits in ST0
are set to Abnormal Termination. If the mP cannot service
a transfer request in time, the last correctly read byte is
transferred.
4. CRC error. The CE bit in ST1 and the CD bit in ST2 are
set. The IC bits in ST0 are set to Abnormal Termination.
If Multi-Track Selector (MT) was set in the Opcode command byte, and the last sector of side 0 has been transferred, the controller then continues with side 1.
Upon terminating the Execution Phase of the Read Data
command, the controller asserts IRQ6, indicating the beginning of the Result Phase. The mP must then read the result
bytes from the FIFO. The values that are read back in the
result bytes are shown in Table 4-10. If an error occurs, the
result bytes indicate the sector read when the error occurred.
TABLE 4-8. Sector Size Selection
Bytes per
Sector Code
Number of Bytes
in Data Field
0
1
2
3
4
5
6
7
128
256
512
1024
2048
4096
8192
16384
The controller then starts the Data Separator and waits for
the Data Separator to find the next sector Address Field.
The controller compares the Address Field ID information
(track, head, sector, bytes per sector) with the desired ID
specified in the Command Phase. If the sector ID bytes do
not match, then the controller waits for the Data Separator
to find the next sector Address Field. The ID comparison
process repeats until the Data Separator finds a sector Address Field ID that matches that in the command bytes, or
until an error occurs. Possible errors are:
1. The mP aborted the command by writing to the FIFO. If
there is no disk in the drive, the controller hangs up. The
mP must then take the controller out of this hung state by
writing a byte to the FIFO. This puts the controller into the
Result Phase.
2. Two index pulses were detected since the search began,
and no valid ID has been found. If the track address ID
differs, the WT bit or BT bit (if the track address is FFh) is
set in ST2. If the head, sector, or bytes per sector code
did not match, the ND bit is set in ST1. If the Address
Field AM was never found, the MA bit is set in ST1.
3. The Address Field was found with a CRC error. The CE
bit is set in ST1.
Once the desired sector Address Field is found, the controller waits for the Data Separator to find the subsequent Data
Field for that sector. If the Data Field (normal or deleted) is
not found within the expected time, the controller terminates
the operation and enters the Result Phase (MD is set in
ST2). If a Deleted Data Mark is found and Skip Flag (SK)
was set in the Opcode command byte, the controller skips
this sector and searches for the next sector Address Field
as described above. The effect of SK on the Read Data
command is summarized in Table 4-9.
Having found the Data Field, the controller then transfers
data bytes from the disk drive to the host (described in
Section 5.3 Controller Phases) until the bytes per sector
count has been reached, or the host terminates the operation (through TC, end of track, or implicitly through overrun).
The controller then generates the CRC for the sector and
compares this value with the CRC at the end of the Data
Field.
Command Phase:
MT
MFM
SK
0
0
1
1
0
IPS
X
X
X
X
HD
DR1
DR0
Track Number
Drive Head Number
Sector Number
Bytes per Sector
End of Track Sector Number
Intersector Gap Length
Data Length
Execution Phase: Data read from disk drive is transferred
to system via DMA or Non-DMA modes.
Result Phase:
Status Register 0
Status Register 1
Status Register 2
Track Number
Head Number
Sector Number
Bytes per Sector
41
4.0 FDC Command Set Description (Continued)
TABLE 4-9. SK Effect on the Read Data Command
SK
Data Type
Sector Read ?
CM Bit (ST2)
0
Normal
Y
0
Normal Termination
Description of Results
0
Deleted
Y
1
No Further Sectors Read
1
Normal
Y
0
Normal Termination
1
Deleted
N
1
Sector Skipped
TABLE 4-10. Result Phase Termination Values with No Error
ID Information at Result Phase
MT
HD
Last
Sector
Track
Head
Sector
0
0
k EOT
NC
NC
Sa1
NC
0
0
e EOT
Ta1
NC
1
NC
0
1
k EOT
NC
NC
Sa1
NC
0
1
e EOT
Ta1
NC
1
NC
1
0
k EOT
NC
NC
Sa1
NC
1
0
e EOT
NC
1
1
NC
1
1
k EOT
NC
NC
Sa1
NC
1
1
e EOT
Ta1
0
1
NC
EOT e End of Track Sector Number from Command Phase
S e Sector Number last operated on by controller
NC e No Change in Value
T e Track Number programmed in Command Phase
Bytes/Sector
TABLE 4-11. SK Effect on the Read Deleted Data Command
SK
Data Type
Sector Read ?
CM Bit (ST2)
Description of Results
0
Normal
Y
1
No Further Sectors Read
0
Deleted
Y
0
Normal Termination
1
Normal
N
1
Sector Skipped
1
Deleted
Y
0
Normal Termination
Execution Phase: Data read from disk drive is transferred
to system via DMA or Non-DMA modes.
4.1.10 Read Deleted Data Command
The Read Deleted Data command reads logical sectors
containing a Deleted Data AM from the selected drive and
makes the data available to the host mP. This command is
identical to the Read Data command, except for the setting
of the CM bit in ST2 and the skipping of sectors. The effect
of SK on the Read Deleted Data command is summarized in
Table 4-11. See Table 4-10 for the state of the result bytes
for a Normal Termination of the command.
Result Phase:
Status Register 0
Status Register 1
Status Register 2
Track Number
Head Number
Command Phase:
Sector Number
MT
MFM
SK
0
1
1
0
0
IPS
X
X
X
X
HD
DR1
DR0
Bytes per Sector
4.1.11 Read ID Command
The Read ID command finds the next available Address
Field and returns the ID bytes (track, head, sector, bytes per
sector) to the mP in the Result Phase. There is no data
transfer during the Execution Phase of this command. An
interrupt is generated when the Execution Phase is completed.
Track Number
Drive Head Number
Sector Number
Bytes per Sector
End of Track Sector Number
Intersector Gap Length
Data Length
42
4.0 FDC Command Set Description (Continued)
4. Multi-track and Skip operations are not allowed. SK and
MT should be set to 0.
The controller first simulates the Motor On time for the selected drive internally. The user must turn on the drive motor
directly by enabling the appropriate drive and motor select
disk interface outputs with the Digital Output Register
(DOR). The Read ID command does not perform an implied
seek.
After waiting the Motor On time, the controller starts the
Data Separator and waits for the Data Separator to find the
next sector Address Field. If an error condition occurs, the
IC bits in ST0 are set to Abnormal Termination, and the
controller enters the Result Phase. Possible errors are:
1. The mP aborted the command by writing to the FIFO. If
there is no disk in the drive, the controller hangs up. The
mP must then take the controller out of this hung state by
writing a byte to the FIFO. This puts the controller into the
Result Phase.
2. Two index pulses were detected since the search began,
and no AM has been found. If the Address Field AM was
never found, the MA bit is set in ST1.
5. If there is a CRC error in the Data Field, the controller
sets CE in ST1 and CD in ST2, but continues reading
sectors.
6. The controller reads a maximum of EOT physical sectors.
There is no support for multi-track reads.
Command Phase:
0
MFM
0
0
0
0
1
0
IPS
X
X
X
X
HD
DR1
DR0
Track Number
Drive Head Number
Sector Number
Bytes per Sector
End of Track Sector Number
Intersector Gap Length
Data Length
Command Phase:
0
MFM
0
0
1
0
1
0
X
X
X
X
X
HD
DR1
DR0
Execution Phase: Data read from disk drive is transferred
to system via DMA or non-DMA modes.
Result Phase:
Execution Phase: Controller reads first ID Field header
bytes it can find and reports these bytes to the system in the
result bytes.
Status Register 0
Status Register 1
Result Phase:
Status Register 2
Track Number
Status Register 0
Status Register 1
Head Number
Status Register 2
Sector Number
Track Number
Bytes per Sector
Head Number
4.1.13 Recalibrate Command
The Recalibrate command is very similar to the Seek command. The controller sets the Present Track Register (PTR)
of the selected drive to zero. It then steps the head of the
selected drive out until the TRK0 disk interface input signal
goes active, or until the maximum number of step pulses
have been issued. See Table 4-12 for the maximum recalibrate step pulse values based on the R255 and ETR bits in
the Mode command. If the number of tracks on the disk
drive exceeds the maximum number of recalibrate step
pulses, another Recalibrate command may need to be issued.
Sector Number
Bytes per Sector
4.1.12 Read A Track Command
The Read A Track command reads sectors in physical order
from the selected drive and makes the data available to the
host. This command is similar to the Read Data command
with the following exceptions:
1. The controller waits for the index pulse before searching
for a sector Address Field. If the mP writes to the FIFO
before the index pulse, the command enters the Result
Phase with the IC bits in ST0 set to Abnormal Termination.
2. A comparison of the sector Address Field ID bytes will be
performed, except for the sector number. The internal
sector address is set to 1, and then incremented for each
successive sector read.
3. If the Address Field ID comparison fails, the controller
sets ND in ST1, but continues to read the sector. If there
is a CRC error in the Address Field, the controller sets CE
in ST1, but continues to read the sector.
TABLE 4-12. Maximum Recalibrate
Step Pulses Based on R255 and ETR
43
Maximum Recalibrate
Step Pulses
R255
ETR
0
0
1
0
255
0
1
3925
1
1
4095
85 (default)
4.0 FDC Command Set Description (Continued)
After the last command byte is issued, the DRx BUSY bit is
set in the MSR for the selected drive. The controller will
simulate the Motor On time, and then enter the Idle Phase.
The execution of the actual step pulses occur while the controller is in the Drive Polling Phase. An interrupt will be generated after the TRK0 signal is asserted, or after the maximum number of recalibrate step pulses are issued. There is
no Result Phase. Recalibrates should not be issued on
more than one drive at a time. This is because the drives are
actually selected via the DOR, which can only select one
drive at a time. No other command except the Sense Interrupt command should be issued while a Recalibrate command is in progress.
4.1.15 Scan Commands
The Scan commands allow data read from the disk to be
compared against data sent from the mP, using ones complement arithmetic, sector by sector.
There are three Scan commands to choose from:
1. Scan Equal: checks to see if the scanned value of the
disk data is equal to that of the mP data. The scan condition is therefore: disk data e mP data?
2. Scan Low or Equal: checks to see if the scanned value of the disk data is equal to or less than that of the mP
data. The scan condition is therefore: disk data s data?
3. Scan High or Equal: checks to see if the scanned value of the disk data is equal to or greater than that of the
mP data. The scan condition is therefore: disk data t
mP data?
The results of these comparisons are indicated in the Status
Register bits 3 and 2, see Table 4-13, and the structure of
the three commands follows.
Each sector is compared starting with the most significant
bytes first, and where the next sector is defined as the current Sector Number plus the Sector Step Size. Reading of
sectors continues until either the scan condition is met, the
End of Track (EOT) has been reached, or the Terminal
Count (TC) is asserted.
If the Wildcard mode is enabled in the Mode command, an
FFh from either the disk or the mP is used as a don’t care
byte that will always match equal. Read errors on the disk
will have the same error conditions as the Read Data command.
Additionally, if the Skip Flag (SK) bit is set, sectors with
deleted data marks will be ignored. If all sectors read are
skipped, the command will terminate with bit 3 of the Status
Register set (mimicking a Scan Equal Hit).
Command Phase:
0
0
0
0
0
1
1
1
0
0
0
0
0
0
DR1
DR0
Execution Phase: Disk drive head is stepped out to Track 0.
Result Phase: None.
4.1.14 Relative Seek Command
The Relative Seek command steps the selected drive in or
out a given number of steps. This command will step the
read/write head an incremental number of tracks, as opposed to comparing against the internal present track register for that drive.
Command Phase:
1
DIR
0
0
1
1
1
1
X
X
X
X
X
HD
DR1
DR0
Execution Phase: Disk drive head stepped in or out a programmable number of tracks.
Result Phase: None.
The Relative Seek parameters are defined as follows:
DIR: Read/Write Head Step Direction Control
0 e Step Head Out
TABLE 4-13. Scan Command Termination Values
Command
Comparison Status
Condition D3 D2
Scan Equal Disk Data e
mP Data?
1 e Step Head In
RTN: Relative Track Number. This value will determine how
many incremental tracks to step the head in or out
from the current track number.
The controller will issue RTN number of step pulses and
update the Present Track Register for the selected drive.
The one exception to this is if the TRK0 disk input goes
active, which indicates that the drive read/write head is at
the outermost track. In this case, the step pulses for the
Relative Seek are terminated, and the PTR value is set according to the actual number of step pulses issued. The
arithmetic is done modulo 255. The DRx BUSY bit in the
MSR is set for the selected drive. The controller will simulate the Motor On time before issuing the step pulses. After
the Motor On time, the controller will enter the Idle Phase.
The execution of the actual step pulses occurs in the Idle
Phase of the controller.
After the step operation is complete, the controller will generate an interrupt. There is no Result Phase. Relative Seeks
should not be issued on more than one drive at a time. This
is because the drives are actually selected via the DOR,
which can only select one drive at a time. No other command except the Sense Interrupt command should be issued while a Relative Seek command is in progress.
Scan Low
or Equal
Scan High
or Equal
44
Disk Data s
mP Data?
Disk Data t
mP Data?
Condition
Met?
Indicated
Result
1
0
Yes
Disk Data e
mP Data
0
1
No
Disk Data
mP Data
1
0
Yes
Disk Data e
mP Data
0
0
Yes
Disk Data k
mP Data
0
1
No
Disk Data l
mP Data
1
0
Yes
Disk Data e
mP Data
0
0
Yes
Disk Data l
mP Data
0
1
No
Disk Data k
mP Data
i
4.0 FDC Command Set Description (Continued)
SCAN LOW OR EQUAL
SCAN EQUAL
Command Phase:
Command Phase:
MT
MFM
SK
1
0
0
0
1
MT
MFM
SK
1
1
0
0
1
IPS
X
X
X
X
HD
DR1
DR0
IPS
X
X
X
X
HD
DR1
DR0
Track Number
Track Number
Drive Head Number
Drive Head Number
Sector Number
Sector Number
Bytes per Sector
Bytes per Sector
End of Track Sector Number
End of Track Sector Number
Intersector Gap Length
Intersector Gap Length
Sector Step Size
Sector Step Size
Execution Phase: Data transferred from system to controller is compared to data read from disk.
Execution Phase: Data transferred from system to controller is compared to data read from disk.
Result Phase:
Result Phase:
MT
MFM
SK
1
1
1
0
1
Status Register 0
IPS
X
X
X
X
HD
DR1
DR0
Status Register 1
Status Register 0
Status Register 2
Status Register 1
Track Number
Status Register 2
Head Number
Track Number
Sector Number
Head Number
Bytes per Sector
Sector Number
4.1.16 Seek Command
The Seek command steps the selected drive in or out until
the desired track number is reached. During the Execution
Phase of the Seek command, the track number to seek to is
compared with the present track number. The controller will
determine how many step pulses to issue, and the DIR disk
interface output will indicate which direction the R/W head
should move. The DRx BUSY bit is set in the MSR for the
appropriate drive. The controller will wait the Motor On time
before issuing the first step pulse.
After the Motor On time, the controller will enter the Idle
Phase. The execution of the actual step pulses occurs in the
Drive Polling phase of the controller. The step pulse rate is
determined by the value programmed in the Specify command. An interrupt will be generated one step pulse period
after the last step pulse is issued. A Sense Interrupt command should be issued to determine the cause of the interrupt. There is no Result Phase.
While the internal microengine is capable of performing
seek commands on 2 or more drives at the same time, software should ensure that only one drive is seeking at a time.
This is because the drives are actually selected via the
DOR, which can only select one drive at a time. No other
command except a Sense Interrupt command should be issued while a Seek command is in progress.
If the extended track range mode is enabled with the ETR
bit in the Mode command, a fourth command byte should be
written in the Command Phase to indicate the four most
significant bits of the desired track number. Otherwise, only
three command bytes should be written.
Bytes per Sector
SCAN HIGH OR EQUAL
Command Phase:
MT
MFM
SK
1
1
1
0
1
IPS
X
X
X
X
HD
DR1
DR0
Track Number
Drive Head Number
Sector Number
Bytes per Sector
End of Track Sector Number
Intersector Gap Length
Sector Step Size
Execution Phase: Data transferred from system to controller is compared to data read from disk.
Result Phase:
Status Register 0
Status Register 1
Status Register 2
Track Number
Head Number
Sector Number
Bytes per Sector
45
4.0 FDC Command Set Description (Continued)
3. The Ready Signal changed state during the polling mode
for an internally selected drive. (Occurs only after a hardware or software reset.)
4. A Seek, Relative Seek, or Recalibrate command terminates.
An interrupt due to reasons 1 or 2 does not require the
Sense Interrupt command and is cleared automatically. This
type of interrupt occurs during normal command operations
and is easily discernible by the mP via the MSR. It is cleared
when reading or writing information from or to the Data Register (FIFO).
An interrupt caused by reasons 3 or 4 is identified with the
aid of the Sense Interrupt command. This type of interrupt is
cleared after the first result byte has been read. Use bits 5,
6, and 7 of ST0 to identify the cause of the interrupt as
shown in Table 4-14.
Issuing a Sense Interrupt command without an interrupt
pending is treated as an Invalid command. If the extended
track range mode is enabled, a third byte should be read in
the Result Phase, which will indicate the four most significant bits of the present track number. Otherwise, only two
result bytes should be read.
Command Phase:
0
0
0
X
X
X
0
1
1
1
1
X
X
HD
DR1
DR0
0
0
0
New Track Number
MSN of Track Number
0
Note: The last Command Phase byte is required only if ETR is set in Mode
Command.
Execution Phase: Disk drive head is stepped in or out to a
programmed track.
Result Phase: None.
4.1.17 Sense Drive Status Command
The Sense Drive Status command returns the status of the
selected disk drive in ST3. This command does not generate an interrupt.
Command Phase:
0
0
0
0
0
1
0
0
X
X
X
X
X
HD
DR1
DR0
Execution Phase: Disk drive status information is detected
and reported.
TABLE 4-14. Status Register 0 Termination Codes
Status Register 0
Result Phase:
Interrupt
Code
Status Register 3
4.1.18 Sense Interrupt Command
The Sense Interrupt command is used to determine the
cause of an interrupt when the interrupt is a result of the
change in status of any disk drive.
Command Phase:
0
0
0
0
1
0
0
Status Register 0
Present Track Number (PTR)
0
0
D7
D6
D5
1
1
0
Internal Ready Went True
0
0
1
Normal Seek Termination
0
1
1
Abnormal Seek Termination
4.1.19 Set Track Command
This command is used to inspect or change the value of the
internal Present Track Register. This can be useful for recovery from disk mistracking errors, where the real current
track can be read through the Read ID command, and then
the Set Track command can be used to set the internal
Present Track Register to the correct value.
If the WNR bit is a 0, a track register is to be read. In this
case, the Result Phase byte contains the value in the internal register specified, and the third byte in the Command
Phase is a dummy byte.
If the WNR bit is a 1, data is written to a track register. In this
case the third byte of the Command Phase is written to the
specified internal track register, and the Result Phase byte
contains this new value.
The DS1 and DS0 bits select the Present Track Register for
the particular drive. The internal register address depends
on MSB, DS1, and DS0 as shown in Table 4-15. This command does not generate an interrupt.
Result Phase:
0
Cause
0
Execution Phase: Status of interrupt is reported.
MSN of PTR
Seek
End
0
Note: The third Result Phase byte can only be read if ETR is set in the Mode
Command.
Four possible causes for the interrupt are:
1. Entry into the Result Phase of any of the following commands:
a. Read Data
b. Read Deleted Data
c. Read a Track
d. Read ID
e. Write Data
f. Write Deleted Data
g. Format
h. Scan
i. Verify
2. Occurrence of a data transfer in the Execution Phase
while in the Non-DMA mode.
46
4.0 FDC Command Set Description (Continued)
Command Phase:
TABLE 4-15. Set Track Register Address
DS1
DS0
0
0
0
0
1
1
1
1
MSB
0
0
1
1
0
0
1
1
0
Register Addressed
0
1
0
1
0
1
0
1
0
0
0
0
Step Rate Time
PTR0 (LSB)
PTR0 (MSB)
PTR1 (LSB)
PTR1 (MSB)
PTR2 (LSB)
PTR2 (MSB)
PTR3 (LSB)
PTR3 (MSB)
0
1
1
Motor Off Time
Motor On Time
DMA
Execution Phase: Internal registers are written.
Result Phase: None.
Step Rate Time: These four bits define the time interval
between successive step pulses during a seek, implied
seek, recalibrate, or relative seek. The programming of this
step rate is shown in Table 4-16.
Command Phase:
TABLE 4-16. Step Rate Time (SRT) Values
0
WNR
1
0
0
0
0
1
0
0
1
1
0
MSB
DS1
DS0
Present Track Number (PTR)
Execution Phase: Internal register selected by MSB of DS1
or DS0 is read or written.
Result Phase:
Data Rate
Value
Range
Units
1 Mbps
500 kbps
300 kbps
250 kbps
(16 b SRT)/2
(16 b SRT)
(16 b SRT) c 1.67
(16 b SRT) c 2
0.5 – 8
1 – 16
1.67 – 26.7
2 –32
ms
ms
ms
ms
Motor Off Time: These four bits determine the simulated
Motor Off time as shown in Table 4-17.
Motor On Time: These seven bits determine the simulated
Motor On time as shown in Table 4-18.
DMA: This bit selects the data transfer mode in the Execution Phase of a read, write, or scan operation.
0 e DMA mode is selected
Value
4.1.20 Specify Command
The Specify command sets the initial values for three internal timers. The parameters of this command are undefined
after power-up, and are unaffected by any reset. Thus, software should always issue a Specify command as part of an
initialization routine. This command does not generate an
interrupt.
1 e Non-DMA mode is selected
TABLE 4-17. Motor Off Time (MFT) Values
Data Rate
Mode 1 (TMR e 0)
Value
Mode 2 (TMR e 1)
Range
Units
Value
Range
1 Mbps
MFT c 8
8 – 128
MFT c 512
512 – 8192
ms
500 kbps
MFT c 16
16 – 256
MFT c 512
512 – 8192
ms
300 kbps
MFT c 80/3
26.7 – 427
MFT c 2560/3
853 – 13653
ms
250 kbps
MFT c 32
32 – 512
MFT c 1024
1024 – 16384
ms
Note: Motor Off Time e 0 is treated as MFT e 16.
TABLE 4-18. Motor On Time (MNT) Values
Data Rate
1 Mbps
Mode 1 (TMR e 0)
Mode 2 (TMR e 1)
Units
Value
Range
Value
Range
MNT
1 – 128
MNT c 32
32 – 4096
ms
500 kbps
MNT
1 – 128
MNT c 32
32 – 4096
ms
300 kbps
MNT c 10/3
3.3 – 427
MNT c 160/3
53 – 6827
ms
250 kbps
MNT c 4
4 – 512
MNT c 64
64 – 8192
ms
Note: Motor On Time e 0 is treated as MNT e 128.
47
4.0 FDC Command Set Description (Continued)
EOT is equal to the last sector to be checked. In this case,
the Data Length parameter should be set to FFh. Refer to
Table 4-10 for the Result Phase values for a successful
completion of the command. Also see Table 4-19 for further
explanation of the result bytes with respect to the MT and
EC bits.
The Motor Off and Motor On timers are artifacts of the NEC
mPD765. These timers determine both the delay from selecting a drive motor until a read or write operation is started, and the delay of deselecting the drive motor after the
command is completed. Since the FDC enables the drive
and motor select line directly through the DOR, these timers
only provide some delay from the initiation of a command
until it is actually started.
Command Phase:
4.1.21 Verify Command
The Verify command reads logical sectors containing a Normal Data AM from the selected drive without transferring
the data to the host. This command is identical to the Read
Data command, except that no data is transferred during
the Execution Phase.
The Verify command is designed for post-format or postwrite verification. Data is read from the disk, as the controller checks for valid Address Marks in the Address and Data
Fields. The CRC is computed and checked against the previously stored value on the disk. The EOT value should be
set to the final sector to be checked on each side. If EOT is
greater than the number of sectors per side, the command
will terminate with an error and no useful Address Mark or
CRC data will be given.
The TC pin cannot be used to terminate this command
since no data is transferred. The verify command can simulate a TC by setting the EC bit to a 1. In this case, the
command will terminate when SC (Sector Count) sectors
have been read. (If SC e 0 then 256 sectors will be verified.) If EC e 0, then the command will terminate when
MT
MFM
SK
1
0
1
1
0
EC
X
X
X
X
HD
DR1
DR0
Track Number
Drive Head Number
Sector Number
Bytes per Sector
End of Track Sector Number
Intersector Gap Length
Data Length/Sector Count
Execution Phase: Data is read from disk but not transferred
to the system.
Result Phase:
Status Register 0
Status Register 1
Status Register 2
Track Number
Head Number
Sector Number
Bytes per Sector
TABLE 4-19. Verify Command Result Phase
MT
EC
SC/EOT Value (Notes 1, 2)
Termination Result
0
0
DTL used (should be FFh)
EOT s Ý Sectors per Side
No Errors
0
0
DTL used (should be FFh)
EOT l Ý Sectors per Side
Abnormal Termination
0
1
SC s Ý Sectors per Side
AND
SC s EOT
No Errors
0
1
SC l Ý Sectors Remaining
OR
SC l EOT
Abnormal Termination
1
0
DTL used (should be FFh)
EOT s Ý Sectors per Side
No Errors
1
0
DTL used (should be FFh)
EOT l Ý Sectors per Side
Abnormal Termination
1
1
SC s Ý Sectors per Side
AND
SC s EOT
No Errors
1
1
SC s (EOT c 2)
AND
EOT s Ý Sectors per Side
No Errors
1
1
SC l (EOT c 2)
Abnormal Termination
Note 1: Ý Sectors per Side e number of formatted sectors per each side of the disk.
Note 2: Ý Sectors Remaining e number of formatted sectors remaining which can be read, which includes side 1 of the disk if the MT bit is set to 1.
Note 3: If MT e 1 and the SC value is greater than the number of remaining formatted sectors on side 0, verifying will continue on side 1 of the disk.
48
4.0 FDC Command Set Description (Continued)
ST0 are set to Abnormal Termination. This is the expected condition during Non-DMA transfers.
4.1.22 Version Command
The Version command can be used to determine the floppy
controller being used. The Result Phase uniquely identifies
the floppy controller version. The FDC returns a value of
90h in order to be compatible with the 82077. The DP8473
and other NEC765 compatible controllers will return a value
of 80h (invalid command).
3. Underrun error. The OR bit in ST1 is set. The IC bits in
ST0 are set to Abnormal Termination. If the mP cannot
service a transfer request in time, the last correctly written byte will be written to the disk.
If MT was set in the Opcode command byte, and the last
sector of side 0 has been transferred, the controller will then
continue with side 1.
Command Phase:
0
0
0
1
0
0
0
0
Command Phase:
Execution Phase: None.
MT
MFM
0
0
0
1
0
1
Result Phase:
IPS
X
X
X
X
HD
DR1
DR0
1
0
0
1
0
0
0
Track Number
0
Drive Head Number
4.1.23 Write Data Command
The Write Data command receives data from the host and
writes logical sectors containing a Normal Data AM to the
selected drive. The operation of this command is similar to
the Read Data command except that the data is transferred
from the mP to the controller instead of the other way
around.
The controller will simulate the Motor On time before starting the operation. If implied seeks are enabled, the seek and
sense interrupt functions are then performed. The controller
then starts the Data Separator and waits for the Data Separator to find the next sector Address Field. The controller
compares the Address ID (track, head, sector, bytes per
sector) with the desired ID specified in the Command
Phase. If there is no match, the controller waits to find the
next sector Address Field. This process continues until the
desired sector is found. If an error condition occurs, the IC
bits in ST0 are set to Abnormal Termination, and the controller enters the Result Phase. Possible errors are:
1. The mP aborted the command by writing to the FIFO. If
there is no disk in the drive, the controller will hang up.
The mP must then take the controller out of this hung
state by writing a byte to the FIFO. This will put the controller into the Result Phase.
2. Two index pulses were detected since the search began,
and no valid ID has been found. If the track address ID
differs, the WT bit or BT bit (if the track address is FFh)
will be set in ST2. If the head, sector, or bytes per sector
code did not match, the ND bit is set in ST1. If the Address Field AM was never found, the MA bit is set in ST1.
3. The Address Field was found with a CRC error. The CE
bit is set in ST1.
4. If the controller detects the Write Protect disk interface
input is Asserted. Bit 1 of ST1 is set.
If the correct Address Field is found, the controller waits for
all (conventional mode) or part (perpendicular mode) of
GAP2 to pass. The controller will then write the preamble
field, address marks, and data bytes to the Data Field. The
data bytes are transferred to the controller by the mP.
Having finished writing the sector, the controller will continue reading the next logical sector unless one or more of the
following termination conditions has occurred:
1. The DMA controller asserted TC. The IC bits in ST0 are
set to Normal Termination.
2. The last sector address (of side 1 if MT was set) was
equal to EOT. The EOT bit in ST1 is set. The IC bits in
Sector Number
Bytes per Sector
End of Track Sector Number
Intersector Gap Length
Data Length
Execution Phase: Data is transferred from the system to
the controller via DMA or Non-DMA modes and written to
the disk.
Result Phase:
Status Register 0
Status Register 1
Status Register 2
Track Number
Head Number
Sector Number
Bytes per Sector
4.1.24 Write Deleted Data
The Write Deleted Data command receives data from the
host and writes logical sectors containing a Deleted Data
AM to the selected drive. This command is identical to the
Write Data command except that a Deleted Data AM is written to the Data Field instead of a Normal Data AM.
Command Phase:
MT
MFM
0
0
1
0
0
1
IPS
X
X
X
X
HD
DR1
DR0
Track Number
Drive Head Number
Sector Number
Bytes per Sector
End of Track Sector Number
Intersector Gap Length
Data Length
Execution Phase: Data is transferred from the system to
the controller via DMA or Non-DMA modes and written to
the disk.
49
4.0 FDC Command Set Description (Continued)
Result Phase:
Result Phase:
Status Register 0
Status Register 0
Status Register 1
Status Register 1
Status Register 2
Status Register 2
Track Number
Undefined
Head Number
Undefined
Sector Number
Undefined
Bytes per Sector
Undefined
4.2 COMMAND SET SUMMARY
INVALID
CONFIGURE
Command Phase:
Invalid Op Codes
Command Phase:
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
EIS
FIFO
POLL
Execution Phase: None.
Result Phase:
THRESH
Status Register 0 (80h)
PRETRK
Execution Phase: Internal registers written.
LOCK
Result Phase: None.
Command Phase:
LOCK
DUMPREG
Command Phase:
0
0
0
0
1
0
1
0
0
Execution Phase: Internal Lock register is written.
0
0
1
1
1
0
Result Phase:
0
Execution Phase: Internal registers read.
Result Phase:
0
0
LOCK
0
0
0
0
MODE
PTR Drive 0
Command Phase:
PTR Drive 1
PTR Drive 2
PTR Drive 3
Step Rate Time
Motor Off Time
Motor On Time
0
0
0
0
0
0
0
1
TMR
IAF
IPS
0
LOW PWR
1
ETR
FWR
FRD
0
0
0
DENSEL
DMA
0
BST
R255
BFR
WLD
0
0
0
0
Head Settle
0
RG
0
PU
Sector per Track/End of Track (Note)
LOCK
0
DC3
DC2
0
EIS
FIFO
POLL
DC1
DC0
GAP
Execution Phase: Internal registers are written.
WG
THRESH
Result Phase: None.
PRETRK
NSC
Note: Sectors per Track parameter returned if last command issued was
Format. End of Track parameter returned if last command issued was
Read or Write.
Command Phase:
0
0
0
1
1
0
0
0
1
0
0
1
1
FORMAT TRACK
Execution Phase: None.
Command Phase:
0
MFM
0
0
1
1
0
1
X
X
X
X
X
HD
DR1
DR0
Result Phase:
0
Bytes per Sector
1
1
PERPENDICULAR MODE
Sectors per Track
Command Phase:
Format Gap
Data Pattern
Execution Phase: System transfers four ID bytes (track,
head, sector, bytes/sector) per sector to the floppy controller via DMA or Non-DMA modes. The entire track is formatted. The data block in the Data Field of each sector is filled
with the data pattern byte.
0
0
0
1
0
0
1
0
OW
0
DC3
DC2
DC1
DC0
GAP
WG
Execution Phase: Internal registers are written.
Result Phase: None.
50
4.0 FDC Command Set Description (Continued)
Execution Phase: Controller reads first ID Field header
bytes it can find and reports these bytes to the system in the
result bytes.
READ DATA
Command Phase:
MT
MFM
SK
0
0
1
1
0
IPS
X
X
X
X
HD
DR1
DR0
Result Phase:
Status Register 0
Track Number
Status Register 1
Drive Head Number
Status Register 2
Sector Number
Track Number
Bytes per Sector
Head Number
End of Track Sector Number
Sector Number
Intersector Gap Length
Bytes per Sector
Data Length
READ A TRACK
Execution Phase: Data read from disk drive is transferred
to system via DMA or Non-DMA modes.
Command Phase:
Result Phase:
Status Register 0
0
MFM
0
0
0
0
1
0
IPS
X
X
X
X
HD
DR1
DR0
Status Register 1
Track Number
Status Register 2
Drive Head Number
Track Number
Sector Number
Head Number
Bytes per Sector
Sector Number
End of Track Sector Number
Bytes per Sector
Intersector Gap Length
Data Length
READ DELETED DATA
Execution Phase: Data read from disk drive is transferred
to system via DMA or non-DMA modes.
Command Phase:
MT
MFM
SK
0
1
1
0
0
IPS
X
X
X
X
HD
DR1
DR0
Result Phase:
Status Register 0
Track Number
Drive Head Number
Status Register 1
Sector Number
Status Register 2
Bytes per Sector
Track Number
Head Number
End of Track Sector Number
Sector Number
Intersector Gap Length
Bytes per Sector
Data Length
RECALIBRATE
Execution Phase: Data read from disk drive is transferred
to system via DMA or Non-DMA modes.
Command Phase:
Result Phase:
Status Register 0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
DR1
DR0
Status Register 1
Track Number
Execution Phase: Disk drive head is stepped out to Track 0.
Result Phase: None.
Head Number
RELATIVE SEEK
Sector Number
Command Phase:
Status Register 2
Bytes per Sector
READ ID
1
DIR
0
0
1
1
1
1
X
X
X
X
X
HD
DR1
DR0
RELATIVE TRACK NUMBER
Command Phase:
0
MFM
0
0
1
0
1
0
X
X
X
X
X
HD
DR1
DR0
51
4.0 FDC Command Set Description (Continued)
Execution Phase: Disk drive head stepped in or out a programmable number of tracks.
Result Phase:
Status Register 0
Result Phase: None.
Status Register 1
SCAN EQUAL
Status Register 2
Track Number
Command Phase:
Head Number
MT
MFM
SK
IPS
X
X
1
0
0
0
1
X
X
HD
DR1
DR0
Sector Number
Bytes per Sector
Track Number
SCAN LOW OR EQUAL
Drive Head Number
Sector Number
Command Phase:
Bytes per Sector
End of Track Sector Number
MT
MFM
SK
1
1
0
0
1
IPS
X
X
X
X
HD
DR1
DR0
Intersector Gap Length
Track Number
Sector Step Size
Drive Head Number
Execution Phase: Data transferred from system to controller is compared to data read from disk.
Sector Number
Bytes per Sector
Result Phase:
End of Track Sector Number
MT
MFM
SK
1
1
1
0
1
Intersector Gap Length
IPS
X
X
X
X
HD
DR1
DR0
Sector Step Size
Status Register 0
Execution Phase: Data transferred from system to controller is compared to data read from disk.
Status Register 1
Status Register 2
Result Phase:
Track Number
Status Register 0
Head Number
Status Register 1
Sector Number
Status Register 2
Bytes per Sector
Track Number
SCAN HIGH OR EQUAL
Head Number
Command Phase:
Sector Number
MT
MFM
SK
IPS
X
X
1
1
1
0
1
X
X
HD
DR1
DR0
Bytes per Sector
SEEK
Track Number
Command Phase:
Drive Head Number
Sector Number
Bytes per Sector
0
0
0
0
1
1
1
1
X
X
X
X
X
HD
DR1
DR0
0
0
0
New Track Number
End of Track Sector Number
MSN of Track Number
0
Intersector Gap Length
Note: The last Command Phase byte is required only if ETR is set in Mode
Command.
Sector Step Size
Execution Phase: Data transferred from system to controller is compared to data read from disk.
Execution Phase: Disk drive head is stepped in or out to a
programmed track.
Result Phase: None.
52
4.0 FDC Command Set Description (Continued)
VERIFY
SENSE DRIVE STATUS
Command Phase:
Command Phase:
0
0
0
0
0
1
0
0
MT
MFM
SK
1
0
1
1
0
X
X
X
X
X
HD
DR1
DR0
EC
X
X
X
X
HD
DR1
DR0
Track Number
Execution Phase: Disk drive status information is detected
and reported.
Drive Head Number
Sector Number
Result Phase:
Bytes per Sector
Status Register 3
End of Track Sector Number
Intersector Gap Length
SENSE INTERRUPT
Data Length/Sector Count
Command Phase:
0
0
0
0
1
0
0
Execution Phase: Data is read from disk but not transferred
to the system.
0
Execution Phase: Status of interrupt is reported.
Result Phase:
Result Phase:
Status Register 0
Status Register 0
Status Register 1
Present Track Number (PTR)
MSN of PTR
0
Status Register 2
0
0
0
Track Number
Head Number
Note: The third Result Phase byte can only be read if ETR is set in the
Mode Command.
Sector Number
SET TRACK
Bytes per Sector
Command Phase:
VERSION
0
WNR
1
0
0
0
0
1
0
0
1
1
0
MSB
DS1
DS0
Command Phase:
0
Present Track Number (PTR)
0
0
1
0
0
0
0
1
0
0
0
0
Execution Phase: None.
Execution Phase: Internal register selected by MSB of DS1
or DS0 is read or written.
Result Phase:
Result Phase:
1
0
0
Value
WRITE DATA
Command Phase:
SPECIFY
Command Phase:
0
0
0
0
Step Rate Time
0
0
1
1
MFM
0
0
0
1
0
1
X
X
X
X
HD
DR1
DR0
Track Number
Motor Off Time
Motor On Time
MT
IPS
Drive Head Number
DMA
Sector Number
Execution Phase: Internal registers are written.
Bytes per Sector
Result Phase: None.
End of Track Sector Number
Intersector Gap Length
Data Length
53
4.0 FDC Command Set Description (Continued)
Execution Phase: Data is transferred from the system to
the controller via DMA or Non-DMA modes and written to
the disk.
Execution Phase: Data is transferred from the system to
the controller via DMA or Non-DMA modes and written to
the disk.
Result Phase:
Result Phase:
Status Register 0
Status Register 0
Status Register 1
Status Register 1
Status Register 2
Status Register 2
Track Number
Track Number
Head Number
Head Number
Sector Number
Sector Number
Bytes per Sector
Bytes per Sector
WRITE DELETED DATA
Command Phase:
MT
MFM
0
0
1
0
0
1
IPS
X
X
X
X
HD
DR1
DR0
Track Number
Drive Head Number
Sector Number
Bytes per Sector
End of Track Sector Number
Intersector Gap Length
Data Length
54
4.0 FDC Command Set Description (Continued)
MFM
4.3 MNEMONIC DEFINITIONS FOR FDC COMMANDS
Symbol
Description
BFR
Buffer enable bit used in the Mode command.
Enabled open-collector output buffers.
Burst Mode disable control bit used in Mode
command. Selects the Non-Burst FIFO mode if
the FIFO is enabled.
Drive Configuration 0–3. Used to set DC1a
drive to conventional or perpendicular DC2
mode. Used in Perpendicular Mode DC3 command.
Density Select control bits used in the Mode
command.
Direction control bit used in Relative Seek
command to indicate step in or out.
DMA mode enable bit used in the Specify command.
Drive Select 0–1 bits used in most commands.
Selects the logical drive.
Data Length parameter used in the Read,
Write, Scan and Verify commands.
Enable Count control bit used in the Verify
command. When this bit is 1, the DTL parameter becomes SC (Sector Count).
Enable Implied Seeks. Used in the Configure
command.
End of Track parameter set in the Read, Write,
Scan, and Verify commands.
Extended Track Range used with the Seek
command.
First-In First-Out buffer. Also a control bit used
in the Configure command to enable or disable
the FIFO.
FIFO Read disable control bit used in the
Mode command.
FIFO Write disable control bit used in the
Mode command.
GAP2 control bit used in the Perpendicular
Mode command.
Head Select control bit used in most commands. Selects Head 0 or 1 of the disk.
Index Address Field control bit used in the
Mode command. Enables the ISO Format during the Format command.
Implied Seek enable bit used in the Mode,
Read, Write, and Scan commands.
Lock enable bit in the Lock command. Used to
make certain parameters be unaffected by a
software reset.
Low Power control bits used in the Mode command.
BST
DC0 – 3
DENSEL
DIR
DMA
DR0 – 1
DTL
EC
EIS
EOT
ETR
FIFO
FRD
FWR
GAP
HD
IAF
IPS
LOCK
LOW PWR
MFT
MNT
MT
OW
POLL
PRETRK
PTR
PU
R255
RG
RTN
SC
SK
SRT
ST0 – 3
THRESH
TMR
WG
WLD
55
Modified Frequency Modulation control bit
used in the Read, Write, Format, Scan and
Verify commands. Selects MFM or FM data
encoding.
Motor Off Time programmed in the Specify
command.
Motor On Time programmed in the Specify
command.
Multi-Track enable bit used in the Read, Write,
Scan and Verify commands.
Overwrite control bit used in the Perpendicular
Mode command.
Enable Drive Polling bit used in the Configure
command.
Precompensation Track Number used in the
Configure command.
Present Track Register. Contains the internal
track number for one of the four logical disk
drives.
Pump diagnostic enable bit used in the Mode
command.
Recalibrate control bit used in Mode command. Sets maximum recalibrate step pulses
to 255.
Read Gate diagnostic enable bit used in the
Mode command.
Relative Track Number used in the Relative
Seek command.
Sector Count control bit used in the Verify
command.
Skip control bit used in read and scan operations.
Step Rate Time programmed in the Specify
command. Determines the time between step
pulses for seek and recalibrates.
Status Register 0 – 3. Contains status ST1 information about the execution of an ST2 command. Read in the Result Phase of some ST3
commands.
FIFO threshold parameter used in the Configure command.
Timer control bit used in the Mode command.
Affects the timers set in the Specify command.
Write Gate control bit used in the Perpendicular Mode command.
Wildcard bit in the Mode command used to enable or disable the wildcard byte (FF) during
Scan commands.
5.0 FDC Functional Description
microprocessor. In addition, when no command is in progress, the controller is in the Idle Phase or Drive Polling
Phase.
The PC87306 is software compatible with the DP8473 and
82077 floppy disk controllers. Upon a power on reset, the
16-byte FIFO will be disabled. Also, the disk interface outputs will be configured as active push-pull outputs, which
are compatible with both CMOS inputs and open-collector
resistor terminated disk drive inputs. The FIFO can be enabled with the Configure command. The FIFO can be very
useful at the higher data rates, with systems that have a
large amount of DMA bus latency, or with multi-tasking systems such as the EISA or MicroChannel bus structures.
The FDC will support all the DP8473 Mode command features as well as some additional features. Additional features include control over the enabling of the FIFO for reads
and writes, a Non-Burst mode for the FIFO, a bit that will
configure the disk interface outputs as open-drain outputs,
and programmability of the DENSEL output.
5.3.1 Command Phase
During the Command Phase, the mP writes a series of bytes
to the Data Register. The first command byte contains the
opcode for the command, and the controller knows how
many more bytes to expect based on this opcode byte. The
remaining command bytes contain the particular parameters
required for the command. The number of command bytes
varies for each particular command. All the command bytes
must be written in the order specified in the Command Description Table. The Execution Phase starts immediately after the last byte in the Command Phase is written. Prior to
performing the Command Phase, the Digital Output Register
should be set and the data rate should be set with the Data
Rate Select Register or Configuration Control Register.
The Main Status Register controls the flow of command
bytes, and must be polled by the software before writing
each Command Phase byte to the Data Register. Prior to
writing a command byte, the RQM bit (D7) must be set and
the DIO bit (D6) must be cleared in the MSR. After the first
command byte is written to the Data Register, the CMD
PROG bit (D4) is also set and remains set until the last
Result Phase byte is read. If there is no Result Phase, the
CMD PROG bit will be cleared after the last command byte
is written.
A new command may be initiated after reading all the result
bytes from the previous command. If the next command
requires selecting a different drive or changing the data rate,
the DOR and DSR or CCR should be updated. If the command is the last command, the software should deselect the
drive.
5.1 MICROPROCESSOR INTERFACE
The FDC interface to the microprocessor consists of the
A9 – A3, AEN, RD, and WR lines, which access the chip for
reads and writes; the data lines D7–0; the address lines
A2 – 0, which select the appropriate register (see Table 3-1);
the IRQ6 signal, and the DMA interface signals DRQ,
DACK, and TC. It is through this microprocessor interface
that the floppy controller receives commands, transfers
data, and returns status information.
5.2 MODES OF OPERATION
The FDC has two modes of operation: PC-AT mode and
PS/2 mode, which are determined by the state of bits 7 and
6 of the ASC register. See Section 3.0 Register Description
for more details on the register set used for each mode of
operation.
PC-AT ModeÐBits 7, 6 of ASC register are 11 (default):
The PC-AT register set is enabled. The DMA enable bit in
the Digital Output Register becomes valid (IRQ6 and DRQ
can be TRI-STATE). TC and DENSEL become active high
signals (defaults to a 5.25× floppy drive).
PS/2 ModeÐBits 7, 6 of ASC register are 01: This mode
supports the PS/2 Models 50/60/80 configuration and register set. The DMA enable bit in the Digital Output Register
becomes a don’t care (IRQ6 and DRQ signals are always
valid). TC and DENSEL become active low signals (default
to 3.5× floppy drive).
Note: As a general rule, the operation of the controller core is independent
of how the mP updates the DOR, DSR, and CCR. The software must
ensure that the manipulation of these registers is coordinated with
the controller operation.
5.3.2 Execution Phase
During the Execution Phase, the disk controller performs
the desired command. Commands that involve data transfers, (e.g., read, write, or format operation) require the mP to
write or read data to or from the Data Register at this time.
Some commands such as a Seek or Recalibrate control the
read/write head movement on the disk drive during the Execution Phase via the disk interface signals. Execution of other commands does not involve any action by the mP or disk
drive, and consists of an internal operation by the controller.
If there is data to be transferred between the mP and the
controller during the Execution, there are three methods
that can be used, DMA mode, interrupt transfer mode, and
5.3 CONTROLLER PHASES
The FDC has three separate phases of a command, the
Command Phase, the Execution Phase, and the Result
Phase. Each of these controller phases determine how data
is transferred between the floppy controller and the host
56
5.0 FDC Functional Description (Continued)
For both the Burst and Non-Burst modes, when the last byte
in the FIFO has been read, DRQ goes inactive. DRQ is then
reasserted when the FIFO trigger condition is satisfied. After
the last byte of a sector has been read from the disk, DRQ
is again generated even if the FIFO has not yet reached its
threshold trigger condition. This guarantees that all the current sector bytes are read from the FIFO before the next
sector byte transfer begins.
software polling mode. The last two modes are called the
Non-DMA modes. The DMA mode is used if the system has
a DMA controller. This allows the mP to do other tasks while
the data transfer takes place during the Execution Phase. If
the Non-DMA mode is used, an interrupt is issued for each
byte transferred during the Execution Phase. Also, instead
of using the interrupt during Non-DMA mode, the Main
Status Register can be polled by software to indicate when
a byte transfer is required. All of these data transfer modes
work with the FIFO enabled or disabled.
Write Data Transfers
Whenever the number of bytes in the FIFO is less than or
equal to THRESH, a DRQ is generated. This is the trigger
condition for the FIFO write data transfers from the mP to
the floppy controller.
Burst Mode. DRQ remains active until enough bytes have
been written to the controller to completely fill the FIFO.
Non-Burst Mode. DRQ is deasserted after each write
transfer. If the FIFO is not full, DRQ is reasserted after a 350
ns delay. This deassertion of DRQ allows other higher priority DMA transfers to take place between floppy transfers.
The FIFO has a byte counter which monitors the number of
bytes being transferred to the FIFO during write operations
for both Burst and Non-Burst modes. When the last byte of
a sector is transferred to the FIFO, DRQ is deasserted even
if the FIFO has not been completely filled. Thus, the FIFO is
cleared after each sector is written. Only after the floppy
controller has determined that another sector is to be written is DRQ asserted again. Also, since DRQ is deasserted
immediately after the last byte of a sector is written to the
FIFO, the system does not need to tolerate any DRQ deassertion delay and is free to do other work.
5.3.2.1 DMA ModeÐFIFO Disabled
The DMA mode is selected by writing a 0 to the DMA bit in
the Specify command and by setting the DMA enabled bit
(D3) in the DOR. With the FIFO disabled, a DMA request
(DRQ) is generated in the Execution Phase when each byte
is ready to be transferred. The DMA controller should respond to the DRQ with a DMA acknowledge (DACK) and a
read or write strobe. The DRQ is cleared by the leading
edge of the active low DACK input signal. After the last byte
is transferred, an interrupt is generated, indicating the beginning of the Result Phase. During DMA operations the chip
select input (CS) must be held high. The DACK signal acts
as the chip select for the FIFO in this case, and the state of
the address lines A2–A0 is a don’t care. The Terminal
Count (TC) signal can be asserted by the DMA controller to
terminate the data transfer at any time. Due to internal gating, TC is only recognized when DACK is low.
PC-AT Mode. When in the PC-AT interface mode with the
FIFO disabled, the controller is in single byte transfer mode.
That is, the system has one byte time to service a DMA
request (DRQ) from the controller. DRQ will be deasserted
between each byte.
PS/2 Mode. When in the PS/2 mode, DMA transfers with
the FIFO disabled are performed differently. Instead of a
single byte transfer mode, the FIFO is actually enabled with
THRESH e 0Fh. Thus, DRQ is asserted when one byte has
entered the FIFO during reads, and when one byte can be
written to the FIFO during writes. DRQ is deasserted by the
leading edge of the DACK input, and is reasserted when
DACK goes inactive high. This operation is very similar to
Burst mode transfer with the FIFO enabled except that DRQ
is deasserted between each byte.
Read and Write Data Transfers
The DACK input signal from the DMA controller may be held
active during an entire burst or it may be strobed for each
byte transferred during a read or write operation. When in
the Burst mode, the floppy controller deasserts DRQ as
soon as it recognizes that the last byte of a burst was transferred. If DACK is strobed for each byte, the leading edge of
this strobe is used to deassert DRQ. If DACK is strobed, RD
or WR are not required. This is the case during the ReadVerify mode of the DMA controller. If DACK is held active
during the entire burst, the trailing edge of the RD or WR
strobe is used to deassert DRQ. DRQ is deasserted within
50 ns of the leading edge of DACK, RD, or WR. This quick
response should prevent the DMA controller from transferring extra bytes in most applications.
5.3.2.2 DMA ModeÐFIFO Enabled
Read Data Transfers
Whenever the number of bytes in the FIFO is greater than
or equal to (16 b THRESH), a DRQ is generated. This is the
trigger condition for the FIFO read data transfers from the
floppy controller to the mP.
Burst Mode. DRQ remains active until enough bytes have
been read from the controller to empty the FIFO.
Non-Burst Mode. DRQ is deasserted after each read transfer. If the FIFO is not completely empty, DRQ is reasserted
after a 350 ns delay. This allows other higher priority DMA
transfers to take place between floppy transfers. In addition,
this mode allows the controller to work correctly in systems
where the DMA controller is put into a read verify mode,
where only DACK signals are sent to the FDC, with no RD
pulses. This read verify mode of the DMA controller is used
in some PC software. The FIFO Non-Burst mode allows the
DACK input from the DMA controller to be strobed, which
correctly clocks data from the FIFO.
Overrun Errors
An overrun or underrun error terminates the execution of
the command if the system does not transfer data within the
allotted data transfer time (see Section 3.7), which puts the
controller into the Result Phase. During a read overrun, the
mP is required to read the remaining bytes of the sector
before the controller asserts IRQ6, signifying the end of execution. During a write operation, an underrun error terminates the Execution Phase after the controller has written
the remaining bytes of the sector with the last correctly written byte to the FIFO and generated the CRC bytes. Whether
there is an error or not, an interrupt is generated at the end
of the Execution Phase, and is cleared by reading the first
Result Phase byte.
57
5.0 FDC Functional Description (Continued)
DACK asserted alone without a RD or WR strobe is also
counted as a transfer. If RD or WR are not being strobed for
each byte, DACK must be strobed for each byte so that the
floppy controller can count the number of bytes correctly. A
new command, the Verify command, has been added to
allow easier verification of data written to the disk without
the need of actually transferring the data on the data bus.
5.3.2.3 Interrupt ModeÐFIFO Disabled
If the Interrupt (Non-DMA) mode is selected, IRQ6 is asserted instead of DRQ when each byte is ready to be transferred. The Main Status Register should be read to verify
that the interrupt is for a data transfer. The RQM and NON
DMA bits (D7 and D5) in the MSR are set. The interrupt is
cleared when the byte is transferred to or from the Data
Register. CS and RD or CS and WR must be used to transfer the data in or out of the Data Register (A2–A0 must be
valid). CS asserted by itself is not significant. CS must be
asserted with RD or WR for a read or write transfer to be
recognized.
The mP should transfer the byte within the data transfer
service time (see Section 3.7). If the byte is not transferred
within the time allotted, an Overrun Error will be indicated in
the Result Phase when the command terminates at the end
of the current sector.
An interrupt is also be generated after the last byte is transferred. This indicates the beginning of the Result Phase.
The RQM and DIO bits (D7 and D6) in the MSR is set, and
the non-DMA bit (D5) is cleared. This interrupt is cleared by
reading the first Result Phase byte.
5.3.3 Result Phase
During the Result Phase, the mP reads a series of bytes
from the data register. These bytes indicate the status of the
command. This status may indicate whether the command
executed properly, or contain some control information (see
the Command Description and Status Register Description).
These Result Phase bytes are read in the order specified for
that particular command. Some commands will not have a
result phase. Also, the number of result bytes varies with
each command. All of the result bytes must be read from
the Data Register before the next command can be issued.
Like the Command Phase, the Main Status Register controls the flow of result bytes, and must be polled by the
software before reading each Result Phase byte from the
Data Register. The RQM bit (D7) and DIO bit (D6) must both
be set before each result byte can be read. After the last
result byte is read, the COM PROG bit (D4) in the MSR is
cleared, and the controller is ready for the next command.
5.3.4 Idle Phase
After a hardware or software reset, or after the chip has
recovered from the power-down mode, the controller enters
the Idle Phase. Also, when there are no commands in progress the controller is in the Idle Phase. The controller waits
for a command byte to be written to the Data Register. The
RQM bit is set and the DIO bit cleared in the MSR. After
receiving the first command (opcode) byte, the controller
enters the Command Phase. When the command is completed the controller again enters the Idle Phase. The Data
Separator remains synchronized to the reference frequency
while the controller is idle. While in the Idle Phase, the controller will periodically enters the Drive Polling Phase (see
Section 5.3.5).
5.3.2.4 Interrupt ModeÐFIFO Enabled
The Interrupt (Non-DMA) mode with the FIFO enabled is
very similar to the Non-DMA mode with the FIFO disabled.
In this case, IRQ6 is asserted instead of DRQ under the
exact same FIFO threshold trigger conditions. The MSR
should be read to verify that the interrupt is for a data transfer. The RQM and NON DMA bits (D7 and D5) in the MSR is
set. CS and RD or CS and WR must be used to transfer the
data in or out of the Data Register (A2–A0 must be valid).
CS asserted by itself is not significant. CS must be asserted
with RD or WR for a read or write transfer to be recognized.
The Burst mode may be used to hold the IRQ6 pin active
during a burst, or the Non-Burst mode may be used to toggle the IRQ6 pin for each byte of a burst. The Main Status
Register is always valid from the mP point of view. For example, during a read command, after the last byte of data
has been read from the disk and placed in the FIFO, the
MSR still indicates that the Execution Phase is active, and
that data needs to be read from the Data Register. Only
after the last byte of data has been read by the mP from the
FIFO does the Result Phase begin.
The same overrun and underrun error procedures from the
DMA mode apply to the Non-DMA mode. Also, whether
there is an error or not, an interrupt is generated at the end
of the Execution Phase, and is cleared by reading the first
Result Phase byte.
5.3.5 Drive Polling Phase
The National FDC supports the polling mode of the old generation 8-inch drives as a means of monitoring any change
in status for each disk drive present in the system. This
mode is supported for the sole purpose of providing backward compatibility with software that expects its presence.
While in the Idle Phase the controller enters a Drive Polling
Phase every 1 ms (based on the 500 kbps data rate). While
in the Drive Polling Phase, the controller interrogates the
Ready Changed status for each of the four logical drives.
The internal Ready line for each drive is toggled only after a
hardware or software reset, and an interrupt is generated for
drive 0. At this point, the software must issue four Sense
Interrupt commands to clear the Ready Changed State
status for each drive. This requirement can be eliminated if
drive polling is disabled via the POLL bit in the Configure
command. The Configure command must be issued within
500 ms (worst case ) of the hardware or software reset for
drive polling to be disabled.
Even if drive polling is disabled, drive stepping and delayed
power-down occurs in the Drive Polling Phase. The controller checks the status of each drive and if necessary it issues
a step pulse on the STEP output with the DIR signal at the
appropriate logic level. Also, the controller uses the Drive
Polling Phase to control the Automatic Low Power mode.
When the Motor Off time has expired, the controller waits
512 ms based on the 500 kbps and 1 Mbps data rate before
powering down if this function is enabled via the Mode command.
5.3.2.5 Software Polling
If the Non-DMA mode is selected and interrupts are not
suitable, the mP can poll the MSR during the Execution
Phase to determine when a byte is ready to be transferred.
The RQM bit (D7) in the MSR reflects the state of the IRQ6
signal. Otherwise, the data transfer is similar to the Interrupt
Mode described above. This is true for the FIFO enabled or
disabled.
58
5.0 FDC Functional Description (Continued)
TL/C/12379 – 30
FIGURE 5-1. FDC Data Separator Block Diagram
tomatically switched into the data separator circuit when the
data rate is selected via the Data Rate Select or Configuration Control Register. These filters have been optimized
through lab experimentation, and are designed into the controller to reduce the external component cost associated
with the floppy controller.
The FDC has a dynamic window margin and lock range performance capable of handling a wide range of floppy disk
drives. Also, the data separator works well under a variety of
conditions, including the high motor speed fluctuations of
floppy compatible tape drives.
If a new command is issued when the FDC is in the middle
of a polling routine, the MSR will not indicate a ready status
for the next parameter byte until the poling sequence completes the loop. This can cause a delay between the first
and second bytes of up to 500 ms at 250 kbps.
5.4 DATA SEPARATOR
The internal data separator consists of an analog PLL and
its associated circuitry. The PLL synchronizes the raw data
signal read from the disk drive. The synchronized signal is
used to separate the encoded clock and data pulses. The
data pulses are deserialized into bytes and then sent to the
mP by the controller.
The main PLL consists of five main components, a phase
comparator, a charge pump, a filter, a voltage controlled
oscillator (VCO), and a programmable divider. The phase
comparator detects the difference between the phase of the
divider’s output and the phase of the raw data being read
from the disk. This phase difference is converted to a current by the charge pump, which either charges or discharges one of three filters which is selected based on the data
rate. The resulting voltage on the filter changes the frequency of the VCO and the divider output to reduce the phase
difference between the input data and the divider’s output.
The PLL is ‘‘locked’’ when the frequency of the divider is
exactly the same as the average frequency of the data read
from the disk. A block diagram of the data separator is
shown in Figure 5-1 .
To ensure optimal performance, the data separator incorporates several additional circuits. The quarter period delay
line is used to determine the center of each bit cell, and to
disable the phase comparator when the raw data signal is
missing a clock or data pulse in the MFM or FM pattern. A
secondary PLL is used to automatically calibrate the quarter
period delay line. The secondary PLL also calibrates the
center frequency of the VCO.
To eliminate the logic associated with controlling multiple
data rates, the FDC supports each of the four data rates
(250, 300, 500 kbps, and 1 Mbps) with a separate, optimized
internal filter. The appropriate filter for each data rate is au-
Figure 5-2 shows the floppy disk controller dynamic window
margin performance at the four different data rates. Dynamic window margin is the primary indicator of the quality and
performance level of the data separator. This measurement
indicates how much motor speed variation (MSV) of the
drive spindle motor and bit jitter (or window margin) can be
tolerated by the data separator.
MSV is shown on the x-axis of the dynamic window margin
graph. MSV is translated directly to the actual data rate of
the data as it is read from the disk by the data separator.
That is, a faster than nominal motor will result in a higher
frequency in the actual data rate.
The dynamic window margin performance curves also indicate how much bit jitter (or window margin) can be tolerated
by the data separator. This parameter is shown on the
y-axis of the graphs. Bit jitter is caused by the magnetic
interaction of adjacent data pulses on the disk, which effectively shifts the bits away from their nominal positions in the
middle of the bit window. Window margin is commonly measured as a percentage. This percentage indicates how far a
data bit can be shifted early or late with respect to its nominal bit position, and still be read correctly by the data separator. If the data separator cannot correctly decode a shifted
bit, then the data is misread and a CRC results.
The dynamic window margin performance curves contain
two pieces of information: 1) the maximum range of MSV
(also called ‘‘lock range’’) that the data separator can handle with no read errors, and 2) the maximum percentage of
59
5.0 FDC Functional Description (Continued)
250 kbps
300 kbps
TL/C/12379 – 32
TL/C/12379–31
500 kbps
1 Mbps
TL/C/12379–33
TL/C/12379 – 34
FIGURE 5-2. PC87306 Dynamic Window Margin Performance
(Typical performance at VDD e 5.0V, 25§ C)
An external oscillator circuit must have a duty cycle of at
least 40% – 60% and minimum input levels of 2.4V and
0.4V. The controller should be configured so that the external oscillator clock is input into the X1/OSC pin.
window margin (or bit jitter) that the data separator can handle with no read errors. Thus, the area under the dynamic
window margin curves in Figure 5-2 is the range of MSV and
bit jitter that the FDC can handle with no read errors. The
FDC internal analog data separator has a much better performance than comparable digital data separator designs,
and does not require any external components.
5.6 PERPENDICULAR RECORDING MODE
The FDC is fully compatible with perpendicular recording
mode disk drives at all data rates. These perpendicular
mode drives are also called 4 Mbyte (unformatted) or
2.88 Mbyte (formatted) drives, which refers to their maximum storage capacity. Perpendicular recording will orient
the magnetic flux changes (which represent bits) vertically
on the disk surface, allowing for a higher recording density
than the conventional longitudinal recording methods. With
this increase in recording density comes an increase in the
data rate of up to 1 Mbps, thus doubling the storage capacity. In addition, the perpendicular 2.88M drive is read/write
compatible with 1.44M and 720k diskettes (500 kbps and
250 kbps respectively).
Note: The dynamic window margin curves were generated using a FlexStar
FS-540 Floppy Disk Simulator and a proprietary dynamic window
margin test program written by National Semiconductor.
The controller takes best advantage of the internal analog
data separator by implementing a sophisticated read algorithm. This ID search algorithm, shown in Figure 5-3 , enhances the PLL’s lock characteristics by forcing the PLL to
relock to the crystal reference frequency any time the data
separator attempts to lock to a non-preamble pattern. This
algorithm ensures that the PLL is not thrown way out of lock
by write splices or bad data fields.
5.5 CRYSTAL OSCILLATOR
The FDC is clocked by a single 24 MHz signal.
60
5.0 FDC Functional Description (Continued)
pre-erase head is located at the beginning of the Data Field
preamble. This means that WGATE should be asserted
when the read/write head is at least 38 bytes (at 1 Mbps)
before the preamble. See Table 4-5 for a description of the
WGATE timing for perpendicular drives at the various data
rates.
Because of the 38 byte spacing between the read/write
head and the pre-erase head at 1 Mbps, the GAP2 length of
22 bytes used in the standard IBM disk format is not long
enough. There is a new format standard for 2.88M drives at
1 Mbps called the Perpendicular Format, which increases
the GAP2 length to 41 bytes (see Figure 4-1 ). The Perpendicular Mode command will put the floppy controller into
perpendicular recording mode, which allows it to read and
write perpendicular media. Once this command is invoked,
the read, write and format commands can be executed in
the normal manner. The perpendicular mode of the floppy
controller will work at all data rates, adjusting the format and
write data parameters accordingly. See Section 4.2.6 for
more details.
The 2.88M drive has unique format and write data timing
requirements due to its read/write head and pre-erase head
design (see Figure 5-4 ). Unlike conventional disk drives
which have only a read/write head, the 2.88M drive has
both a pre-erase head and read/write head. With conventional disk drives, the read/write head by itself is able to
rewrite the disk without problems. For 2.88M drives, a preerase head is needed to erase the magnetic flux on the disk
surface before the read/write can write to the disk surface.
The pre-erase head is activated during disk write operations
only, i.e., Format and Write Data commands.
In 2.88M drives, the pre-erase head leads the read/write
head by 200 mm, which translates to 38 bytes at 1 Mbps
(19 bytes at 500 kbps). For both conventional and perpendicular drives, WGATE is asserted with respect to the position of the read/write head. With conventional drives, this
means that WGATE is asserted when the read/write head is
located at the beginning of the Data Field preamble. With the
2.88M drives, since the preamble must be pre-erased before it is rewritten, WGATE should be asserted when the
TL/C/12379 – 35
FIGURE 5-3. Read Data AlgorithmÐState Diagram
TL/C/12379 – 36
FIGURE 5-4. Perpendicular Recording Drive R/W Head and Pre-Erase Head
61
5.0 FDC Functional Description (Continued)
function of the manual low power mode is a logical OR function between the DSR low power bit and the Mode command manual low power bit setting.
Automatic low power mode will switch the controller into low
power 500 ms (at the 500 kbps MFM data rate) after it has
entered the idle state. Once the auto low power mode is set,
it does not have to be set again, and the controller will automatically go into low power mode after it has entered the
idle state. Automatic low power mode can only be set with
the Mode command.
There are two ways the FDC section can recover from the
power-down state. 1) The part will power up after a software
reset via the DOR or DSR. Since a software reset requires
reinitialization of the controller, this method can be undesirable. 2) The part will also power up after a read or write to
either the Data Register or Main Status Register. This is the
preferred method of power up since all internal register values are retained. It may take a few milliseconds for the oscillator to stabilize, and the mP will be prevented from issuing commands during this time through the normal Main
Status Register protocol. That is, the RQM bit in the MSR
will be a 0 until the oscillator has stabilized. When the controller has completely stabilized from power up, the RQM bit
in the MSR is set to 1 and the controller can continue where
it left off.
The Data Rate Select, Digital Output, and Configuration
Control Registers are unaffected by the power-down mode.
They will remain active. It is up to the user to ensure that the
Motor and Drive Select signals are turned off.
5.7 DATA RATE SELECTION
The data rate can be chosen two different ways with the
FDC. For PC compatible software, the Configuration Control
Register at address 3F7h is used to program the data rate
for the floppy controller. The lower bits D1 and D0 are used
in the CCR to set the data rate. The other bits should be set
to zero. See Table 3-7 for the data rate select encoding.
The data rate can also be set using the Data Rate Select
Register at address 4. Again, the lower two bits of the register are used to set the data rate. The encoding of these bits
is exactly the same as those in the CCR. The remainder of
the bits in the DSR are used for other functions. Consult the
Register Description (Section 3.1.6) for more details.
The data rate is determined by the last value that is written
to either the CCR or the DSR. In other words, either the
CCR or the DSR can override the data rate selection of the
other register. When the data rate is selected, the microengine and data separator clocks are scaled appropriately.
Also, the DRATE0 and DRATE1 output pins will reflect the
state of the data select bits that were last written to either
the CCR or the DSR.
5.8 WRITE PRECOMPENSATION
Write precompensation is a way of preconditioning the
WDATA output signal to adjust for the effects of bit shift on
the data as it is written to the disk surface. Bit shift is caused
by the magnetic interaction of data bits as they are written
to the disk surface, and has the effect of shifting these data
bits away from their nominal position in the serial MFM or
FM data pattern. Data that is subject to bit shift is much
harder to read by a data separator, and can cause soft read
errors. Write precompensation predicts where bit shift could
occur within a data pattern. It then shifts the individual data
bits early, late, or not at all such that when they are written
to the disk, the resultant shifted data bits will be back in their
nominal position.
The FDC supports software programmable write precompensation. Upon power up, the default write precomp values
will be used (see Table 3-6). The programmer can choose a
different value of write precomp with the DSR register if
desired (see Table 3-5). Also on power up, the default starting track number for write precomp is track zero. This starting track number for write precomp can be changed with the
Configure command.
Note: If the power to an external oscillator driving the PC87306 is to be
independently removed during the FDC low power mode, it must not
be done until 2 ms after the FDC low power command is issued.
5.10 RESET OPERATION
The floppy controller can be reset by hardware or software.
Hardware reset is enacted by pulsing the Master Reset input pin. A hardware reset will set all of the user addressable
registers and internal registers to their default values. The
Specify command values will be don’t cares, so they must
be reinitialized. The major default conditions are: FIFO disabled, FIFO threshold e 0, Implied Seeks disabled, and
Drive Polling enabled.
A software reset can be performed through the Digital Output Register or Data Rate Select Register. The DSR reset
bit is self-clearing, while the DOR reset bit is not self-clearing. If the LOCK bit in the Lock command was set to a 1
previous to the software reset, the FIFO, THRESH, and
PRETRK parameters in the Configure command will be retained. In addition, the FWR, FRD, and BST parameters in
the Mode command will be retained if LOCK is set to 1. This
function eliminates the need for total reinitialization of the
controller after a software reset.
After a hardware (assuming the FDC is enabled in the FER)
or software reset, the Main Status Register is immediately
available for read access by the mP. It will return a 00h value
until all the internal registers have been updated and the
data separator is stabilized. When the controller is ready to
receive a command byte, the MSR will return a value of 80h
(Request for Master bit is set). The MSR is guaranteed to
return the 80h value within 2.5 ms after a hardware or software reset. All other user addressable registers other than
the Main Status Register and Data Register (FIFO) can be
accessed at any time, even while the part is in reset.
5.9 FDC LOW POWER MODE LOGIC
The FDC section of the PC87306 supports two low power
modes described here in detail. Other low power modes of
the PC87306 are described in Section 2.5. Details concerning entering and exiting low power mode via setting Date
Rate Select Register bit 6 or by executing the FDC Mode
Command are covered below and in Section 3.1.6 and Section 4.1.6. The microcode is driven from the clock, so it will
be disabled while the clock is off. The FDC clock is always
disabled upon entering this mode, however, the oscillator is
only disabled when PTR1 e 1. Upon entering the powerdown state, the RQM (Request For Master) bit in the MSR
will be cleared.
There are two modes of low power in the floppy controller:
manual low power and automatic low power. Manual low
power is enabled by writing a 1 to bit 6 of the DSR. The chip
will go into low power immediately. This bit will be cleared to
0 after the chip is brought out of low power. Manual low
power can also be accessed via the Mode command. The
62
6.0 Serial Ports
Bits 0,1 These two bits specify the number of data bits in
each transmitted or received serial character. The
encoding of bits 0 and 1 is as follows:
Each of these serial ports functions as a serial data input/
output interface in a microcomputer system. The system
software determines the functional configuration of the
UARTs via a 8-bit bidirectional data bus.
The UARTs are completely independent. They perform
serial-to-parallel conversion on data characters received
from a peripheral device or a MODEM, and parallel-to-serial
conversion on data characters received from the CPU. The
CPU can read the complete status of either UART at any
time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART, as well as any error
conditions (parity, overrun, framing, or break interrupt).
The UARTs have programmable baud rate generators that
are capable of dividing the internal reference clock by divisors of 1 to (216 –1), and producing a 16x clock for driving
the transmitter logic. Provisions are also included to use this
16x clock to drive the receiver logic. The UARTs have complete MODEM-control capability and a prioritized interrupt
system. Interrupts can be programmed to the user’s requirements, minimizing the computing required to handle the
communications link.
Bit 2
Bit 3
6.1 SERIAL PORT REGISTERS
Two identical register sets, one for each channel, are in the
PC87306. All register descriptions in this section apply to
the register sets in both channels. See Table 6-1.
Bit 4
TABLE 6-1. PC87306 UART
Register Addresses (AEN e 0)
DLAB
A2
A1
A0
Selected Register
0
0
0
0
Receiver Buffer (Read),
Transmitter Holding (Write)
0
0
0
1
Interrupt Enable
0
0
1
0
Interrupt Identification (Read)
FIFO Control (Write)
X
0
1
1
Line Control
X
1
0
0
MODEM Control
X
1
0
1
Line Status
X
1
1
0
MODEM Status
X
1
1
1
Scratch
1
0
0
0
Divisor Latch
(Least Significant Byte)
1
0
0
1
Divisor Latch
(Most Significant Byte)
Bit 5
Bit 6
Bit 1
Bit 0
Data Length
0
0
5 Bits
0
1
6 Bits
1
0
7 Bits
1
1
8 Bits
This bit specifies the number of Stop bits transmitted with each serial character. If it is 0, one Stop
bit is generated in the transmitted data. If it is 1,
when a 5-bit data length is selected, one and a
half Stop bits are generated. If it is logic 1, when
either a 6-, 7-, or 8-bit word length is selected, two
Stop bits are generated. The receiver checks the
first Stop bit only, regardless of the number of
Stop bits selected.
This bit is the Parity Enable bit. When it is 1, a
Parity bit is generated (transmit data) or checked
(receive data) between the last data bit and Stop
bit of the serial data. (The Parity bit is used to
produce an even or odd number of 1s when the
data bits and the Parity bit are summed.)
This bit is the Even Parity Select bit. When parity is
enabled and bit 4 is 0, an odd number of logic 1s
is transmitted or checked in the data word bits and
Parity bit. When parity is enabled and bit 4 is 1, an
even number of logic 1s is transmitted or checked.
This bit is the Stick Parity bit. When parity is enabled it is used in conjunction with bit 4 to select
Mark or Space Parity. When LCR bits 3, 4 and 5
are 1 the Parity bit is transmitted and checked as a
0 (Space Parity). If bits 3 and 5 are 1 and bit 4 is a
0, then the Parity bit is transmitted and checked as
1 (Mark Parity). If bit 5 is 0 Stick Parity is disabled.
This bit is the Break Control bit. It causes a break
condition to be transmitted to the receiving UART.
When it is set to 1, the serial output (SOUT) is
forced to the Spacing state (0). The break is disabled by setting bit 6 to 0. The Break Control bit
acts only on SOUT and has no effect on the transmitter logic.
Note that this feature enables the CPU to alert a
terminal. If the following sequence is used, no erroneous characters will be transmitted because of
the break.
1. Wait for the transmitter to be idle, (TEMT e 1).
2. Set break for the appropriate amount of time. If
the transmitter will be used to time the break
duration, then check that TEMT e 1 before
clearing the Break Control bit.
3. Clear break when normal transmission has to
be restored.
During the break, the Transmitter can be used as
a character timer to accurately establish the break
duration by sending characters and monitoring
THRE and TEMT.
6.2 LINE CONTROL REGISTER (LCR)
Read/Write
The system programmer uses the Line Control Register
(LCR) to specify the format of the asynchronous data communications exchange and set the Divisor Latch Access bit.
This is a read and write register. Table 6-2 shows the contents of the LCR. Details on each bit follow.
TL/C/12379 – 37
FIGURE 6-1. PC87306 Composite Serial Data
63
6.0 Serial Ports (Continued)
TABLE 6-2. PC87306 Register Summary for an Individual UART Channel
Register Address
Bit
No.
A0 –2 e 0
DLAB e 0
A0 –2 e 0
DLAB e 0
A0 – 2 e 1
DLAB e 0
2
2
3
4
5
6
7
Receiver
Buffer
Register
(Read
Only)
Transmitter
Holding
Register
(Write
Only)
Interrupt
Enable
Register
Interrupt
Ident.
Register
(Read
Only)
FIFO
Control
Register
(Write
Only)
Line
Control
Register
MODEM
Control
Register
Line
Status
Register
MODEM
Status
Register
Scratch
Pad
Register
A0– 2 e 0 A0– 2 e 1
DLAB e 1 DLAB e 1
Divisor
Latch
(LSB)
Divisor
Latch
(MSB)
RBR
THR
IER
IIR
FCR
LCR
MCR
LSR
MSR
SCR
DLL
DLM
0
Data Bit 0
(Note 1)
Data Bit 0
Enable
Received
Data
Available
Interrupt
‘‘0’’ if
Interrupt
Pending
FIFO
Enable
Word
Length
Select
Bit 0
Data
Terminal
Ready
(DTR)
Data
Ready
(DR)
Delta
Clear
to Send
Bit 0
Bit 0
Bit 8
1
Data Bit 1
Data Bit 1
Enable
Transmitter
Holding
Register
Empty
Interrupt
Interrupt
ID
Bit
RCVR
FIFO
Reset
Word
Length
Select
Bit 1
Request
to Send
(RTS)
Overrun
Error
(OE)
Delta
Data
Set
Ready
Bit 1
Bit 1
Bit 9
2
Data Bit 2
Data Bit 2
Enable
Receiver
Line Status
Interrupt
Interrupt
ID
Bit
XMIT
FIFO
Reset
Number of
Stop Bits
Out 1
Bit
(Note 3)
Parity
Error
(PE)
Trailing
Edge Ring
Indicator
Bit 2
Bit 2
Bit 10
3
Data Bit 3
Data Bit 3
Enable
MODEM
Status
Interrupt
Interrupt
ID
Bit
(Note 2)
Reserved
Parity
Enable
IRQ
Enable
Framing
Error
(FE)
Delta
Data
Carrier
Detect
Bit 3
Bit 3
Bit 11
4
Data Bit 4
Data Bit 4
0
0
Reserved Even Parity
Select
Loop
Break
Interrupt
(BI)
Clear to
Send
Bit 4
Bit 4
Bit 12
5
Data Bit 5
Data Bit 5
0
0
Reserved
Stick
Parity
0
Transmitter
Holding
Register
(THRE)
Data
Set
Ready
Bit 5
Bit 5
Bit 13
6
Data Bit 6
Data Bit 6
0
FIFOs
Enabled
(Note 2)
RCVR
Trigger
(LSB)
Set
Break
0
Transmitter
Empty
(TEMT)
Ring
Indicator
Bit 6
Bit 6
Bit 14
7
Data Bit 7
Data Bit 7
0
FIFOs
Enabled
(Note 2)
RCVR
Trigger
(MSB)
Divisor
Latch
Access Bit
(DLAB)
0
Error in
RCVR
FIFO
(Note 2)
Data
Carrier
Detect
Bit 7
Bit 7
Bit 15
Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
Note 2: These bits are always 0 in the NS16450 Mode.
Note 3: This bit no longer has a pin associated with it.
64
6.0 Serial Ports (Continued)
TABLE 6-3. PC87306 UART Reset Configuration
Register or Signal
Reset Control
Reset State
Interrupt Enable
Master Reset (MR)
0000 0000 (Note 1)
Interrupt Identification
Master Reset
0000 0001
FIFO Control
Master Reset
0000 0000
Line Control
Master Reset
0000 0000
MODEM Control
Master Reset
0000 0000
Line Status
Master Reset
0110 0000
MODEM Status
Master Reset
XXXX 0000 (Note 2)
SOUT
Master Reset
High
INTR (RCVR Errs)
Read LSR/MR
Low/TRI-STATE
INTR (RCVR Data Ready)
Read RBR/MR
Low/TRI-STATE
INTR (THRE)
Read IIR/Write THR/MR
Low/Low/TRI-STATE
INTR (Modem Status Changes)
Read MSR/MR
Low/TRI-STATE
Interrupt Enable Bit
Master Reset
Low
RTS
Master Reset
High
DTR
Master Reset
High
RCVR FIFO
MR or (FCR1 e 1 and FCR0 e 1) or Change in FCR0
All Bits Low
XMIT FIFO
MR or (FCR2 e 1 and FCR0 e 1) or Change in FCR0
All Bits Low
Note 1: Boldface bits are permanently low.
Note 2: Bits 7–4 are driven by the input signals.
Bit 7
This bit is the Divisor Latch Access Bit (DLAB). It
must be set high (logic 1) to access the Divisor
Latches of the Baud rate Generator during a Read
or Write operation or to have the Baud Out
(BOUT) signal appear on the BOUT pin. It must be
set low (logic 0) to access any other register.
TABLE 6-4. PC87306 UART Divisors,
Baud Rates and Clock Frequencies
24 MHz Input Divided to 1.8462 MHz
6.3 PROGRAMMABLE BAUD RATE GENERATOR
The PC87306 contains two independently programmable
Baud rate Generators. The 24 MHz oscillator frequency input is divided by 13, resulting in a frequency of 1.8462 MHz.
This is sent to each Baud rate Generator and divided by the
divisor of the associated UART. The output frequency of the
Baud rate Generator (BOUT1,2) is 16 c the baud rate.
divisor Ý e (frequency input) (baud rate c 16)
The output of each Baud rate Generator drives the transmitter and receiver sections of the associated serial channel.
Two 8-bit latches per channel store the divisor in a 16-bit
binary format. These Divisor Latches must be loaded during
initialization to ensure proper operation of the Baud rate
Generator. Upon loading either of the Divisor Latches, a
16-bit Baud Counter is loaded. Table 6-4 provides decimal
divisors to use with crystal frequencies of 24 MHz. The oscillator input to the chip should always be 24 MHz to ensure
that the Floppy Disk Controller timing is accurate and that
the UART divisors are compatible with existing software.
Using a divisor of zero is not recommended.
Baud Rate
Decimal Divisor
for 16x Clock
Percent
Error (Note)
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
57600
115200
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2
1
0.1
0.4
0.5
Note: The percent error for all baud rates, except where indicated otherwise
is 0.2%.
65
6.0 Serial Ports (Continued)
Bit 5
6.4 LINE STATUS REGISTER (LSR)
This 8-bit register provides status information to the CPU
concerning the data transfer. Table 6-2 shows the contents
of the Line Status Register. Details on each bit follow:
Bit 0 This bit is the receiver Data Ready (DR) indicator. It
is set to 1 whenever a complete incoming character
has been received and transferred into the Receiver
Buffer Register or the FIFO. It is reset to 0 by reading the data in the Receiver Buffer Register or the
FIFO.
Bit 1 This bit is the Overrun Error (OE) indicator. It indicates that data in the Receiver Buffer Register was
not read by the CPU before the next character was
transferred into the Receiver Buffer Register, thereby destroying the previous character. The OE indicator is set to 1 upon detection of an overrun condition,
and reset whenever the CPU reads the contents of
the Line Status Register. If the FIFO mode data continues to fill the FIFO beyond the trigger level, an
Overrun error will occur only after the FIFO is completely full and the next character has been received
in the shift register. OE is indicated to the CPU as
soon as it happens. The character in the shift register is overwritten, but is not transferred to the FIFO.
Bit 2 This bit is the Parity Error (PE) indicator. It indicates
that the received data character does not have the
correct parity, as selected by the even-parity select
bit. The PE bit is set to 1 upon detection of a parity
error and is reset to 0 whenever the CPU reads the
contents of the Line Status Register. In the FIFO
mode this error is associated with the particular
character in the FIFO that it applies to. This error is
revealed to the CPU when its associated character is
at the top of the FIFO.
Bit 3 This bit is the Framing Error (FE) indicator. It indicates that the received character did not have a valid Stop bit. It is set to 1 whenever the Stop bit following the last data bit or parity bit is a 0 (Spacing level).
The FE indicator is reset whenever the CPU reads
the contents of the Line Status Register. In the FIFO
mode this error is associated with the particular
character in the FIFO that it applies to. This error is
revealed to the CPU when its associated character is
at the top of the FIFO. The UART will try to resynchronize after a framing error by assuming that the
error was due to the next start bit. It samples this
‘‘start’’ bit twice and then takes in the bits following it
as the rest of the frame.
Bit 4 This bit is the Break Interrupt (BI) indicator. It is set
to 1 whenever the received data input is held in the
Spacing (0) state for longer than a full word transmission time (i.e., the total time of Start bit a data
bits a Parity a Stop bits). The BI indicator is reset
whenever the CPU reads the contents of the Line
Status Register. In the FIFO mode this error is associated with the particular character in the FIFO that it
applies to. This error is revealed to the CPU when its
associated character is at the top of the FIFO. When
break occurs only one character is loaded into the
FIFO. To Restart after a break is received, the SIN
pin must be 1 for at least (/2 bit time.
Bit 6
Bit 7
This bit is the Transmitter Holding Register Empty
(THRE) indicator. It indicates that the UART is ready
to accept a new character for transmission. In addition, it causes the UART to issue an interrupt to the
CPU when the Transmit Holding Register Empty Interrupt enable is set high. The THRE bit is set to 1
when a character is transferred from the Transmitter
Holding Register into the Transmitter Shift Register.
The bit is reset to 0 whenever the CPU loads the
Transmitter Holding Register. In the FIFO mode it is
set when the XMIT FIFO is empty; it is cleared when
at least 1 byte is written to the XMIT FIFO.
This bit is the Transmitter Empty (TEMT) indicator. It
is set to 1 whenever the Transmitter Holding Register (THR) and the Transmitter Shift Register (TSR)
are both empty. It is reset to 0 if either the THR or
TSR contains a data character. In the FIFO mode
this bit is set to 1 whenever the transmitter FIFO and
the shift register are both empty.
In the NS16450 Mode this is 0. In the FIFO Mode
this bit is set when there is at least one parity error,
framing error or break indication in the FIFO. It is
cleared when the CPU reads the LSR, if there are no
subsequent errors in the FIFO.
Note: The Line Status Register is intended for read operations
only. Writing to this register is not recommended as this
operation is only used for factory testing. In the FIFO mode
the software must load a data byte in the Rx FIFO via the
Loopback Mode in order to write to LSR2–LSR4. LSR0 and
LSR7 can’t be written to in FIFO Mode.
6.5 FIFO CONTROL REGISTER (FCR)
This is a write-only register at the same location as the IIR
(the IIR is a read-only register). This register is used to enable the FIFOs, clear the FIFOs and to set the RCVR FIFO
trigger level.
Bit 0
Writing a 1 to FCR0 enables both the XMIT and
RCVR FIFOs. Resetting FCR0 clears all bytes in
both FIFOs. When changing from FIFO Mode to
NS16450 Mode and vice versa, data is automatically cleared from the FIFOs. This bit must already be 1 when other FCR bits are written to or
they will not be programmed.
Bit 1
Writing 1 to FCR1 clears all bytes in the RCVR
FIFO and resets its counter logic to 0. The shift
register is not cleared. The 1 that is written to this
bit position is self-clearing.
Bit 2
Writing 1 to FCR2 clears all bytes in the XMIT
FIFO and resets its counter logic to 0. The shift
register is not cleared. The 1 that is written to this
bit position is self-clearing.
Bit 3
Writing to FCR3 does not change UART operations.
Bits 4, 5 FCR4 and FCR5 are reserved for future use.
Bits 6, 7 The combination of FCR6 and FCR7 are used to
designate the interrupt trigger level. See Figure
6-2 . When the number of bytes in the RCVR FIFO
equals the designated interrupt trigger level, a Received Data Available Interrupt is activated. This
interrupt must be enabled by setting the Interrupt
Enable Register (IER) bit 0.
Note: Bits 1 through 4 are the error conditions that produce a
Receiver Line Status interrupt whenever any of the corresponding conditions are detected and the interrupt is enabled.
66
6.0 Serial Ports (Continued)
FCR Bits
7
6
RCVR FIFO
Trigger Level (Bytes)
0
0
01
0
1
04
1
0
08
1
1
14
Bit 3
This bit enables the MODEM Status Interrupt
when set to logic 1.
Bits 4 – 7 These four bits are always logic 0.
6.8 MODEM CONTROL REGISTER (MCR)
This register controls the interface with the MODEM or data
set (or a peripheral device emulating a MODEM). The contents of the MODEM Control Register (MCR) are indicated
in Table 6-2 and are described as follows:
Bit 0
This bit controls the Data Terminal Ready (DTR)
output. When it is set to 1, the DTR output is
forced to a logic 0. When it is reset to 0, the DTR
output is forced to 1. In Local Loopback Mode, this
bit controls bit 5 of the MODEM Status Register.
FIGURE 6-2. Receiver FIFO Trigger Level
6.6 INTERRUPT IDENTIFICATION REGISTER (IIR)
In order to provide minimum software overhead during data
character transfers, the UART prioritizes interrupts into four
levels and records these in the Interrupt Identification Register. The four levels of interrupt conditions in order of priority are Receiver Line Status; Received Data Ready; Transmitter Holding Register Empty; and MODEM Status.
When the CPU accesses the IIR, the UART freezes all interrupts and indicates the highest priority pending interrupt to
the CPU. While this CPU access is occurring, the UART
records new interrupts, but does not change its current indication until the current access is complete. Table 6-2 shows
the contents of the IIR. Details on each bit follow.
Bit 0
This bit can be used in an interrupt environment to
indicate whether an interrupt condition is pending.
When it is 0, an interrupt is pending and the IIR
contents may be used as a pointer to the appropriate interrupt service routine. When it is 1, no interrupt is pending. See Table 6-5.
Bits 1, 2 These two bits of the IIR are used to identify the
highest priority interrupt pending as indicated in
Table 6-5.
Bit 3
In the 16450 mode this bit is 0. In the FIFO mode it
is set along with bit 2 when a time-out interrupt is
pending. See Table 6-5.
Bits 4, 5 These bits of the IIR are always 0.
Bits 6, 7 These two bits are set when FCR0 e 1. (FIFO
Mode enabled.)
Note: The DTR and RTS output of the UART may be applied to
an EIA inverting line driver (such as the DS1488) to obtain the proper polarity input at the MODEM or data set.
This bit controls the Request to Send (RTS) output. Its effect on the RTS output is identical to that
described above for bit 0. In Local Loopback
Mode, this bit controls bit 4 of the MODEM
Status Register.
Bit 2
This bit is the OUT1 bit. It does not have an output
pin associated with it. It can be written to and read
by the CPU. In Local Loopback Mode, this bit controls bit 6 of the MODEM Status Register.
Bit 3
This bit enables the interrupt when set. No external pin is associated with this bit other than IRQ3,
4. In Local Loopback Mode, this bit controls bit 7
of the MODEM Status Register.
Bit 4
This bit provides a Local loopback feature for diagnostic testing of the UART. When it is set to 1, the
following changes take place: the transmitter Serial Output (SOUT) is set to the Marking (1) state;
the receiver Serial Input (SIN) is disconnected; the
output of the Transmitter Shift Register is ‘‘looped
back’’ (connected) to the Receiver Shift Register;
the four MODEM Control inputs (DSR, CTS, RI
and DCD) are disconnected; and the DTR, RTS,
OUT1, IRQ ENABLE bits in MCR are internally
connected to DSR, CTS, RI and DCD in MSR, respectively. The MODEM Control output pins are
forced to their high (inactive) states. In the Loopback Mode, data that is transmitted is immediately
received. This feature allows the processor to verify the transmit-and-received-data paths of the serial port.
In the Loopback Mode, the receiver and transmitter interrupts are fully operational. The MODEM
Status Interrupts are also operational, but the interrupts’ sources are the lower four bits of MCR
instead of the four MODEM control inputs. Writing
a 1 to any of these 4 MCR bits will cause an interrupt. In Loopback Mode the interrupts are still controlled by the Interrupt Enable Register. The IRQ3
and IRQ4 pins will be at TRI-STATE in the Loopback Mode.
Bits 5 – 7 These bits are permanently set to 0.
Bit 1
6.7 INTERRUPT ENABLE REGISTER (IER)
This register enables the five types of UART interrupts.
Each interrupt can individually activate the appropriate interrupt (IRQ3 or IRQ4) output signal. It is possible to totally
disable the interrupt system by resetting bits 0 through 3 of
the Interrupt Enable Register (IER). Similarly, setting bits of
this register to 1, enables the selected interrupt(s). Disabling
an interrupt prevents it from being indicated as active in the
IIR and from activating the interrupt output signal. All other
system functions operate in their normal manner, including
the setting of the Line Status and MODEM Status Registers.
Table 6-2 shows the contents of the IER. Details on each bit
follow. See MODEM Control Register bit 3 for more information on enabling the interrupt pin.
Bit 0
When set to 1 this bit enables the Received Data
Available Interrupt and Timeout Interrupt in the
FIFO Mode.
Bit 1
This bit enables the Transmitter Holding Register
Empty Interrupt when set to 1.
Bit 2
This bit enables the Receiver Line Status Interrupt
when set to logic 1.
67
6.0 Serial Ports (Continued)
TABLE 6-5. PC87306 Interrupt Control Functions
Interrupt
Identification
Register
Interrupt Set and Reset Functions
Bit 3
(FIFO
Mode
Only)
Bit 2
Bit 1
Bit 0
0
0
0
1
Ð
None
None
0
1
1
0
Highest
Receiver Line
Status
Overrun Error, Parity Error,
Framing Error or Break Interrupt
Reading the Line
Status Register
0
1
0
0
Second
Received Data
Available
Receiver Data Available
Read Receiver Buffer
1
1
0
0
Second
(FIFO
Mode
Only)
Character
Time-Out
Indication
No Characters Have Been
Removed from or input to the
RCVR FIFO During the Last 4
Character Times and there is at
least 1 Character in it during this
Time.
Reading the Receiver
Buffer Register
0
0
1
0
Third
Transmitter Holding
Register Empty
Transmitter Holding
Register Empty
Reading the IIR Register
(if Source of Interrupt) or
Writing the Transmitter
Holding Register
0
0
0
0
Fourth
MODEM Status
Clear to Send or Data Set
Ready or Ring Indicator or
Data Carrier Detect
Reading the MODEM
Status Register
Priority
Level
Interrupt Type
Bit 6
6.9 MODEM STATUS REGISTER (MSR)
This register provides the current state of the control lines
from the MODEM (or peripheral device) to the CPU. In addition to this current-state information, four bits of the
MODEM Status Register provide change information. These
bits are set to a logic 1 whenever a control input from the
MODEM changes state. They are reset to logic 0 whenever
the CPU reads the MODEM Status Register. Table 6-2
shows the contents of the MSR. Details on each bit follow.
Bit 0 This bit is the Delta Clear to Send (DCTS) indicator.
Bit 0 indicates that the CTS input to the chip has
changed state since the last time it was read by the
CPU.
Bit 1 This bit is the Delta Data Set Ready (DDSR) indicator. It indicates that the DSR input to the chip has
changed state since the last time it was read by the
CPU.
Bit 2 This bit is the Trailing Edge of Ring Indicator (TERI)
detector. It indicates that the RI input to the chip has
changed from a low to a high state.
Bit 3 This bit is the Delta Data Carrier Detect (DDCD) indicator. It indicates that the DCD input to the chip
has changed state.
Bit 7
Bit 5
Interrupt Reset
Control
Ð
This bit is the complement of the Ring Indicator (RI)
input. If bit 4 of the MCR is set to a 1, this bit is
equivalent to OUT1 in the MCR.
This bit is the complement of the Data Carrier Detect (DCD) input. If bit 4 of the MCR is set to a 1, this
bit is equivalent to IRQ ENABLE in the MCR.
6.10 SCRATCHPAD REGISTER (SCR)
This 8-bit Read/Write Register does not control the UART
in any way. It is intended as a scratchpad register to be used
by the programmer to hold data temporarily.
7.0 Serial Infrared Wireless
Communication Port
The PC87306 supports a serial InfraRed (IR) wireless communication port. An IR interface connects a UART’s serial in
and serial out signals via one or more transmitter LED and
receiver photo diode pairs.
The IR port of the PC87306 is hooked to UART2. SOUT of
UART2 is also encoded by the PC87306 and routed to the
InfraRed Transmitter (IRTX) pin. The InfraRed Receiver pin
(IRRX) is decoded by the PC87306 and routed to the SIN
signal of UART2.
There are two UART2 interface modes:
Note: Whenever bit 0, 1, 2, or 3 is set to logic 1, a MODEM Status
Interrupt is generated.
Bit 4
Interrupt Source
# Normal (MODEM) mode: The normal NS16550A UART
This bit is the complement of the Clear to Send
(CTS) input. If bit 4 (loopback) of the MCR is set to a
1, this bit is equivalent to RTS in the MCR.
This bit is the complement of the Data Set Ready
(DSR) input. If bit 4 of the MCR is set to a 1, this bit
is equivalent to DTR in the MCR.
interface.
# IR mode: InfraRed mode, IrDA compliant.
A system board can have a PC87306 configured with two
UARTs and one IR interface because these functions utilize
separate pins on the device. The selection of UART2 interface mode is a run-time selection that yields either two
68
7.0 Serial Infrared Wireless Communication Port (Continued)
PMC bit 2 for UART TRI-STATE control. An additional register, the IRC (InfraRed Configuration), is provided to configure the IR interface. Also, UART2’s IRQ mapping can be
modified using the PNP1 register.
The state of UART2 pins for both modes follow.
In IR mode (IRC.0 e 1) the default values for the following
UART2 pins are:
RI2 and DCD2 are 1.
DSR2 and CTS2 are 0.
SOUT2 is driven high (inactive).
In Normal (MODEM) mode (IRC.0 e 0) the default value for
the IR port pins are:
IRRX is 1.
IRTX is driven low (inactive).
Float Control: UART2 pins (except IRQ3 and IRQ4) and IR
pins IRTX and IRRX are controlled by the UART2 TRISTATE control bit (bit 3 of SCF0). The outputs are in TRISTATE, and the inputs are blocked to reduce the leakage
current, when the UART2 TRI-STATE control bit is 1, and
either UART2 is disabled or the PC87306 is in power-down
mode.
UARTs, or one UART plus one IR port, simultaneously. Normal (MODEM) mode implies two UARTs. IR mode implies
one UART plus one IR port.
The IR port is either Full Duplex or Half Duplex where:
# Full Duplex e Both transmitter and receiver are enabled
simultaneously.
# Half Duplex e The receiver input is blocked to ‘‘1’’ while
the transmitter is busy; from the beginning of the start bit
till the end of the stop bit(s).
The IR port is either in Encoded mode or Non-Encoded
mode where:
# Encoded mode e UART2’s SOUT pin is encoded and
routed to the IRTX pin, and the IRRX pin is decoded and
routed to UART2’s SIN pin.
# Non-Encoded mode e UART2’s SOUT pin is inverted
and routed to the IRTX pin, and the IRRX is routed to
UART2’s SIN pin.
When in Encoded mode, the IR port’s output signal (IRTX) is
active for intervals of either 1.6 ms or 3/16 baud.
Configuration of UART2 is still handled via the FER, FAR,
and PTR registers. However, SCF0 bit 3 is used instead of
TL/C/12379 – 38
FIGURE 7-1. UART2 Serial and IR Interface Block Diagram
69
8.0 Parallel Port
TABLE 8-3. SPP Data Register Read and Write Modes
8.1 INTRODUCTION
This parallel interface is designed to provide all of the signals and registers needed to communicate through a standard parallel printer port as found in the IBM PC-XT, PC-AT,
PS/2 and Centronics systems. This parallel port supports
three standard modes of operation: SPP, EPP, ECP. The
Standard Parallel Port (SPP) is a software based protocol
with performance of up to 150 kbps.
The Enhanced Parallel Port (EPP) is a hardware protocol
which offers up to 2 Mbps.
The Extended Capabilities Port (ECP) is also a hardware
protocol with up to 2 Mbps transfer rate. In addition, the
ECP has FIFO’s for receive and transmit, and DMA support,
to reduce the CPU overhead. The ECP mode 0 is in fact
compatible with the SPP mode. The ECP specification defines the AC/DC parameters of the signals to allow fast
communication without termination problems.
All the above standards are incorporated into the 1284 IEEE
specifications.
The address decoding of the registers in SPP mode utilizes
A0 and A1 as shown in Table 8-1. (Address decoding of
registers in EPP and ECP modes is shown in Table 8-5 and
8-7 respectively.) Table 8-3 shows the Reset states of Parallel port registers and pin signals. These registers are
shown in Section 8.2 to Section 8.4.
A0
Address
0
0
0
Data
Register
Read/Write
0
1
1
Status
Read
1
0
2
Control
Read/Write
1
1
3
TRI-STATE
Access
0
1
0
Data Written to PD0 – 7
Result
0
X
0
1
Data Read from the Output
Latch
1
0
1
0
Data Written to PD0 – 7
1
1
1
0
Data Written is Latched
1
0
0
1
Data Read from the Output
Latch
1
1
0
1
Data Read from PD0 – 7
This is a bidirectional data port that transfers 8-bit date. The
direction is determined by the PTR7 and the CTR5 bits.
When PTR7 is high, the CTR5 bit will determine the data
direction in conjunction with the Read and Write strobes.
When PTR7 bit is low, the parallel port operates in the output mode only. See PTR7 bit and CTR5 bit for further information. The reset value of this register is 0. See Table 8-3.
PTR7
Extended
WR
1
TL/C/12379 – 39
TABLE 8-2. Standard Parallel Port
Modes Selection
Port Function
RD
X
8.2 DATA REGISTER (DTR)
Special circuitry provides protection against damage that
might be caused when the printer is powered but the
PC87306 is not.
There are two Standard Parallel Port (SPP) modes of operation (Compatible and Extended, see Table 8-2), two Enhanced Parallel Port (EPP) modes of operation and one Extended Capabilities Port (ECP) mode to complete a full IEEE
1284 parallel port.
Compatible
CTR5
0
To support a high transfer rate, the I/O buffers of the parallel port signals require improved impedance matching. IEEE
P1284 defines two types of I/O buffers, Level 1 (standard
I/O buffersÐopen-drain with weak pull-up), and Level 2
(new I/O buffersÐpush-pull with driver impedance and slew
rate according to new standards).
IEEE P1284, Draft 2.00, September 10, 1993, Microsoft’s
ECP Protocol, and ISA Interface Standard, revision 1.14,
July 7, 1993 provide detailed descriptions of Level 2 I/O
buffers.
When in EPP 1.9 or ECP mode 3, or ECP mode 2 with bit 1
of PCR equal to 1, the following parallel port pins have Level
2 I/O buffers: PD0 – PD7, STB, AFD, INIT, SLIN, ACK, ERR,
SLCT, PE and BUSY.
(See DC Electrical Characteristics, Section 11.1 for further
information.)
TABLE 8-1. Parallel Interface Register Addresses
A1
PTR7
8.3 STATUS REGISTER (STR)
In Compatible mode a write operation causes the data to be
presented on pins PD0–PD7. A read operation in this mode
causes the Data Register to present the last data written to
it by the CPU. See Table 8-3.
In the Extended Mode a write operation to the data register
causes the data to be latched. If the Data Port Direction bit
(CTR5) is 0, the latched data is presented to the pins; if it is
1 the data is only latched. When Data Port Direction bit
(CTR5) is 0, a read operation from this register allows the
CPU to read the last data it wrote to the port. In the Extended Mode with the Data Port Direction bit set to 1 (read), a
read from this register causes the port to present the data
on pins PD0 – PD7.
TL/C/12379 – 40
This register provides status for the signals listed below. It is
a read only register. Writing to it is an invalid operation that
has no effect.
70
8.0 Parallel Port (Continued)
Bit 0 When in EPP mode, this is the timeout status bit.
When this bit is 0, no timeout.
When this bit is 1, timeout occurred on EPP cycle
(minimum 10 ms).
It is cleared to 0 after STR is read, i.e., consecutive
reads (after the first read) always return 0. It is also
cleared to 0 when EPP is enabled (bit 0 of PCR is
changed from 0 to 1).
When not in EPP mode, this bit is 1.
Bit 1 Reserved, this bit is always 1.
Bit 2 In the compatible mode (PTR7 bit is 0), or in ECP and
EPP modes, this bit is always one.
In the Extended Mode (PTR7 bit is 1), or in ECP and
EPP with bit 4 of PCR e 1, this bit is the IRQ
STATUS bit.
In the Extended mode if CTR4 e 1, then this bit is
latched low when the ACK signal makes a transition
from low to high. Reading this bit sets it to a one.
Bit 3 This bit represents the current state of the printer
error signal (ERROR). The printer sets this bit low
when there is a printer error. This bit follows the state
of the ERR pin.
Bit 4 This bit represents the current state of the printer
select signal (SLCT). The printer sets this bit high
when it is selected. This bit follows the state of the
SLCT pin.
Bit 5 This bit represents the current state of the printer
paper end signal (PE). The printer sets this bit high
when it detects the end of the paper. This bit follows
the state of the PE pin.
Bit 6 This bit represents the current state of the printer
acknowledge signal (ACK). The printer pulses this
signal low after it has received a character and is
ready to receive another one. This bit follows the
state of the ACK pin.
Bit 7 This bit (BUSY) represents the current state of the
printer busy signal. The printer sets this bit low when
it is busy and cannot accept another character. This
bit is the inverse of the (BUSY/WAIT) pin.
Bit 2
This bit (INIT) directly controls the signal to initialize the printer via the INIT pin. Setting this bit to
low initializes the printer. This bit follows the INIT
pin.
Note: This pin must be set to 1 before enabling the EPP or ECP
modes via bits 0 or 2 of the PCR register.
Bit 3
This bit (SLIN) directly controls the select in signal
to the printer via the SLIN pin. Setting this bit high
selects the printer. It is the inverse of the SLIN pin.
Bit 4
This bit controls the parallel port generated by the
ACK signal. Its function changes slightly depending on the parallel port mode selected. In ECP
mode this bit should be set to 0. In the following
description, IRQx indicates either IRQ5 or IRQ7
(based upon PTR3).
Compatible mode:
when bit 4 e 0 IRQx is floated
when bit 4 e 1 IRQx follows ACK transitions
Extended mode:
when bit 4 e 0 IRQx is floated
when bit 4 e 1 IRQx becomes active on ACK trailing edge
EPP mode:
when bit 4 e 0 IRQx is floated
when bit 4 e 1 IRQx follows ACK transitions, or
an EPP timeout occurs.
Bit 5
This bit determines the parallel port direction when
bit 7 of PTR is 1. The default condition results in
the parallel port being in the output mode. This is a
Read/Write bit in EPP mode, and the software
should write a 1 to it. In SPP mode it is a write only
bit; a read from it will return 1. See Table 8-3 for
further details.
Bits 6, 7 Reserved. These bits are always 1.
Normally when the Control Register is read, the bit values
are provided by the internal output data latch. These bit
values can be superseded by the logic level of the STB,
AFD, INIT, and SLIN pins, if these pins are forced high or
low by an external voltage. In order to force these pins high
or low the corresponding bits should be set to their inactive
state (e.g., AFD e STB e SLIN e 0, INIT e 1). See Table
8-4.
TABLE 8-4. Parallel Port Reset States
8.4 CONTROL REGISTER (CTR)
Signal
TL/C/12379 – 41
This register provides all output signals to control the printer. Except for bit 5, it is a read and write register.
Bit 0
This bit (STB) directly controls the data strobe signal to the printer via the STB pin. This bit is the
inverse of the STB pin.
Bit 1
This bit (AFD) directly controls the automatic feed
XT signal to the printer via the AFD pin. Setting this
bit high causes the printer to automatically feed
after each line is printed. This bit is the inverse of
the AFD pin.
Reset Control
State after Reset
SLIN
MR
TRI-STATE
INIT
MR
Zero
AFD
MR
TRI-STATE
STB
MR
TRI-STATE
IRQ5, 7
MR
TRI-STATE
8.5 ENHANCED PARALLEL PORT OPERATION
EPP mode provides for greater throughput, and more complexity, than Compatible or Extended modes by supporting
faster transfer times and a mechanism that allows the host
to address peripheral device registers directly. Faster transfers are achieved by automatically generating the address
and data strobes. EPP is compatible with both Compatible
and Extended mode parallel-port devices. It consists of
eight (0 – 7) single-byte registers (See Table 8-5).
71
8.0 Parallel Port (Continued)
TABLE 8-5. EPP Register Addresses
A2
A1
A0
Address
Register
Access
Description
0
0
0
0
Data (DTR)
R/W
A write to this register sets the state of the eight data pins on the 25-pin Dshell connector.
0
0
1
1
Status (STR)
R
A read from this register presents the system microprocessor with the
real-time status of five pins on the 25-pin D-shell connector, and the IRQ.
0
1
0
2
Control (CTR)
R/W
A write operation to this port sets the state of four pins on the 25-pin Dshell connector, and controls both the parallel port interrupt enable and
direction.
0
1
1
3
Address
R/W
A write operation to this port initiates an EPP device/register selection
operation.
1
0
0
4
Data Port 0
R/W
Accesses to this port initiate device read or write operations with bits 0 – 7.
1
0
1
5
Data Port 1
R/W
This port is only accessed to transfer bits 8 to 15 of a 16-bit read or write
to data port 0.
1
1
0
6
Data Port 2
R/W
This port is only accessed to transfer bits 16 to 23 of a 32-bit read or write
to data port 0.
1
1
1
7
Data Port 3
R/W
This port is only accessed to transfer bits 24 to 31 of a 32-bit read or write
to data port 0.
4. When IOCHRDY goes high it causes WR to go high. If
WAIT is high during the host write cycle then the EPP
does not pull IOCHRDY to low.
5. When WR goes high it causes the EPP to pull WRITE
and ASTRB to high.
Only when WRITE and ASTRB are high can the EPP
change PD0 – 7.
There are two EPP modes:
EPP rev 1.7 is supported when bit 0 of PCR is 1, and bit 1 of
PCR is 0.
EPP rev 1.9 (IEEE 1284) is supported when bit 0 of PCR is
1, and bit 1 of PCR is 1.
EPP is supported for a parallel port whose base address is
8-bytes aligned (A0, 1, 2 e 0, 0, 0). Otherwise unpredictable
results occur. There are four EPP transfer operations: address write, address read, data write and data read. An EPP
transfer operation is composed of a host read or write cycle
(from or to an EPP register) and an EPP read or write cycle
(from a peripheral device to an EPP register, or from an EPP
register to a peripheral device).
The software must write zero to bits 0, 1 and 3 of the CTR
register, before accessing the EPP registers, since the pins
controlled by these bits are controlled by hardware during
EPP access. Once these bits are written with zero, the software may issue multiple EPP access cycles. When EPP is
enabled, the software should write a 1 to bit 5 of CTR.
To meet the EPP 1.9 specifications, the software should
write to DTR only when bit 7 of STR is 1.
EPP 1.7 Address Write
The following procedure selects a peripheral device or register. See also Figure 8-1 .
1. The host writes a byte to the EPP address register. WR
goes low to latch D0–D7 into the address register. The
latch drives the address register onto PD0–7 and the
EPP pulls WRITE low.
2. The EPP pulls ASTRB low to indicate that data has been
sent.
3. If WAIT is low during the host write cycle, IOCHRDY
goes low.
When WAIT goes high, the EPP pulls IOCHRDY high.
TL/C/12379 – 42
FIGURE 8-1. EPP 1.7 Address Write
EPP 1.7 Address Read
The following procedure reads from the address register.
See also Figure 8-2 .
1. The host reads a byte from the EPP address register. RD
goes low to gate PD0 – 7 into D0 – 7.
2. The EPP pulls ASTRB low to signal the peripheral to
start sending data.
72
8.0 Parallel Port (Continued)
5. If the peripheral is fast enough to pull WAIT low before
the host terminates the write cycle, the EPP pulls
IOCHRDY to low, but does not pull ZWS to low, thus
carrying out a normal (non-ZWS EPP 1.7) write operation.
3. If WAIT is low during the host read cycle, then the EPP
pulls IOCHRDY low.
When WAIT goes high, the EPP stops pulling IOCHRDY
to low.
4. When IOCHRDY goes high it causes RD to go high if
WAIT is high during the host read cycle then the EPP
does not pull IOCHRDY to low.
5. When RD goes high, it causes the EPP to pull ASTRB
high.
Only when ASTRB is high can the EPP change PD0 – 7.
After ASTRB goes high, the EPP puts D0–7 in TRISTATE.
Note: A read operation is similar, except for the data direction, and the
activation of RD instead of WR.
EPP Zero Wait State (ZWS) Data Write/Read Operation
(both 1.7 and 1.9)
An EPP 1.7 and 1.9 Zero Wait State data write/read operation is similar to the EPP Zero Wait State address write/read
operation with the exception that the data strobe (DSTRB
signal), and a data register, replace the address strobe
(ASTRB signal) and the address register, respectively. See
Figure 8-3 .
TL/C/12379 – 43
FIGURE 8-2. EPP 1.7 Address Read
EPP 1.7 Data Write and Data Read
This procedure writes to the selected peripheral device or
register. See also Figure 8-3 .
An EPP 1.7 data write operation is similar to the EPP 1.7
address write operation, and an EPP 1.7 data read operation is similar to the EPP 1.7 address read operation, except
that the data strobe (DSTRB signal), and a data register,
replace the address strobe (ASTRB signal) and the address
register respectively.
TL/C/12379 – 44
FIGURE 8-3. EPP Write with ZWS
EPP 1.9 Address Write
The following procedure selects a peripheral or register.
See also Figure 8-4 .
1. The host writes a byte to the EPP address register.
2. The EPP pulls IOCHRDY low, and waits for WAIT to go
low.
3. When WAIT goes low the EPP pulls WRITE to low drives
the latched byte onto PD0 – 7.
If WAIT was already low, steps 2 and 3 occur concurrently.
4. The EPP pulls ASTRB low and waits for WAIT to go high.
EPP Zero Wait State (ZWS) Address Write/Read Operation (both 1.7 and 1.9)
The following procedure performs a short write to the selected peripheral device or register.
ZWS should be configured as follows: bit 5 of FCR is 1 and
bit 6 of FCR is 0.
1. The host writes a byte to the EPP address register. WR
goes low to latch D0–7 into the data register. The latch
drives the data register onto PD0–7.
2. The EPP first pulls WRITE low, and then pulls ASTRB
low to indicate that data has been sent.
3. If WAIT is high during the host write cycle, ZWS goes low
and IOCHRDY goes high.
4. When the host pulls WR high, the EPP pulls ASTRB,
ZWS and WRITE to high.
Only when WRlTE and ASTRB are high can the EPP
change PD0–7.
5. When WAIT goes high, the EPP stops pulling IOCHRDY
low, pulls ASTRB high, and waits for WAIT to go low.
6. Only if no EPP write is pending, when WAIT goes low, (or
when bit 7 of PTR is 1, and the direction is changed to
Backwards by setting bit 5 of CTR to 1), the EPP pulls
WRITE to high.
If an EPP write is pending WRITE remains low, and the
EPP may change PD0 – 7.
73
8.0 Parallel Port (Continued)
4. When RD goes high, the EPP puts D0 – 7 in TRI-STATE.
EPP 1.9 Data Write and (Backward) Data Read
This procedure writes to the selected peripheral drive or
register. See Figure 8-5 .
EPP 1.9 data read and write operations are similar to EPP
1.9 address read and write operations, respectively, except
that the data strobe (DSTRB signal) and a data register replace the address strobe (ASTRB signal) and the address
register.
Table 8-6 shows the standard 25-pin, D-type connector definition for various parallel port operations.
TL/C/12379–45
FIGURE 8-4. EPP 1.9 Address Write
EPP 1.9 Address Read
The following procedure reads from the address register.
See also Figure 8-5 .
1. The host reads a byte from the EPP address register.
When RD goes low, the EPP pulls IOCHRDY low, and
waits for WAIT to go low.
2. When WAIT goes low, the EPP pulls ASTRB low and
waits for WAIT to go high.
If wait was already low, steps 2 and 3 occur concurrently.
3. When WAIT goes high, the EPP stops pulling IOCHRDY
low, latches PD0–7, and pulls ASTRB high.
TL/C/12379 – 46
FIGURE 8-5. EPP 1.9 Address Read
TABLE 8-6. Parallel Port Pin Out
Connector
Pin No.
Chip
Pin No.
SPP, ECP
Mode
Pin
Direction
EPP Mode
Pin
Direction
1
137
STB
I/O
WRITE
I/O
2
136
PD0
I/O
PD0
I/O
3
135
PD1
I/O
PD1
I/O
4
134
PD2
I/O
PD2
I/O
5
133
PD3
I/O
PD3
I/O
6
131
PD4
I/O
PD4
I/O
7
130
PD5
I/O
PD5
I/O
8
129
PD6
I/O
PD6
I/O
9
128
PD7
I/O
PD7
I/O
10
127
ACK
I
ACK
I
11
126
BUSY
I
WAIT
I
12
125
PE
I
PE
I
13
124
SLCT
I
SLCT
I
14
119
AFD
I/O
DSTRB
I/O
15
120
ERR
I
ERR
I
16
122
INIT
I/O
INIT
I/O
17
123
SLIN
I/O
ASTRB
I/O
74
8.0 Parallel Port (Continued)
ward direction when bit 5 of DCR is 1). All DMA transfers are
to or from these registers. The ECP does not assert DMA
request for more than 32 consecutive DMA cycles. The ECP
stops requesting DMA when TC is detected during an ECP
DMA cycle.
Writing into a full FIFO, and reading from an empty FIFO,
are ignored. The written data is lost, and the read data is
undefined. The FIFO empty and full status bits are not affected by such access.
Some registers are not accessible in all modes of operation,
or may be accessed in one direction only. Accessing a non
accessible register has no effect: Data read is undefined,
data written is ignored, the FIFO does not update. The
PV87323VF Parallel Port registers (DRT, STR and CTR) are
not accessible when ECP is enabled.
To improve noise immunity in ECP cycles, the state machine does not examine the control handshake response
lines until the data has had time to switch.
IN ECP mode:
DATAR replaces DTR of SPP/EPP modes
DSR replaces SPR of SPP/EPP modes
DCR replaces CTR of SPP/EPP modes
A detailed description of the various modes follows in Sections 8.8 – 8.11.
8.6 EXTENDED CAPABILITIES PARALLEL PORT (ECP)
8.6.1 Introduction
The ECP support includes a 16-byte FIFO that can be configured for either direction, command/data FIFO tags (one
per byte), a FIFO threshold interrupt for both directions,
FIFO empty and full status bits, automatic generation of
strobes (by hardware) to fill or empty the FIFO, transfer of
commands and data, and a Run Length Encoding (RLE)
expanding (decompression) as explained below.
The Extended Capabilities Port (ECP) is enabled when bit 2
of PCR is 1. Once enabled, its mode is controlled via the
mode field of ECRÐbits 5,6,7 of ECR register.
The ECP has ten registers. See Table 8-7.
The AFIFO, CFIFO, DFIFO and TFIFO registers access the
same ECP FIFO. The FlFO is accessed at Base a 000h, or
Base a 400h, depending on the mode field of ECR and the
register.
FIFO can be accessed by host DMA cycles, as well as host
PIO cycles.
When DMA is configured and enabled (bit 3 of ECR is 1 and
bit 2 of ECR is 0) the ECP automatically (by hardware) issues DMA requests to fill the FIFO (in the forward direction
when bit 5 of DCR is 0) or to empty the FIFO (in the back-
TABLE 8-7. ECP Registers
A10
A1
A0
Offset
Address
Access
Size
Mode Ý
ECR (5 – 7)
Function
0
0
0
0
DATAR
R/W
Byte
000,001
Parallel Port Data Register
0
0
0
0
0
1
0
AFIFO
W
Byte
011
ECP Address FIFO
1
DSR
R
Byte
ALL
Status Register
0
1
1
0
0
2
DCR
R/W
Byte
ALL
Control Register
0
3
CFIFO
W
Byte
010
1
Parallel Port Data FIFO
0
0
3
DFIFO
R/W
Byte
011
ECP Data FIFO
1
0
0
3
TFIFO
R/W
Byte
110
Test FIFO
1
0
0
3
CNFGA
R
Byte
111
Configuration Register A
1
0
1
4
CNFGB
R
Byte
111
Configuration Register B
1
1
0
5
ECR
R/W
Byte
ALL
Extended Control Register
Register
The Base address is stored in bits A2–A9. It is 278h, 378h or 3BCh, as specified in the FAR register.
75
8.0 Parallel Port (Continued)
Reading this register has no effect and the data read is
undefined. Writes to this register during backward direction
(bit 5 of DCR is 1) have no effect and the data is ignored.
DSR: Read only. Same as the current STR register, except
for bit 2, which is reserved.
Writes to this register have no effect and the data is ignored.
8.6.2 Software Operation
Software operation is detailed in the document Extended
Capabilities Port Protocol and ISA Interface Standard. To
highlight the ECP usage some software operations are detailed below:
1. The software should enable ECP (bit 2 of PCR is 1) after
bits 0 – 4 of the Parallel Port Control Register (CTR) are
00100.
2. When ECP is enabled, and the software wishes to switch
modes, it should switch only through modes 000 or 001.
3. When ECP is enabled, the software should change direction only in mode 001.
4. The software should switch from mode 010, or 011 to
mode 000, or 001, only when the FIFO is empty.
5. The software should switch to mode 011 when bits 0 and
1 of DCR are 0.
6. The software should switch to mode 010 when bit 0 of
DCR is 0.
7. The software should disable ECP (bit 2 of PCR is 0) only
when in mode 000 or 001.
Software may switch from mode 011 backward direction to
modes 000 or 001 when there is an on-going ECP read
cycle. In this case the read cycle is aborted by deasserting
AFD. The FIFO is reset (empty) and a potential byte expansion (RLE) is automatically terminated since the new mode
is 000 or 001.
The ZWS signal is asserted by the ECP when ECP is enabled, and an ECP register is accessed by host PIO instructions, thus using a host zero wait cycle.
The ECP uses the X1/OSC clock. This clock can be frozen
(a power-down mode). When this power-down mode occurs, the DMA is disabled, all interrupts (except ACK) are
masked, and the FIFO registers are not accessible (access
is ignored). The other ECP registers are always accessible
when the ECP is enabled. During this period the FIFO status
and contents are not lost, although the host reads bit 2 of
ECR as 0, bit 1 of ECR as 1 and bit 0 of ECR as 1, regardless of the actual values of these bits. When the clock starts
toggling again these bits resume their original functions (values).
When the clock is frozen, an on-going ECP cycle may be
corrupted but next ECP cycle will not start. This is true even
if in forward direction the FIFO is not empty, and in backward direction the FIFO is not full. If the ECP clock starts or
stops toggling during a host cycle that accesses the FIFO,
the cycle may yield wrong data.
Note: The FDC has a register of the same name (DSR).
DCR: Same as the SPP CTR register, with the following
exceptions:
1. When bit 5 of the DCR is 0 the ECP is in forward
direction, and when bit 5 is high (1) the ECP is in
backward direction.
2. The ECP drives the PD0 – PD7 pins in the forward
direction but does not drive them in the backward
direction.
3. The direction bit, bit 5, is readable and writable.
4. When the control bit is read, the bit values are
provided by the internal data latch. These bit values are not superseded by the logic level of the
STB, AFD, INIT and SLIN pins.
5. Bit 4 of the DCR enables the ACK deassertion
interrupt event (1 e enable, 0 e mask). If a level
interrupt is configured (bit 4 of PCR is 1) clearing
this bit clears the ACK pending interrupt request.
This bit does not float the IRQ pin.
In mode 011, when bit 1 of DRC is 0, AFD is controlled by
ECP hardware. When bit 1 of DCR is 1, AFD is driven low.
In mode 011 or 010, when bit 0 of DCR is 0, STB is controlled by the ECP hardware. When bit 0 of DCR is 1, STB is
driven low.
CFIFO: Parallel Port FIFO Register. Write only.
A byte written, or DMAed, to this register is pushed into the
FIFO and tagged as data.
Reading this register has no effect and the data read is
undefined.
DFIFO: ECP Data FIFO Register.
In the forward direction (bit 5 of DCR is 0) a byte written, or
DMAed, to this register is pushed into the FIFO and tagged
as data.
Reading this register has no effect and the data read is
undefined.
In the backward direction (bit 5 of DCR is 1) the ECP automatically issues ECP read cycles to fill the FIFO. Reading
this register pops a byte from the FIFO.
Writing this register has no effect and the data written is
ignored.
TFIFO: Test FlFO Register.
A byte written into this register is pushed into the FIFO. A
byte read from this register is popped from the FIFO. The
ECP does not issue a ECP cycle to transfer the data to or
from the peripheral device.
The TFIFO is readable and writable in both directions. In the
forward direction (bit 5 of DCR is 0) PD0 – PD7 are driven,
but the data is undefined.
Note 1: The ECP outputs are inactive when the ECP is disabled.
Note 2: Only the FIFO/DMA/RLE are not functional when the clock is frozen. All other registers are accessible and functional. The FIFO/
DMA/RLE are affected by ECR modifications. i.e., they are reset
even when exits from modes 010/011 are carried out while the
clock is frozen.
8.7 REGISTER DEFINITIONS
DATAR: Same as DTR register, except that read always
returns the values of the PD0–PD7 pins (not the register
latched data).
AFIFO: ECP Address FIFO Register. Write Only. In the forward direction (bit 5 of DCR is 0) a byte written into this
register is pushed into the FIFO and tagged as command.
76
8.0 Parallel Port (Continued)
The FIFO does not stall when overwritten or underrun (access is ignored). Bytes are always read from the top of the
FIFO, regardless of the direction bit (bit 5 of DCR). For example if 44h, 33h, 22h, 11h is written into the FIFO, reading
the FIFO returns 44h, 33h, 22h, 11h (in the same order it
was written).
CNFGA: Configuration Register A. Read only.
Reading this register always returns 0001x100. Writing this
register has no effect and the data is ignored.
Bit 3 of CNFGA reflects the value of bit 5 of the ASC register.
CNFGB: Configuration Register B. Read only.
Reading this register returns the configured parallel port interrupt line, and its state, as follows.
Bit 7
This bit is always 0.
Bit 6
Holds the (non-inverted) value on the configured IRQ pin.
Bits 5, 4
These bits are 1 when IRQ5 is configured, and
0 when IRQ7 is configured.
Bit 3
This bit is always 1.
Bit 2
This bit is always 0.
Writing this register has no effect and the data
is ignored.
Bits 1, 0
These bits reflect the values of bit 2 and 1, respectively, of the SCF1 register.
ECR: Extended Control Register. This register controls the
ECP and parallel port functions. Upon reset this register is
initialized to 00010101.
IOCHRDY is driven low on ECR read when the ECR status
bits are not holding updated data.
Bits 7 – 5 (Mode) Bit 7 is the MSB of the three bits value.
000: Standard mode. Write cycles are performed under software control. STB, AFD,
INIT, and SLIN are open-drain outputs.
Bit 5 of DCR is ignored (assumes forward
direction) and PD0–PD7 are driven. The
FIFO is reset (empty).
001: PS/2 mode. Read and write cycles are
performed under software control. The
FIFO is reset (empty). STB, AFD, INIT,
and SLIN are open-drain outputs.
010: Parallel Port FIF0 mode. Write cycles are
performed under hardware control (STB is
controlled by hardware). Bit 5 of DCR is
ignored (assumes forward direction) and
PD0–PD7 are driven. STB, AFD, INIT, and
SLIN are open-drain output buffers when
bit 1 of PCR is 0. When bit 1 of PCR is 1,
the output buffers are push-pull.
011: ECP FIFO mode. The FIFO direction is
controlled by bit 5 of DCR.
Read and write cycles to the device are
performed under hardware control (STB
and AFD are controlled by hardware).
STB, AFD, INIT, and SLIN are push-pull
output buffers.
100: Reserved.
101: Reserved.
Bit 4
Bit 3
110: FIFO test mode. The FIFO is accessible
via the TFIFO register.
The ECP does not issue ECP cycles to fill/
empty the FIFO.
111: Configuration mode. The CNFGA and
CNFGB registers are accessible in this
mode.
ECP Interrupt Mask bit. When this bit is 0 an
interrupt is generated on ERR assertion (the
high-to-low edge of ERR). An interrupt is also
generated when ERR is asserted while this bit is
changed from 1 to 0; this prevents the loss of
an interrupt between ECR read and ECR write.
When this bit is 1, no interrupt is generated.
ECP DMA Enable bit. When this bit is 0, DMA is
disabled and the PDRQ pin is in TRI-STATE.
When this bit is 1, DMA is enabled and DMA
starts when bit 2 of ECR is 0.
Note: PDACK is assumed inactive when this bit is 0.
Bit 2
Bit 1
Bit 0
77
ECP Service bit. When this bit is 0, and one of
the following three interrupt events occur, an interrupt is generated and this bit is set to 1 by
hardware.
1. Bit 3 of ECR is 1, and terminal count is
reached during DMA.
2. Bit 3 of ECR is 0 and bit 5 of DCR is 0, and
there are eight or more bytes free in the
FIFO.
3. Bit 3 of ECR is 0 and bit 5 of DCR is 1, and
there are eight or more bytes to be read from
the FIFO.
When this bit is 1, DMA and the above three
interrupts are disabled.
Writing 1 to this bit does not cause an interrupt.
When the ECP clock is frozen this bit is read as
0, regardless of its actual value (even though
the bit may be modified by software when the
ECP clock is frozen).
FIFO Full bit. Read only.
This bit is 0 when the FIFO has at least one free
byte.
This bit is 1 when the FIFO is full.
This bit continuously reflects the FIFO state,
and therefore can only be read. Data written to
this bit is ignored.
When the ECP clock is frozen this bit is read as
1, regardless of the actual FIFO state.
FIFO Empty bit. Read only.
This bit is 0 when the FiFO has at least one byte
of data.
This bit is 1 when the FIFO is empty.
This bit continuously reflects the FIFO state,
and therefore can only be read. Data written to
this bit is ignored.
When the ECP clock is frozen this bit is read as
1, regardless of the actual FIFO state.
8.0 Parallel Port (Continued)
8.8 SOFTWARE CONTROLLED DATA TRANSFER
(Modes 000 and 001)
deasserts STB to terminate the write cycle. In 011 mode the
ECP waits for BUSY to be high before it deasserts STB.
Software controlled data transfer is supported in modes 000
and 001. The software generates peripheral-device cycles
by modifying the DATAR and DCR registers and reading the
DSR, DCR and DATAR registers. The negotiation phase
and nibble mode transfer, as defined in the IEEE 1284 standard, are performed in these modes.
In these modes the FIFO is reset (empty) and is not functional, the DMA and RLE are idle.
Mode 000 is for the forward direction only; the direction bit
is forced to 0 and PD0–7 are driven. Mode 001 is for both
the forward and backward directions. The direction bit controls whether PD0 –7 are driven.
When BUSY is high the ECP deasserts STB and changes
AFD and PD0 – 7 only after BUSY is low.
8.9 AUTOMATIC DATA TRANSFER (Modes 010 and 011)
Automatic data transfer (ECP cycles generated by hardware) is supported only in modes 010 and 011. Automatic
DMA access to fill or empty the FIFO is supported in modes
010, 011 and 110. Mode 010 is for the forward direction
only. The direction bit is forced to 0 and PD0–7 are driven.
Mode 011 is for both the forward and backward directions.
The direction bit controls whether PD0–7 are driven.
Automatic Run Length Expanding (RLE) is supported in the
backward direction.
8.9.3 Backward Direction (bit 5 of DCR is 1)
When the ECP is in the backward direction, and the FIFO is
not full (bit 1 of ECR is 0), the ECP issues a read cycle from
the peripheral device and monitors the BUSY signal. If
BUSY is high the byte is a data byte and it is pushed into the
FIFO. If BUSY is low the byte is a command byte. The ECP
checks bit 7 of the command byte, if it is high the byte is
ignored, if it is low the byte is tagged as an RLC byte (not
pushed into the FIFO but used as a Run Length Count to
expand the next byte read). Following an RLC read the ECP
issues a read cycle from the peripheral device to read the
data byte to be expanded. This byte is considered a data
byte, regardless of its BUSY state (even if it is low). This
byte is pushed into the FIFO (RLC a 1) times (i.e.,
RLC e 0: push the byte once, RLC e 127: push the byte
128 times).
When the ECP is in the backward direction, and the FIFO is
not empty (bit 0 of ECR is 0), the FIFO can be emptied by
software reads from the FIFO register (only DFIFO in mode
011, no AFIFO and CFIFO read).
When DMA is enabled (bit 3 of ECR is 1 and bit 2 of ECR is
0) the ECP automatically issues DMA requests to empty the
FIFO (only in mode 011).
TL/C/12379 – 47
FIGURE 8-6. ECP Forward Write Cycle
Note 1: FIFO-full condition is checked before every expanded byte push.
Note 2: A pending DMA request is removed, and a pending RLE expansion
is aborted, when you switch from modes 010 or 011 to other
modes.
Note 3: The two FIFO ports are neither synchronized nor linked together,
except via the empty and full FIF0 status bits. The FIFO shall not
delay the push and pop operations, even when they are performed
concurrently. Care must be taken not to corrupt PD0–PD7 or D0–7
while the other FIFO port is accessed.
Note 4: In the forward direction, the empty bit is updated when the ECP
cycle is completed, not right after the last byte is popped out of the
FIFO (valid cleared on cycle end).
Note 5: ZWS is not asserted for DMA cycles.
Note 6: The one-bit command/data tag is used only in forward direction.
8.9.1 Forward Direction (bit 5 of DCR e 0)
When the ECP is in forward direction and the FIFO is not full
(bit 1 of ECR is 0) the FIFO can be filled by software writes
to the FlFO registers (AFIFO and DFIFO in mode 011, and
CFIFO in mode 010).
When DMA is enabled (bit 3 of ECR is 1 and bit 2 of ECR is
0) the ECP automatically issues DMA requests to fill the
FIFO with normal data byte.
When the ECP is in forward direction and the FIFO is not
empty (bit 0 of ECR is 0) the ECP pops a byte from the FIFO
and issues write cycle to the peripheral device. The ECP
drives AFD according to the operation mode (ECR bits 5–7)
and according to the tag of the popped byte as follows: In
Parallel Port FIFO mode (mode 010) AFD is controlled by bit
1 of DCR. In ECP mode (mode 011) AFD is controlled by the
popped tag. AFD is driven high for normal data byte and
driven low for command byte.
8.9.4 ECP Backward Read Cycle
An ECP read cycle starts when the ECP drives AFD low.
The peripheral device drives BUSY high for a normal data
read cycle, or drives BUSY low for a command read cycle,
and drives the byte to be read onto PD0 – 7.
When ACK is asserted the ECP drives AFD high. When AFD
is high the peripheral device deasserts ACK. The ECP reads
the PD0 – 7 byte, then drives AFD low. When AFD is low the
peripheral device may change BUSY and PD0 – 7 states in
preparation for the next cycle.
8.9.2 ECP Forward Write Cycle
An ECP write cycle starts when the ECP drives the popped
tag onto AFD and the popped byte onto PD0–7. When
BUSY is low the ECP asserts STB. In 010 mode the ECP
TL/C/12379 – 48
FIGURE 8-7. ECP Backward Read Cycle
78
9.2 IDE SIGNALS
8.0 Parallel Port (Continued)
Using ’LS244 devices in the IDE interface provides buffering
of the control and address lines. Four control signals, IDEHI,
IDELO, HCS0, HCS1, one status signal, IOCS16, and one
data signal, IDED7, are required by the IDE interface. The
PC87306 provides all of these signals. They are summarized below.
IDEHI enables an ’LS245 octal bus transceiver for the upper
data lines (D15 – 8) during 16-bit read and write operations
at addresses 1F0 – 1F7. IDEHI will activate the ’LS245 only if
the IOCS16 output from the hard drive is active. IDELO enables another ’LS245 octal bus transceiver for the lower
data lines (D7 – 0) during all (1F0 – 1F7, 3F6 and 3F7) reads
and writes.
The IDED7 signal insures that the D7 data bus signal line is
disabled for address 3F7 (this bit is used for the Disk
Changed register on the floppy disk controller at that address).
The two ’LS245 chips are used to enable or TRI-STATE the
data bus signals. In the PC-AT mode the PC87306 provides
the two hard disk chip selects (HCS0, HCS1) for the IDE
interface.
The HCS0 output is active low when the 1F0 – 1F7h I/O
address space is chosen and corresponds to the 1FX signal
on the IDE header.
The HCS1 output is active low when the 3F6 or 3F7 I/O
addresses are chosen and corresponds to 3FX on the IDE
header. These are the two address blocks used in the
PC-AT hard disk controller.
Table 9-1 summarizes the addresses used by the PC-AT
hard disk controller.
8.10 FIFO TEST ACCESS (Mode 110)
Mode 110 is for testing the FIFO in PIO and DMA cycles.
Both read and write operations (pop and push) are supported, regardless of the direction bit.
In the forward direction PD0–PD7 are driven, but the data is
undefined. This mode can be used to measure the hostECP cycle throughput, usually with DMA cycles. This mode
can also be used to check the FIFO depth and its interrupt
threshold, usually with PIO cycles.
8.11 CONFIGURATION REGISTERS ACCESS (Mode 111)
The two configuration registers, CNFGA and CNFGB, are
accessible only in this mode.
8.12 INTERRUPT GENERATION
An interrupt pulse is generated when any of the following
events occur:
1. When bit 2 of ECR is 0, bit 3 of ECR is 1 and TC is
asserted during ECP DMA cycle.
2. When bit 2 of ECR is 0, bit 3 of ECR is 0, bit 5 of DCR is 0
and there are eight or more bytes free in the FIFO. It
includes the case when bit 2 of ECR is cleared to 0 and
there are already eight or more bytes free in the FIFO
(modes 010, 011 and 110 only).
3. When bit 2 of ECR is 0, bit 3 of ECR is 0, bit 5 of DCR is 1
and there are eight or more bytes to be read from the
FIFO. It includes the case when bit 2 of ECR is cleared to
0 and there are already eight or more bytes to be read
from the FIFO (modes 011 and 110 only).
4. When bit 4 of ECR is 0 and ERR is asserted (high to low
edge) or ERR is asserted when bit 4 of ECR is modified
from 1 to 0.
5. When bit 4 of DCR is 1 and ACK is deasserted (low-tohigh edge).
The interrupt is generated according to bits 5 and 6 of PCR.
TABLE 9-1. IDE Registers and Their ISA Addresses
Address
Note: Interrupt events Ý2, Ý3 and Ý4 are level events, thus they are
shaped as interrupt pulses. These interrupts are masked (inactive)
when the ECP clock is frozen. Interrupt event Ý1 is a pulse event.
The last interrupt event behaves as in the normal SPP mode: the IRQ
signal follows the ACK signal transition (when bit 5 of PCR is 0 and bit
6 of PCR is 0). Note that interrupt event Ý4 may be lost when the
ECP clock is frozen.
Read Function
Write Function
1F0
Data
Data
1F1
Error
Features
(Write Precomp)
1F2
Sector Count
Sector Count
1F3
Sector Number
Sector Number
1F4
Cylinder Low
Cylinder Low
9.0 Integrated Device Electronics
Interface (IDE)
1F5
Cylinder High
Cylinder High
1F6
Drive/Head
Drive/Head
9.1 INTRODUCTION
Another key interface for PC design is facilitated through the
use of the PC87306 IDE (Integrated Drive Electronics) Hard
Disk interface. Only three buffer chips are required to construct the IDE Hard Disk Interface circuit.
The IDE interface is essentially the PC-AT bus ported to the
hard drive. The hard disk controller resides on the hard drive
itself. So the IDE interface circuit must provide the PC-AT
bus signals, including data bits D15–0, address lines A3 – 0,
as well as the common control signals.
1F7
Status
Command
3F6
Alternate Status
Device Control
3F7
Drive Address
(Note)
Not Used.
Data Bus TRI-STATE
Note: Data bus bit D7 is dedicated to the floppy disk controller at this address. When reading this address the floppy disk controller disk
change status will be provided by bit D7. There is no write function at
this address in the IDE associated with this bit.
79
9.0 Integrated Device Electronics Interface (IDE) (Continued)
b) IDED7 is functional (i.e., read: IDED7 to D7, write D7 to
IDED7) when IDEACK is asserted and either RD or WR
is asserted.
c) HCS1,0 are not asserted on DMA cycles.
The equations show in Figure 9-1 define the signals of the
PC87306 IDE pins.
The IDE Interface Circuit has some additional IDE DMA support. When bit 1 of FCR is 1, the PC87306 IDE responds to
a DMA acknowledgement on the IDEACK input pin as follows:
a) IDEL0 is asserted when IDEACK is asserted and either
RD or WR is asserted.
Equations
HCS0 e A9*A8*A7*A6*A5*A4*A3* AEN
HCS1 e A9*A8*A7*A6*A5*A4*A3*A2*A1* AEN
IDELO e [HCS0*(RD a WR)] a ÀHCS1*[(WR*A0) a RD] Ó
IDEHI e IOCS16*HCS0*(RD a WR)
IDED7 (read) e (HCS0*RD) a [(HCS1* A0)*RD]
IDED7 (write) e WR*[HCS0 a (HCS1* A0)]
Comments
Active at 1F0 – 1F7
Active at 3F6, 3F7
Write 1F0 – 1F7, 3F6; Read 1F0 – 1F7, 3F6, 3F7
Read or Write 1F0 – 1F7 in AT Mode
Provides D7 during Read 1F0 – 1F7 and 3F6
Provides D7 during Write 1F0 – 1F7 and 3F6
FIGURE 9-1. IDE Interface Signal Equations (Non-DMA)
80
10.0 Keyboard Controller and Real-Time Clock
vices are available by special order. For applications which
require program development capabilities, the RAM-based
PC87323 SuperI/O Sidewinder is recommended.
The keyboard controller (KBC) is a general purpose 8-bit
microcontroller. It consists of 256 Bytes of data memory and
2 kBytes of Read-Only Memory (ROM), two 8-bit I/O ports,
a three register system interface, an 8-bit timer/counter,
and facilities for both binary and Binary Coded Decimal
(BCD) arithmetic. Figure 10-1 shows the relationships of
these functional blocks and Figure 10-2 displays the interface between the PC87306 and a host system.
The ROM may be custom programmed during manufacture
according to customer requirements. These versions of de-
The KBC is enabled when bit 0 of KRR is 1. It is guaranteed
to work with SYSCLK up to 16 MHz (when KRR7 e 1).
The KBC is software compatible with the 8042AH industry
standard keyboard controller as well as National’s
PC87911. The PC87306 can execute code previously written for an 8042 without further development.
TL/C/12379 – 49
FIGURE 10-1. Keyboard Controller Functional Block Diagram
81
10.0 Keyboard Controller and Real-Time Clock (Continued)
The STATUS register holds status information related to the
system interface. Figure 10-3 shows the bit definition. It is
read-only by the system.
Section 10.1 will describe in detail the operation of the functional blocks shown in Figure 10-1 .
The RTC supports a 100-year calendar as well as a time-ofday clock with alarm features and battery backup. Section
10.2 will describe the RTC in detail.
ST7
bit
10.1 PC87306 KBC FUNCTION
7
ST6
ST5
ST4
F1
F0
6
5
4
3
2
FIGURE 10-3. Status Register
10.1.1 Host System Interface
IBF
OBF
1
0
OBF . Output Buffer Full. A 1 indicates that data is
written into the DBBOUT register. It is cleared by a
system read operation.
Bit 1
IBF . Input Buffer Full. When a write operation is
performed by the host system, it will be set to 1.
Upon executing an IN A,DBB instruction, it will be
cleared.
Bit 2
F0 . A general purpose flag that can be cleared or
toggled by the keyboard controller software.
Bit 3
F1 . Command/Data Flag. This flag holds the
state of A2 when the host system performs a write
operation. It is typically used to distinguish between commands and data coming from the host
system. For example; when A2 e 1, F1 e 1 and
indicates a command was written by the host.
When A2 e 0, F1 e 0, indicating data was written
by the host.
Bits 4-7 ST4 – ST7 . General purpose flags. They can be
written by a MOV STS,A instruction.
Table 10-1 shows the register address decoding utilized by
the keyboard control system interface.
Bit 0
Common Signals
The keyboard controller is interfaced to the host system
through a common system interface. The interface consists
of the address bus A0–A15, Address Enable (AEN) signal,
data bus D0 – D7, and control signals I/O Read (IOR), and
I/O Write (IOW) (see Figure 10-2 ).
Address bus A0 –A15 connects to the system address
SA0 – SA15 of the system. The PC87306 uses the system
address and the AEN signal to decode the access to the
configuration register.
Data bus D0 – D7 connects to the peripheral bus XD0–XD7
of the system.
The IOR and IOW inputs connect to the IOR and IOW lines
of the system. All read and write operations to the PC87306
are I/O operations.
The PC87306 decodes the keyboard controller chip-select
from A0 – A15 (60h or 64h).
System Interface Registers
The keyboard controller consists of three 8-bit registers:
Data Byte Buffer Output (DBBOUT), Data Byte Buffer Input
(DBBIN), and STATUS. See Figure 10-1 .
The DBBOUT register is used to transfer data from the keyboard controller to the host system. It is written by the keyboard controller using the OUT DBB,A instruction. A data
read operation by the host system reads its content.
The DBBIN register is used to transfer data from the host
system to the keyboard controller. It is written by the host
system. It is read by the keyboard controller using an IN
A, DBB instruction.
TABLE 10-1. Summary of System Interface Operations
RD
WR
A2
A0 – 15*
0
1
0
0
Read DBBOUT
Operation
1
0
0
0
Write DBBIN, F1 Clear
0
1
1
0
Read STATUS
1
0
1
0
Write DBBIN, F1 Set
X
X
X
1
No Operation
*A0–A15 e 00000000011000XX.
TL/C/12379 – 50
FIGURE 10-2. Keyboard Controller to Host System Interface
82
10.0 Keyboard Controller and Real-Time Clock (Continued)
TL/C/12379 – 53
FIGURE 10-4. Fast IRQ Latching and Clearing
IRQ1 and IRQ2
When the KBC is enabled, the keyboard and mouse IRQ
lines (IRQ1 and IRQ12) are either identical to, or a function
of, the 8042’s P24 and P25; as detailed in Figure 10-4.
IRQ12 can be placed in TRI-STATE by setting the IRQ12
TRI-STATE control bit (bit 2 of SCF0) to 1. In this case
IRQ12 input is blocked to 1.
NOTE: EN FLAGS command (used for routing OBF and IBF onto P24 and
P25) will cause unpredictable results and should not be issued.
10.1.2 Program Memory
The keyboard controller of the PC87306 has a 2k x 8 ROM
based program memory. An 11-bit program counter allows
direct access to every location of the program memory. Figure 10-5 shows the memory map. There are three special
locations associated with hardware functions.
1. 000h After the keyboard controller is reset, the program
counter is initialized to 000h.
2. 003h When the input buffer of the host interface (DBBlN)
is full, and the IBF interrupt is enabled, the CPU
makes an interrupt call to this location.
3. 007h When the timer overflows and the timer interrupt is
enabled, the CPU makes an interrupt call to this
location.
10.1.3 Data Memory and Registers
The keyboard controller has 256 Bytes of data memory, including 2 banks of registers, 8 registers each, and an 8-level
stack. Figure 10-5 shows the data RAM organization.
TL/C/12379 – 51
FIGURE 10-5. Keyboard Controller Data Memory Map
83
10.0 Keyboard Controller and Real-Time Clock (Continued)
RAM locations 0h –7h are used as register bank0. They are
designated as R0–R7 respectively. Register bank1 (R0Ê –
R7Ê ) are located in 18h–1Fh of the address map. Bank0 is
the default register bank when the chip comes out from reset. Bank switching is accomplished by using ‘‘register bank
select’’ instructions (SEL RB0, SEL RB1). Locations 8h–
17h are reserved for the stack. Each stack entry consists of
2 bytes. Figure 10-6 shows the organization of the stack.
The stack pointer in the PSW register points to the top of
the stack. A 0 in the stack pointer corresponds to RAM
locations 8h and 9h.
Bit 5
F0. Flag 0. A general purpose software flag.
Bit 4
BS. The current active register bank.
0 e bank 0, 1 e bank 1.
Reserved. User should not change its power-up
value.
Bits 2-0 Stack Pointer. 3-bit Stack Pointer for 8-level stack.
When the CPU performs a subroutine call or interrupt call,
the PC and the upper 4 bits of the PSW are pushed into the
stack. Upon return, the PSW can be restored in option. If a
RETR Return instruction is executed, PSW is restored. PSW
is not restored if an RET Return instruction is executed. See
Figure 10-6 .
Bit 3
10.1.4 I/O Interface
The keyboard controller of the PC87306 provides 16 general purpose I/O lines, two open-collector output lines and
two input lines as shown in the Functional Block Diagram in
Figure 10-1 .
General Purpose I/O
The 16 general purpose I/O lines, P12 – P17 and P20 – P21,
are mapped to Port 1 and Port 2 respectively. These I/O
lines are quasi-bidirectional because the output buffer cannot be turned off even if the I/O line is intended for input.
When a 0 is written to an I/O line, it behaves like an output.
When a 1 is written to an I/O line, it behaves like an input.
On reset, all I/O lines are inputs.
Figure 10-8 illustrates the structure of the I/O line. Q1 and
Q2 are the normal output transistors. When the I/O line is
intended for output, 0 is written into the flip-flop, which latches, and Q2 turns on. When 1 is written, Q1 turns on briefly
because it is gated by a short port-write pulse also. Q1
charges up the pad to near VCC and then turns off. An active pull-up transistor Q3 turns on also, but it provides a
large pull-up resistance because it is a weak transistor. At
this stage, the I/O line can be used as input: a low impedance low voltage can override the pin and the input buffer
reads a low level input. If the pin is driven high or undriven, a
high level is read. Therefore, to use a port pin as input, a
logic 1 must first be written to it. When the keyboard controller is reset, all port lines will be initialized to logic 1.
Because Q1 turns on momentarily when a write to the port
is performed there is potential for a current surge. A series
resistor connected to those port lines used as inputs, is recommended to limit the potential surge (Figure 10-9) .
TL/C/12379–52
FIGURE 10-6. Keyboard Controller Stack Organization
Program Status Word Register (PSW)
This 8-bit register holds the program execution status. The
bit definition of the PSW register is shown in Figure 10-7 .
CY
bit
Bit 7
Bit 6
7
AC
F0
BS
res
6
5
4
3
FIGURE 10-7. PSW Register Bits
SP k2:0l
2-0
CY. Carry flag of the accumulator.
AC. Auxiliary Carry flag of the accumulator, i.e.,
carry from bit 3 to 4 of the ALU.
TL/C/12379 – 54
FIGURE 10-8. Active Pull-Up I/O Port Structure
84
10.0 Keyboard Controller and Real-Time Clock (Continued)
R: current limiting resistor
A small-value series current limiting
resistor is recommended when
PORT PINS are used as inputs.
TL/C/12379 – 55
FIGURE 10-9. Using Port Pins as Inputs
When the port line is used as an output, an active pull-up
technique is used (instead of a traditional pull-up resistor),
which turns on Q3 only when Q2 is off, hence eliminating a
steady current flow.
Timer Operation
The counter can be set to the timer operation mode by connecting its clock source to the internal timing generator. The
clock frequency to the timer is equal to the oscillator frequency divided by 480.
The initial value of the timer is programmable. After the timer is started (by STRT T instruction), it counts up continuously until it is stopped or the keyboard controller is reset.
The Timer Overflow Flag is set when the count value overflows from FFh back to 00h. The Timer Overflow Flag can
be tested by a conditional jump instruction (JTF). This instruction also resets the flag. When the timer interrupt is
enabled, an interrupt occurs when the timer overflows. This
is discussed more detail in the interrupt section.
Open-Collector Outputs
In order to reduce the glue logic used in a PC-AT compatible
environment, four dedicated open-collector outputs are provided: KBCLK, KBDAT, MCLK and MDAT. KBCLK is the
complement of P26. KBDAT is the complement of P27.
MCLK is the complement of P23. MDAT is the complement
of P22. These four drivers can drive 16 mA, making them
suitable for driving keyboard and mouse cables. TEST0 and
TEST1 are internally connected to KBCLK and KBDAT, respectively, in the PC-AT compatible applications. P10 and
P11 are connected internally to KBDAT and MDAT, respectively.
Event Counter Operation
When the clock input of the counter is switched to the external input (MCLK), it essentially becomes an event counter.
The falling edge of the signal on the MCLK pin causes the
counter to increment. Timer Overflow Flag and Timer interrupt operate in the same way as they do in the timer mode.
Test Inputs
KBCLK and MCLK are two dedicated input pins. Conditional
jump instructions directly check the level of these two pins.
MCLK also serves as the event counter input.
10.1.6 Interrupts
The keyboard controller of the PC87306 provides 2 different
internal interrupts. They are the Input Buffer Full (IBF) interrupt and Timer Overflow interrupt. These two interrupts can
be independently enabled or disabled by software. Both of
them are disabled when the chip comes out from reset.
10.1.5 Timer/Counter
The keyboard controller is equipped with an 8-bit counter
which can be used as a timer or an event counter.
Figure 10-10 shows the two different clock sources for the
counter. The clock source is selected by software.
TL/C/12379 – 56
FIGURE 10-10. Timing Generation and Timer Circuit
85
10.0 Keyboard Controller and Real-Time Clock (Continued)
Timer Interrupt
10.2 REAL-TIME CLOCK FUNCTION
If the timer interrupt is enabled, upon the timer overflow, an
interrupt occurs. It causes the program to perform a subroutine call to program address 007h. The interrupt is cleared
by this subroutine call. The current Program Counter (PC)
and the upper 4 bits of the PSW is pushed into the stack
before the call occurs. At the end of the timer interrupt service routine, an RETR instruction restores the PSW and the
PC. Because the timer interrupt has a lower priority than the
IBF interrupt, simultaneous IBF and timer interrupts cause
the timer interrupt to be pending. It is served as soon as the
program returns from the IBF interrupt service routine.
The RTC in the PC87306 is a low-power clock that provides
a time-of-day clock and 100-year calendar with alarm features and battery operation. Other features include three
maskable interrupt sources and 242 bytes of general purpose RAM. Valid RAM and time can be maintained through
the use of an external battery source. It is software compatible with the DS1287 and MC146818.
10.2.1 Memory Map
The RTC contains 14 time and control registers. It also contains 242 bytes of general purpose battery backed static
RAM in two banks. RAMSEL is used to select the active
bank. Refer to Table 10-2.
Input Buffer Full (IBF) Interrupt
If the lBF interrupt is enabled, when there is a host write
operation to the keyboard controller (IOW e 0), an interrupt
occurs. The processor saves the current Program Counter
and the upper 4 bits of the PSW into the stack and performs
a subroutine call to the program address 003h. Upon entering the interrupt service routine, further interrupts are held
off. The interrupt is re-enabled upon the execution of the
RETR instruction.
10.2.2 Bus Interface
The RTC function is mapped to I/O locations 70h (index)
and 71h (data). This decode is done internal to the
PC87306.
10.2.3 Time Generation
The Time Generation function divides the 32.768 kHz from
the external clock pins (X1C, X2C) down to a one Hertz
signal. The divider chain is controlled by bits 6 – 4 of Control
Register A. Bits 3 – 0 of Control Register A select one of
fifteen taps from the divider chain to be used as a Periodic
Interrupt. See Control Register A in the Control Register and
Interrupt section for divider configurations and rate selections.
During divider reset (bits 6 – 4 of Control Register A e 11x),
the divider chain is reset to 0. An update will occur 500 ms
after the divider chain is activated into normal operational
mode (bits 6 – 4 of Control Register A e 010). The periodic
flag also becomes active 1/2 of the programmed value
when the divider chain is activated.
10.1.7 Oscillator and Instruction Timing
The oscillator pin of the keyboard controller is X1, when bit
7 of KRR is 0. When bit 7 of KRR is 1, the Keyboard Controller clock is SYSCLK. Figures 10-11 shows the connections for external clock configuration via the X1 pin.
The oscillator clock is divided by 3 to generate the state
timing, then is further divided down by 5 to generate the
instruction timing (Figure 10-12) . Hence each instruction cycle consists of 5 states and 15 clock cycles.
Most of the keyboard controller instructions require only one
instruction cycle. The others require two cycles. Refer to the
instruction set for details.
Figure 10-13 represents the internal and external circuitry
that comprise the oscillator. The oscillator input may be driven from an external source. If this is desired, the input
should be driven rail to rail and be approximately a 50%
duty cycle. The oscillator output should be open in this case.
The external capacitor values should be chosen to provide
the manufacturer’s specified load capacitance for the crystal when combined with the parasitic capacitance of the
trace, socket, and package, which can vary from 0 pF to
8 pF. The rule of thumb in choosing these capacitors is:
CL e (C1 * C2)/(C1 a C2) a Cparasitic
C2 l C1
C1 can be trimmed to obtain the 32768.0 Hz.
TL/C/12379–57
FIGURE 10-11. External Clock Connection
TL/C/12379 – 58
FIGURE 10-12. Instruction Cycle Timing
86
10.0 Keyboard Controller and Real-Time Clock (Continued)
TABLE 10-2. RTC Memory Map
Index
(RAMSEL e 0)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E – 7F
(RAMSEL e 1)
00 – 7F
Function
BCD Format
Seconds
Seconds Alarm
Minutes
Minutes Alarm
Hours
Hours Alarm
Day of Week
Date of Month
Month
Year
Control Register A
Control Register B
Control Register C
Control Register D
Battery-Backed RAM
(114 Bytes)
00 – 59
00 – 59
00 – 59
00 – 59
12 hr. e
12 hr. e
24 hr. e
12 hr. e
12 hr. e
24 hr. e
01 – 07
01 – 31
01–12
00 – 99
01 – 12 (AM)
81 – 92 (PM)
00 –23
01 – 12 (AM)
81 – 92 (PM)
00 –23
Battery-Backed RAM
(128 Bytes)
Comments
00 – 3b
00 – 3b
00 – 3b
00 – 3b
01 – 0c (AM)
81 – 8c (PM)
00 –17
01 – 0c (AM)
81 – 8c (PM)
00 –17
01 – 07 (Sunday e 1)
01 – 1f
01 – 0c
00 – 63
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W (Bit 7 is Read Only)
R/W (Bit 3 is Read Only)
R
R
R/W
R/W
Daylight savings and leap year exceptions are handled by
the time keeping function. When bit 0 of Control Register A
(DSE) is a ‘‘1’’, time advances from 1:59:59 AM to 3:00:00
on the first Sunday in April. On the last Sunday of October
time changes from 1:59:59 to 1:00:00 when daylight savings
is enabled. On leap year February is extended to 29 days.
The time is updated once per second. If a read of the timing
registers coincides with an update, data read may not be
valid. Also, writes to time registers during an update have
undefined results.
To avoid accessing invalid data, the RTC in the PC87306
provides a user copy of the time registers. The sequence
used to update the time registers is shown in Figure 10-14.
Four methods are available for reading and writing time to
ensure that the correct time is written or read. They are as
follows:
Method 1ÐSet the SET bit. (CRB7)
Set the SET bit to 1. This takes a snapshot of the internal
time registers and loads it into the user copy. Then when
the SET bit is written with 0, the user copy will update the
internal registers.
Method 2ÐAccess after detection of an Update Ended
Interrupt.
This interrupt indicates that an update has just completed
and the next update will occur after 999 ms.
Method 3ÐPoll update-in-progress (bit 7 in Control Register A).
Rext e 5 kX
15 pF
C1 e 12
C2 e 15 pF
8 pF
Cparasitic e 0
x
x
TL/C/12379–96
FIGURE 10-13. Oscillator Internal and External Circuitry
The start-up time of this oscillator may vary from two to
seven seconds and is due to the high ‘‘Q’’ of the crystal.
The parameters below describe the crystal to be used:
Parallel Resonant, tuning fork (N cut) or XY Bar
Q l 35k
Load Capacitance (CL)
Accuracy
Temperature Coefficient
Binary Format
9 pF to 13 pF
User Choice
User Choice
10.2.4 Time Keeping
The time is kept in BCD or binary format. The format is
determined by bit 2 of Control Register B (DM). Either 12 or
24 hour representation for the hours can be maintained as
determined by bit 1 of Control Register B (24/12). Note that
when changing the format the time registers must be re-initialized to the corresponding data format.
87
10.0 Keyboard Controller and Real-Time Clock (Continued)
TL/C/12379 – 59
where:
UIP e Update In Progress Bit
UF e Update Ended Flag (Update Ended Interrupt if Enabled)
PF e Periodic Flag (Periodic Interrupt if Enabled)
AF e Alarm Flag (Alarm Interrupt if Enabled)
Flags (and IRQ) are reset at the conclusion of Control Register C read or by RESETC low.
A
B
C
P
Update in Progress Bit High before Update Occurs e 244 ms
Periodic interrupt to Update e P/2 a 244 ms
e Update to Alarm Interrupt e 30.5 ms
e Period is programmed by RS3–0 of control Register A.
e
e
FIGURE 10-14. Interrupt/Status Timing
The update occurs 244 ms after the update-in-progress
bit goes high. Therefore if a 0 is read, there is a minimum
of 244 ms in which the time is guaranteed to remain stable.
Method 4ÐUse a Periodic interrupt to determine if an
update cycle is in progress.
The periodic interrupt is first set to a desired period. The
program can then use the periodic interrupt to signify that
there is (Periodic Interrupt/2 a 244 ms) remaining until
another update occurs.
The Alarm condition is also generated by the Time Keeping
function. After each update, the seconds, minutes, and
hours are compared with the seconds alarm, minutes alarm,
and hours alarm. If equal, the Alarm lag is set in Control
Register C. This causes an interrupt condition (IRQZ e 0) if
the Alarm Interrupt Enable bit is set in Control Register B. If
both bit 7 and bit 6 of any alarm byte (seconds alarm, minutes alarm, hours alarm) are 1, then that alarm byte is a
‘‘don’t care’’.
10.2.6 Power Management
The Power Management function provides power to the
RTC in the PC87306. During system operation, power from
the system is used. When system voltage falls below battery
voltage, the Power Management function switches the RTC
cell to battery power. For proper operation, a 500 mV differential is needed between VCC and VBAT. Figure 10-15 represents a typical battery configuration and Figure 10-16 represents typical battery current during battery backed mode.
TL/C/12379 – 60
FIGURE 10-15. Typical Battery Configuration
10.2.5 RAM
The RAM data is accessed at locations 0E–7F when
RAMSEL (bit 2) of the configuration registers is 0, and locations 00 – 7F when RAMSEL is 1. Battery backed power enables the RAM to retain information during system powerdown.
Bit 0 of SCF0 locks RTC RAM cells at addresses 38-3Fh.
The bit is 0 upon reset, thus enabling read and write access.
When the bit is 1, writes to RTC RAM cells at addresses
38 – 3Fh are ignored, and reads return FFh. Once set to 1
the bit can only be cleared by a hardware reset.
TL/C/12379 – 61
FIGURE 10-16. Typical Battery Current
during Battery Backed Mode
88
10.0 Keyboard Controller and Real-Time Clock (Continued)
Bits 0 – 3 RS3 – 0ÐPeriodic Interrupt Rate Select
(Read/Write)
10.2.7 System Bus Lock Out and Power-Up Detection
As the RTC switches to battery power all inputs are locked
out so that the internal registers can not be modified. This
lockout condition continues for 62 ms (min) to 125 ms (max)
after the RTC switches from battery power to system power.
The 62 ms–125 ms lockout during power transition from
battery to system power depends on the following conditions:
1. If the Divider Chain Control (bits 6–4 in Control Register
A) is in any mode but Normal Operation (010), all inputs
are enabled immediately upon detection of system voltage above that of battery voltage.
2. When Battery voltage is below 1V and MR is 1, all inputs
are enabled immediately upon detection of system voltage above that of battery voltage. This also initializes
registers 00 through 0D to 00.
3. If the VRT bit (bit 7 in Control Register D) is 0, all inputs
are enabled immediately upon detection of system voltage above that of battery voltage.
These bits control the rate of the periodic interrupt. Reset has no effect on these bits.
RS3 –0
0000
10.2.8 Oscillator
When power is applied to the RTC in the PC87306, the
Oscillator is operational with the following exceptions:
1. The VRT bit (bit 7 in Control Register D) is a 0. The
oscillator is disabled after initial power-up. This reduces
power consumption during the time between when the
battery is initially installed and when the RTC is initialized
for timekeeping.
2. The Divider Chain Control (bits 6–4 in Control Register
A) is in Oscillator Disabled modes (000 and 001). This
provides a means for the user to ‘‘shut-down’’ the oscillator and reduce the power consumption of the RTC cell.
The RAM remains functional when the oscillator is disabled.
Bit 7
Control Register A
DV2
DV1
DV0
RS3
RS2
RS1
RS0
7
6
5
4
3
2
1
0
3.90625
ms
0010
7.8125
ms
0011
122.070
ms
0100
244.141
ms
0101
488.281
ms
0110
976.562
ms
0111
1.953125
ms
1000
3.90625
ms
1001
7.8125
ms
1010
15.625
ms
1011
31.25
ms
1100
62.5
ms
1101
125
ms
1110
250
ms
1111
500
ms
DV2 –0
10.2.10 Control Registers
The four Control Registers used to configure timing interrupts can be accessed at any time during non-battery
backed operation. These Control Registers are located at
addresses 0Ah, 0Bh, 0Ch and 0Dh. Their descriptions follow.
UIP
None
0001
Bits 4 – 6 DV2 – 0ÐDivider Chain Control
(Read/Write)
These bits control the configuration of the divider
chain in the Timing Generation function.
Reset has no effect on these bits.
10.2.9 Interrupt Handling
The Periodic, Alarm, and Update ended Interrupts are generated (IRQZ is driven low) when the respective enable bits
in Control Register B are set and an interrupt condition occurs. A read from Register C clears the active interrupt. If a
second interrupt condition occurs (other than that which
caused the interrupt) during a read from Register C, IRQZ
remains active (low). Thus, it is recommended that when
multiple interrupts are enabled, the interrupt service routine
continues to read (and service interrupts) until bit 7 of Control Register C (IRQ Flag) returns to a 1. Note that if an
interrupt is not serviced before a second condition of the
same interrupt occurs, the second interrupt event is lost.
bit
Periodic
Interrupt Rate
89
Divider Chain
Configuration
000
Oscillator Disabled
001
Oscillator Disabled
010
Normal Operation
011
TEST
100
TEST
101
TEST
110
Divider Chain RESET
111
Divider Chain RESET
UIPÐUpdate in Progress
(Read Only)
1: Signifies that the timing registers will be updated within 244 ms.
0: Signifies that an update will not occur before
244 ms. This bit reads 0 when bit 7 of Control
Register B (SET) is a 1.
Reset has no effect on this bit.
10.0 Keyboard Controller and Real-Time Clock (Continued)
0: Disables generation of the Periodic interrupt.
Control Register B
bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
SET
PIE
AIE
UIE
0
DM
24/12
DSE
7
6
5
4
3
2
1
0
Reset forces this bit to 0.
Note: It is recommended that the software clears bits 4–6 of
Control Register B, and reads Control Register C, after
reset.
DSEÐDaylight Savings Enable
(Read/Write)
1: Enables daylight savings. Two conditions apply as follows:
Daylight Savings Spring: Time advances from
1:59:59 to 3:00:00 on the first Sunday in April.
Daylight Savings Fall: Time advances from
1:59:59 to 1:00:00 on the last Sunday in October.
0: Disables the daylight savings feature.
Reset has no effect on this bit.
24/12Ð24 or 12 Hour Mode
(Read/Write)
1: Enables 24 hour format.
0: Enables 12 hour format.
Reset has no effect on this bit.
DMÐData Mode
(Read/Write)
1: Enables BINARY format.
0: Enables BCD format.
Reset has no effect on this bit.
This bit is defined as ‘‘Square Wave Enable’’ by
the MC146818 and is not supported by the RTC
Cell. This bit is always read as 0.
UIEÐUpdate Ended Interrupt Enable
(Read/Write)
1: Enables generation of the Update Ended interrupt. This interrupt is generated at the time
an update occurs.
0: Disables generation of the Update Ended interrupt.
Reset forces this bit to 0.
Bit 7
SETÐSet mode
(Read/Write)
1: The user copy of time is ‘‘frozen’’ allowing the
time registers to be accessed without regard
for an occurrence of an update.
0: The timing updates occur normally.
Reset has no effect on this bit.
Control Register C
IRQF
Note: It is recommended that the software clears bits 4–6 of
Control Register B, and reads Control Register C, after
reset.
Bit 5
AIEÐAlarm Interrupt Enable
(Read/Write)
1: Enables generation of the Alarm interrupt. The
Alarm interrupt is generated immediately after
a time update in which the Seconds, Minutes,
and Hours time matches with their respective
alarm counterparts.
0: Disables generation of the alarm interrupt.
Reset forces this bit to 0.
AF
UF
0
0
0
0
VRT
0
0
0
0
0
0
0
bit
7
6
5
4
3
2
1
0
Bits 0 – 6 Reserved
(Always 0)
Bit 7
VRTÐValid RAM and Time
(Read Only)
1: This bit indicates that the contents of the RTC
are valid.
0: This bit indicates that the battery source is low
and that the RTC data and RAM data are
questionable. This bit is set to 1 at the conclusion of a read from this register.
Note: It is recommended that the software clears bits 4–6 of
Control Register B, and reads Control Register C, after
reset.
Bit 6
PF
bit
7
6
5
4
3
2
1
0
Bits 0 – 3 Reserved
(Always 0)
Bit 4
UFÐUpdate Ended Interrupt Flag
(Read Only)
1: When the time registers are updated. This bit
is reset to 0 at the conclusion of a read from
this register. Reset forces this bit to 0.
Bit 5
AFÐAlarm Interrupt Flag
(Read Only)
1: When an alarm condition is detected. This bit
is reset to 0 at the conclusion of a read from
this register. Reset forces this bit to 0.
Bit 6
PFÐPeriodic Interrupt Flag
(Read Only)
1: When a transition occurs on the selected tap
of the divider chain. This bit is reset to 0 at
the conclusion of a read from this register.
Reset forces this bit to 0.
Bit 7
IRQFÐInterrupt Request Flag
(Read Only)
1: When bit pairs PIE and PF; AIE and AF, and
UIE and UF all equal 1. The IRQF bit mirrors
the value on the IRQZ output. When lRQZ is
active (low), IRQF is 1. Reset forces this bit to
0.
Control Register D
PIEÐPeriodic Interrupt Enable
(Read/Write)
1: Enables generation of the Periodic interrupt.
Bits 3–0 of Control Register A determine the
rate of the Periodic interrupt.
90
11.0 General Purpose Input and Output (GPIO) Ports
The GPIO ports have open-drain outputs with internal pullups and TTL inputs. The GPIO behave as follows:
1. Writes are latched internally. A latched 0 drives the pin
low; a latched 1 pulls the pin high via the internal pullup.
2. Reads return the pins’ values. A driven-low pin is always
read as 0. A pulled-up pin is read as either 0 or 1, according to the pin voltage as dictated by the pullup or external
active driver (TTL input buffers are used).
Upon reset the write latches are initialized to FFh.
A GPIO port must not be enabled at the same address as
another accessible PC87306 register. Undefined results will
occur if a GPIO is configured in this way.
The PC87306 supports two identical General Purpose I/O
(GPIO) ports. See Figure 11-1.
The PC87306 can wake up with both GPIO Ports either enabled or disabled, according to the CFG1 strap pin. GPIO
Port 1 is at offset 0 and GPIO Port 2 is at offset 1 from the
16-bit GPIO Port base address. The GPIO port’s base address is software configurable. GPBA is an 8-bit configuration register that holds address bit A2-9 (bit 0 holds A2). The
other eight bits of the 16-bit GPIO port base address are 0.
Upon reset GPBA is initialized to 00011110, thus dictating
base address e 78h).
TL/C/12379 – 65
FIGURE 11-1. General Purpose I/O (GPIO) Ports
91
12.0 Electrical Characteristics
ABSOLUTE MAXIMUM RATINGS (Notes 1 and 2)
RECOMMENDED OPERATING CONDITIONS
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
b 0.5V to a 7.0V
Supply Voltage (VDD)
Supply Voltage (VDD)
Input Voltage (VI)
Output Voltage (VO)
Storage Temperature (TSTG)
Power Dissipation (PD)
Lead Temperature (TL)
(Soldering, 10 seconds)
4.5V to 5.5V
0§ C to a 70§ C
1500V
Operating Temp. Range (TA)
ESD Tolerance
CZAP e 100 pF (Note 3)
RZAP e 1.5 kX (Note 3)
b 0.5V to VDD a 0.5V
b 0.5V to VDD a 0.5V
Note 3: Value based on test complying with NSC SOP5-028 human body
model ESD testing using the ETS-910 tester.
b 65§ C to a 165§ C
1W
a 260§ C
Note 1: Absolute Maximum Ratings are those values beyond which damage
to the device may occur.
Note 2: Unless otherwise specified, all voltages are referenced to ground.
CAPACITANCE TA e 25§ C, f e 1 MHz
Symbol
Parameter
Min
Typ
Max
Units
CIN
Input Pin Capacitance
5
7
pF
CIN1
Clock Input Capacitance
8
10
pF
CIO
I/O Pin Capacitance
10
12
pF
CO
Output Pin Capacitance
6
8
pF
12.1 DC ELECTRICAL CHARACTERISTICS Under Recommended Operating Conditions
Symbol
Max
Units
Input High Voltage
2.0
VDD
V
VIL
Input Low Voltage
b 0.5
0.8
mA
ICC
VDD Average Supply Current
VIH
ICCSB
IIL
Parameter
VDD Quiescent Supply
Current in Low Power Mode
Input Leakage Current
(Note 4)
Conditions
Min
Typ
VIL e 0.5V
VIH e 2.4V
No Load
32
50
mA
VIL e VSS
VIH e VDD
No Load
1.3
1.7
mA
VIN e VDD
10
mA
VIN e VSS
b 10
mA
Note 4: During reset the MFM pin is rated for 10 mA; b 150 mA leakage is due to an internal pull-up resistor. The RTS1, 2; SOUT1, 2; DTR1, 2; HCS0, 1; IDEHI;
VLD0, 1 and IDEHLO are rated for 100 mA; b 10 mA leakage is due to internal pull-down resistors. During normal operation the BUSY, PE, and SLCT pins are rated
for 100 mA; b 10 mA leakage is due to internal pull down resistors. The ACK and ERR pins are rated for 10 mA; b 100 mA leakage is due to internal pull-up resistors.
92
12.0 Electrical Characteristics (Continued)
12.1 DC ELECTRICAL CHARACTERISTICS (Continued)
12.1.1 Microprocessor, Parallel Port, and IDE Interface Pins
Symbol
VOH
VOL
IOZ
Parameter
Output High Voltage
Output Low Voltage
Conditions
Min
IOH e b15 mA on:
D0 – 7, IDED7, IRQ3 – 7, DRQ
IOH e b6 mA on:
DTR, RTS, SOUT, MFM,
DRATE, CSOUT, IDEHI,
IDELO, HCS0, HCS1, CS0, CS1
2.4
Max
V
IOL e 24 mA on:
D0 – 7, IDED7, IRQ3 – 7, IRQ8,
DRQ, ZWS, IOCHRDY
IOL e 12 mA on:
DTR, RTS, SOUT, HCS,
IDEHI, IDELO
IOL e 6 mA on:
DRATE, CS0, CS1
Output TRI-STATE Leakage
Current (D7–0, IRQ3–7, DRQ)
Units
0.4
V
VIN e VDD
50
mA
VIN e VSS
b 50
mA
Note 1: Pins IOCHRDY and ZWS are open drain pins.
12.1.2 Disk Interface Pins
Symbol
Parameter
Conditions
Min
Typ
Max
250
Units
VH
Input Hysteresis
VOH
Output High Voltage (Note 1)
IOH e b4 mA
mV
VOL
Output Low Voltage
IOL e 40 mA
0.4
V
ILKG
Output High Leakage Current
(Note 1)
VIN e VDD
10
mA
VIN e VSS
b 10
mA
2.4
V
Note 1: VOH and ILKG for the disk interface pins are valid for CMOS buffered outputs only.
12.1.3 Oscillator Pin (X1)
Symbol
Parameter
VIH
X1 Input High Voltage
IXLKG
X1 Leakage
Conditions
Min
Typ
Max
2.0
Units
V
VIN e VDD
400
mA
VIN e VSS
b 400
mA
12.1.4 Parallel Port Pins
Parameter
Conditions
IOH
Symbol
High Level Output Current (Note 1)
VOH e 2.4V
Min
Typ
12
Max
Units
mA
IOL
Low Level Output Current
VOL e 0.4V
12
mA
Note 1: AFD, INIT, SLIN and STB are open drain pins when the PC87306 parallel port is operating in one of the following modes: Compatible, Extended, EPP1.7,
ECP mode 0 or 1, or ECP mode 2 if PCR1 e 0. 4.7 kX resistors should be used.
12.1.5 GPIO Pins
Symbol
VOL
Parameter
Conditions
Output Low Voltage (Note 1)
IOL e 2.0 mA
Note 1: GPIO pins are open drain outputs, with internal pull-up resistors between 10 and 26 kX.
93
Min
Typ
Max
Units
0.4
V
12.0 Electrical Characteristics (Continued)
12.1.6 Keyboard Controller and Real-Time Clock Pins 0§ C –70§ C
Symbol
VOH
VOL
IIN
Parameter
Conditions
Minimum High Level Output Voltage
# P10–P17, P20–P27 (Note 1)
# All other push-pull outputs, KBCLK, KBDAT,
MCLK, MDAT (Note 2)
VIN e VIH or VIL
# IOH e b2.0 mA
# IOH e b4.0 mA
Maximum Low Level Output Voltage
# P10–P17, P20–P27
# KBDAT, KBCLK, MCLK, MDAT
# All Other Outputs
VIN e VIH or VIL
# IOL e 2.0 mA
# IOL e 16.0 mA
# IOL e 4.0 mA
Maximum Input Current
# Inputs only: A0–A9, AEN, CS, EA, IOR, IOW,
PWRGOOD, T0, T1
# Inputs with Resistors: SS, TRI
STROBE
IBAT
VBAT Quiescent Supply Current
2.4
2.4
Units
V
V
V
V
V
# VIN e VCC or VSS
10
mA
# VIN e VCC
10
400
10
10
400
mA
mA
mA
mA
mA
8
mA
0.4
mA
VCC b 0.5
V
e
e
e
e
VIL
VCC or VSS
VCC
VIL
VBAT e 3.0V
VIN e VCC e VSS e 0V
Real-Time Clock
f e 32.768 kHz
Input Leakage
VBAT
Max
0.4
0.4
0.4
VIN
# VIN
# VIN
VIN
# I/Os Only: D0–D7
# I/Os with Resistors: P10–P17, P20–P27, SYNC,
Min
VCC e 5.0V, VBAT e 3.0V
Battery Voltage
2.4
Note 1: IOH is driven for 10 ns on switch from low to high.
Note 2: KBCLK, KBDAT, MCLK and MDAT are open drain outputs with 10k minimum pull-up resistors.
12.2 AC ELECTRICAL CHARACTERISTICS
12.2.1 AC Test Conditions TA e 0§ C to a 70§ C, VDD e 5.0V g 10%
LOAD CIRCUIT (Notes 1, 2, 3)
AC TESTING INPUT, OUTPUT WAVEFORM
TL/C/12379 – 67
TL/C/12379–66
Note 1: CL e 100 pF, includes jig and scope capacitance.
Note 2: S1 e Open for push-pull outputs. S1 e VDD for high impedance to active low and active low to high impedance measurements. S1 e GND for high
impedance to active high and active high to high impedance measurements. RL e 1.0 kX for mP interface pins.
Note 3: For the FDC Open Drive Interface Pins S1 e VDD and RL e 150X.
94
12.0 Electrical Characteristics (Continued)
12.2.2 Clock Timing
Parameter
Min
tCH
Symbol
Clock High Pulse Width
16
Max
Units
tCL
Clock Low Pulse Width
16
tCP
Clock Period
40
tICP
Internal Clock Period
(Table 12-1)
ns
tDRP
Data Rate Period
(Table 12-1)
ns
ns
ns
43
ns
TABLE 12-1 Nominal tICP, tDRP Values
MFM Data Rate
tDRP
tICP
Value
Units
1 Mbps
1000
3 x tCP
125
ns
500 kbps
2000
3 x tCP
125
ns
300 kbps
3333
5 x tCP
208
ns
250 kbps
4000
6 x tCP
250
ns
TL/C/12379 – 68
FIGURE 12-1. Clock Timing
12.2.3 Microprocessor Interface Timing
Symbol
Parameter
Min
Max
Units
tAR
Valid Address to Read Active
18
tAW
Valid Address to Write Active
18
ns
tDH
Data Hold
0
ns
tDS
Data Setup
18
ns
tHZ
Read to Floating Data Bus
13
tPS
Port Setup
10
ns
tRA
Address Hold from Inactive Read
0
ns
tRCU
Read Cycle Update
45
ns
tRD
Read Strobe Width
60
ns
tRDH
Read Data Hold
10
tRI
Read Strobe to Clear IRQ6
55
ns
tRVD
Active Read to Valid Data
55
ns
tWA
Address Hold from Inactive Write
0
ns
tWCU
Write Cycle Update
45
ns
tWI
Write Strobe to Clear IRQ6
55
ns
tWO
Write Data to Port Update
60
ns
tWR
Write Strobe Width
60
ns
RC
Read Cycle e tAR a tRD a tRCU
123
ns
WC
Write Cycle e tAW a tWR a tWCU
123
ns
tWRR
RD Low after WR High
80
ns
95
ns
25
ns
ns
12.0 Electrical Characteristics (Continued)
TL/C/12379 – 69
FIGURE 12-2. Microprocessor Read Timing
TL/C/12379 – 70
FIGURE 12-3. Microprocessor Write Timing
TL/C/12379 – 72
FIGURE 12-4. Read after Write Operation to All Registers and RAM Timing
96
12.0 Electrical Characteristics (Continued)
12.2.4 Baud Out Timing
Symbol
Parameter
Conditions
N
Baud Divisor
tBHD
Baud Output Positive Edge Delay
tBLD
Baud Output Negative Edge Delay
Min
Max
Units
1
65535
ns
CLK e 24 MHz/2, 100 pF Load
56
ns
CLK e 24 MHz/2, 100 pF Load
56
ns
TL/C/12379 – 73
FIGURE 12-5. Baud Out Timing
12.2.5 Transmitter Timing
Symbol
Parameter
Min
Max
Units
1.6 ms
*/16
BAUD OUT Cycles
40
ns
tIRTXW
IRTX Pulse Width
tHR
Delay from WR (WR THR) to Reset IRQ
tIR
Delay from RD (RD IIR) to Reset IRQ (THRE)
55
ns
tIRS
Delay from Initial IRQ Reset to Transmit Start
8
24
Baud Out Cycles
tSI
Delay from Initial Write to IRQ
16
24
Baud Out Cycles
tSTI
Delay from Start Bit to IRQ (THRE)
8
Baud Out Cycles
TL/C/12379 – 74
Note 1: See Microprocessor Write cycle timing, Figure 12-3 .
Note 2: See Microprocessor Read cycle timing, Figure 12-2 .
FIGURE 12-6. Transmitter Timing
97
12.0 Electrical Characteristics (Continued)
12.2.6 Receiver Timing
Symbol
Parameter
Min
Max
Units
1.6 ms
6/16
BAUD OUT Cycles
Delay from Active Edge of RD to Reset IRQ
78
ns
Delay from Inactive Edge of RD (RD LSR) to Reset IRQ
55
ns
tIRRXW
IRRX Pulse Width
tRAI
tRINT
tSCD
Delay from RCLK to Sample Time
tSINT
Delay from Stop Bit to Set Interrupt
Conditions
(Note 1)
41
ns
2
Baud Out
Cycles
Note 1: This is an internal timing specification and is therefore not tested.
TL/C/12379 – 75
FIGURE 12-7. Receiver Timing
TL/C/12379 – 76
Note 1: If SCR0 e 1, then tSINT e 3 RCLKs. For a Timeout Interrupt, tSINT e 8 RCLKs.
FIGURE 12-8. FIFO Mode Receiver Timing
98
12.0 Electrical Characteristics (Continued)
TL/C/12379 – 77
Note 1: If SCR0 e 1, then tSINT e 3 RCLKs. For a Timeout Interrupt, tSINT e 8 RCLKs.
FIGURE 12-9. Timeout Receiver Timing
12.2.7 MODEM Control Timing
Max
Units
tMDO
Symbol
Delay from WR (WR MCR) to Output
Parameter
Conditions
Min
40
ns
tRIM
Delay to Reset IRQ from RD (RD MSR)
78
ns
tSIM
Delay to Set IRQ from MODEM Input
40
ns
TL/C/12379 – 78
Note 1: See Microprocessor Write cycle timing, Figure 12-3 .
Note 2: See Microprocessor Read cycle timing, Figure 12-2 .
FIGURE 12-10. MODEM Control Timing
99
12.0 Electrical Characteristics (Continued)
12.2.8 DMA Timing
12.2.8.1 FDC
Symbol
Parameter
Min
tKI
FDACK Inactive Pulse Width
25
tKK
FDACK Active Pulse Width
65
tKQ
FDACK Active Edge to FDRQ Inactive
tQK
FDRQ to FDACK Active Edge
tQP
FDRQ Period (except Non-Burst DMA) (Note 3)
tQQ
FDRQ Inactive Non-Burst Pulse Width
300
tQR
FDRQ to RD or WR Active
15
tQW
FDRQ to End of RD, WR (Notes 2, 3)
(FDRQ Service Time)
tQT
FDRQ to TC Active (Notes 2, 3)
(FDRQ Service Time)
tRQ
RD, WR Active Edge to FDRQ Inactive
(Note 1)
tTQ
TC Active Edge to FDRQ Inactive
tTT
TC Active Pulse Width
Max
ns
ns
65
10
ns
ns
8 x tDRP
50
Units
ms
400
ns
ns
(8 x tDRP) b(16 x tICP)
ms
(8 x tDRP) b(16 x tICP)
ms
65
ns
75
ns
ns
Note 1: The active edge of RD or WR and TC is recognized only when FDACK is active.
Note 2: Values shown are with the FIFO disabled, or with FIFO enabled and THRESH e 0. For nonzero values of THRESH, add (THRESH x 8 x tDRP) to the values
shown.
Note 3: tDRP and tICP are defined in Table 12-1.
TL/C/12379 – 79
FIGURE 12-11. FDC DMA Timing
100
12.0 Electrical Characteristics (Continued)
12.2.8.2 ECP
Symbol
Parameter
Min
Max
Units
tKIP
PDACK Inactive Pulse Width
25
ns
tKKP
PDACK Active Pulse Width
65
tKQP
PDACK Active Edge to PDRQ Inactive (Notes 2, 3)
tQKP
PDRQ to PDACK Active Edge
10
ns
tQPP
PDRQ Period
330
ms
tQQP
PDRQ Inactive Non-Burst Pulse Width
300
tQRP
PDRQ to RD, WR Active
15
tRQP
RD or WR Active Edge to PDRQ Inactive (Note 1)
65
ns
tTQP
TC Active Edge to PDRQ Inactive
75
ns
tTT
TC Active Pulse Width
ns
65 a (6 x 32 x tCP)
50
400
ns
ns
ns
ns
Note 1: The active edge of RD or WR and TC is recognized only when PDACK is active.
Note 2: One DMA transaction takes six clock cycles.
Note 3: tCP is defined in Section 12.2.2 Clock Timing.
TL/C/12379 – 80
FIGURE 12-12. ECP DMA Timing
101
12.0 Electrical Characteristics (Continued)
12.2.9 Reset Timing
Symbol
Parameter
tRW
Reset Width (Note 1)
tSRC
Reset to Control Inactive
Min
Max
Units
100
ms
300
ns
Note 1: The software reset pulse width is 100 ns.
TL/C/12379 – 81
Note 2: DRQ and IRQ6 will be TRI-STATE after time tSRC when in the PC-AT.
FIGURE 12-13. Reset Timing
12.2.10 FDC Write Data Timing
Symbol
Parameter
Min
Max
Units
tHDH
HDSEL Hold from WGATE Inactive
750
ms
tHDS
HDSEL Setup to WGATE Active
100
ms
tWDW
Write Data Pulse Width
Table 12-2
ns
TABLE 12-2. Minimum tWDW Values
Data Rate
tDRP
tWDW
tWDW Value
Units
1 Mbps
1000
2 x tICP
250
ns
500 kbps
2000
2 x tICP
250
ns
300 kbps
3333
2 x tICP
375
ns
250 kbps
4000
2 x tICP
500
ns
TL/C/12379 – 82
FIGURE 12-14. Write Data Timing
102
12.0 Electrical Characteristics (Continued)
12.2.11 FDC Read Data Timing
Symbol
tRDW
Parameter
Min
Read Data Pulse Width
50
Max
Units
ns
TL/C/12379 – 83
FIGURE 12-15. Read Data Timing
12.2.12 Drive Control Timing
Symbol
Parameter
Min
tDRV
DR0– 3, MTR0–3 from End of WR
tDST
DIR Setup to STEP Active
tIW
Max
100
Units
ns
6
ms
Index Pulse Width
100
ns
tSTD
DIR Hold from STEP Inactive
tSTR
ms
tSTP
STEP Active High Pulse Width
8
ms
tSTR
STEP Rate Time (see Table 4-15)
1
ms
TL/C/12379 – 84
FIGURE 12-16. Drive Control Timing
12.2.13 IDE Timing
Symbol
Parameter
Min
Max
Units
tAD
Delay from Address to Disable Strobe
25
ns
tAE
Delay from Address to Enable Strobe
25
ns
TL/C/12379 – 85
FIGURE 12-17. IDE Timing
103
12.0 Electrical Characteristics (Continued)
12.2.14 Parallel Port Timing
Parameter
Conditions
Type
tPDH
Symbol
Port Data Hold
(Note 1)
500
tPDS
Port Data Setup
(Note 1)
500
tPI
Port Interrupt
tSW
STB Width
Max
ns
ns
33
(Note 1)
Units
500
ns
ns
Note 1: These times are system dependent and are therefore not tested.
TL/C/12379 – 86
FIGURE 12-18. Compatible Mode Parallel Port Interrupt Timing
TL/C/12379 – 87
FIGURE 12-19. Extended Mode Parallel Port Interrupt Timing
TL/C/12379 – 88
FIGURE 12-20. Typical Parallel Port Data Exchange
104
12.0 Electrical Characteristics (Continued)
12.2.15 Enhanced Parallel Port Timing
Symbol
Parameter
tWW
WRITE Active from WR Active (Note 1)
tWST
DSTRB or ASTRB Active from WR Active
(Notes 1, 2)
tWEST
Conditions
DSTRB or ASTRB Active after
WRITE Active
Min
Max
Units
45
ns
EEP 1.7
45
ns
EPP 1.9
65
ns
EPP 1.7
0
ns
EPP 1.9
10
ns
50
ns
tWPDh
PD0–PD7 Hold after DSTRB or ASTRB
Inactive
tHRW
IOCHRDY Active after WAIT Active (Note 3)
tWPDS
PD0–PD7 Valid after WRITE Active
tEPDW
EPP Data Width
80
ns
tEPDh
EPP Data Width Hold after DSTRB
or ASTRB Inactive
0
ns
tZWSa
ZWS Valid after WR or RD Active
tZWSh
ZWS Hold after WR or RD Inactive
EPP 1.7
40
ns
D0 – 7 is stable 15 ns
before WR Active
15
ns
45
0
ns
ns
Note 1: tWST and tWW are valid in EPP 1.9 only if WAIT is low when WR becomes active, else tWST and tWW are measured from WAIT.
Note 2: The PC87306 design guarantees that WRITE will not change from low to high before DSTRB or ASTRB goes from low to high.
Note 3: In EPP 1.9, IOCHRDY inactive is measured from WR or RD.
TL/C/12379 – 89
FIGURE 12-21. Enhanced Parallel Port Timing
105
12.0 Electrical Characteristics (Continued)
12.2.16 Extended Capabilities Port Timing
12.2.16.1 Forward
Symbol
Parameter
Conditions
Min
Max
Units
tecdsf
Data Setup before STB Active
0
tecdhf
Data Hold after BUSY
0
ns
ns
teclhf
BUSY Setup after STB Active
75
ns
techhf
STB Active after BUSY
0
1
s
techlf
BUSY Setup after STB Inactive
0
35
ms
tecllf
STB Active after BUSY
0
ns
TL/C/12379 – 90
FIGURE 12-22. ECP Parallel Port Forward Timing Diagram
12.2.16.2 Backward
Symbol
Parameter
Conditions
Min
Max
Units
tecdsb
Data Setup before STB Active
0
tecdhb
Data Hold after BUSY
0
ns
ns
teclhb
BUSY Setup after STB Active
75
ns
techhb
STB Active after BUSY
0
1
s
techlb
BUSY Setup after STB Inactive
0
35
ms
tecllb
STB Active after BUSY
0
ns
TL/C/12379 – 91
FIGURE 12-23. ECP Parallel Port Backward Timing Diagram
106
12.0 Electrical Characteristics (Continued)
12.2.17 GPIO Write Timing
Symbol
tWGO
Parameter
Conditions
Min
Write data to GPIO update
Max
Units
300 (Note 1)
ns
Note 1: GPIO are open drain pins with 10 kX external pull-ups.
TL/C/12379 – 92
FIGURE 12-24. GPIO Write Timing
Note: Refer to Microprocessor Interface Timing for Read Timing.
12.2.18 RTC
Symbol
Parameter
Conditions
Min
Max
Units
ns
tRW
IOR to IRQ TRI-STATE
36
tRCI
MR to IRQ TRI-STATE
25
tRCL
MR High Time
100
ms
tVMR
VCC (4.5V) to MR
10
ms
ns
TL/C/12379 – 93
FIGURE 12-25. IRQ Release Delay
TL/C/12379 – 94
FIGURE 12-26. MR Timing
107
12.0 Electrical Characteristics (Continued)
12.2.19 Programmable Chip Select Timing
Parameter
Min
Max
Units
tCE
Symbol
Delay from Command to Enable Chip Select
0
25
ns
tCD
Delay from Command to Disable Chip Select
0
25
ns
TL/C/12379 – 95
FIGURE 12-27. Chip Select Timing
108
109
PC87306 SuperI/O Enhanced Sidewinder Lite Floppy Disk Controller, Keyboard Controller,
Real-Time Clock, Dual UARTs, Infrared Interface, IEEE 1284 Parallel Port, and IDE Interface
Physical Dimensions inches (millimeters)
Plastic Quad Flatpak
Order Number PC87306VUL
NS Package Number VUL160A
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