LM21305
5A Adjustable Frequency Synchronous Buck Regulator
General Description
Key Specifications
The LM21305 is a full-featured 5A synchronous buck POL
regulator optimized for solution size, flexibilty, and high conversion efficiency. High power density LM21305 designs are
achieved via monolithic integration of the high-side and lowside power MOSFETs, high switching frequency, currentmode control, and optimized thermal design. The efficiency
of the LM21305 is elevated at light loads with diode emulation
mode operation and at heavy loads by optimal design of the
MOSFET gate drivers to minimize switch dead-times and
body-diode conduction losses.
The LM21305 accepts a wide input voltage range of 3V to
18V, facilitating interface to all intermediate bus voltages, including 3.3V, 5V and 12V rails. An output voltage as low as
0.598V is supported with excellent setpoint accuracy and low
ripple and RMS noise. The LM21305 offers flexible system
configuration with programmable switching frequency from
300 kHz to 1.5 MHz using one resistor or via external clock
synchronization. On-chip bias supply sub-regulators alleviate
the need for external bias power and simplify PCB layout. The
device also offers internal soft-start to limit inrush current, prebiased and monotonic startup capability, cycle-by-cycle current limiting, and thermal shutdown. Peak current-mode
control with a high-gain error amplifier maintains stability
throughout the entire input voltage and load current ranges
and enables excellent line and load transient response.
Offered in a thermally enhanced LLP-28 package, the
LM21305 features internal output over-voltage and over-current protection circuits for increased system reliability. A precision enable pin and integrated input UVLO allow the turnon of the device to be tightly controlled and sequenced. An
integrated open-drain power good indicator provides power
rail sequencing capability and fault indication.
■
■
■
■
Single-rail input voltage range from 3V to 18V
0.598V feedback voltage reference
300 kHz to 1.5 MHz switching frequency range
LLP-28 package (5 x 5 x 0.8 mm, 0.5 mm pitch)
Features
■ High efficiency switcher core with integrated low RDSon
power MOSFETs
■ Resistor programmable switching frequency with
frequency synchronization
Internal soft-start with monotonic and pre-biased startup
Low shutdown quiescent current
Precision enable with hysteresis
PGOOD indicator function
Input under-voltage lock-out (UVLO)
Output over-voltage protection (OVP)
High-bandwidth load transient response with peak
current-mode control
■ Cycle-by-cycle current limiting
■ Thermal shutdown
■
■
■
■
■
■
■
Applications
■ POL regulation from 3.3V, 5V, and 12V supply rails
■ High efficiency supply for DSPs, FPGAs, ASICs and
processors
■ Broadband, networking and optical communications
infrastructure
Typical Application Circuit
30111101
© 2011 National Semiconductor Corporation
301111
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LM21305 5A Adjustable Frequency Synchronous Buck Regulator
September 27, 2011
LM21305
Connection Diagram
30111102
LLP-28 Package, Exposed Pad
NS Package Number SQA28B
Order Information
Order Number
NSC Package Drawing
Package Marking
LM21305SQ
LM21305SQX
SQA28B
21305SQ
LM21305SQE
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Supplied As
1000 units, tape & reel
4500 units, tape & reel
250 units, tape & reel
2
LM21305
Pin Descriptions
Number
Name
Type
1,2,27,28
PVIN
P
Pad Description
Input voltage to the power switches inside the device.
3,4,5,6
SW
P
Switch node output of the power switches. Voltage swings from PVIN to GND on this
pin. SW also delivers current to the external inductor.
7,8,9,10
PGND
G
Power ground for the internal power switches.
Compensation pin to connect to external compensation network.
11
COMP
A
12
PGOOD
OD
Power Good, open-drain output. If high, indicates the output voltage is regulated
within tolerance. A pull-up resistor (10 kΩ to 100 kΩ) is recommended for most
applications.
13
FB
A
Voltage Feedback pin. This pin can be connected to the output voltage directly or
through a resistor divider to set the output voltage range.
14,17,18,19,20,24
AGND
G
Analog ground for the internal bias circuitry.
15
EN
I
Precision enable pin. An external divider can be used to set the device turn-on
threshold. If not used, the EN pin should be connected to AVIN.
16
FREQ
A
Frequency setting pin. This pin can be connected to a resistor to AGND to set the
internal oscillator frequency. It also can be connected to an external clock source via
a capacitor such that the switching frequency of the device is synchronized to the
external clock.
21
2V5
P
2.5V output of internal regulator. This pin is only for bypassing the internal LDO.
Loading this pin is not recommended.
22,23
AVIN
P
Analog power input. AVIN powers the internal 2.5V and 5.0V LDOs which provide
bias current and internal driver power. It can be connected to PVIN through a low
pass RC filter or can be supplied by a separate rail.
25
5V0
P
5.0V output of internal regulator. This pin is only for bypassing the internal LDO.
Loading this pin is not recommended.
26
CBOOT
A
Bootstrap pin to drive the high-side switch. A bootstrap capacitor should be
connected between this pin and the SW pin.
PAD
PAD
P: Power
A: Analog
Exposed pad at the back of the device. The PAD should be connected to PGND, but
cannot be used as primary ground connection. Use multiple vias under the PAD for
optimal thermal performance.
I: Digital Input
3
OD: Open Drain
G: Ground
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LM21305
Maximum Continuous Power
Dissipation PD-MAX (Note 2)
Maximum Lead Temperature
Lead-free Compatible (Note 3)
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
PVIN, AVIN, SW, EN, PGOOD to
AGND
CBOOT to AGND
CBOOT to SW
5V0, FB, COMP, FREQ to AGND
2V5 to AGND
AGND to PGND
Junction Temperature (TJ-MAX)
Storage Temperature Range
260°C
ESD Ratings
−0.3V to +20V
All pins, Human Body Model (Note 4)
−0.3V to +25V
−0.3V to +5.5V
−0.3V to +6V
−0.3V to +3V
−0.3V to +0.3V
150°C
−65°C to 150°C
Electrical Characteristics
Internally limited
±2kV
Operating Ratings
PVIN to PGND, AGND
AVIN to PGND, AGND
3V to 18V
3V to 18V
Junction Temperature
Ambient Temperature
Junction-to-Ambient Thermal Resistance
θJA
−40°C to 125°C
−40°C to 85°C
32.4°C/W
(Note 7, Note 8)
Specifications with standard typeface are for TJ = 25°C, and those in boldface type apply over the full Operating Temperature
Range (TJ = -40°C to +125°C). Unless otherwise specified, VIN = VPVIN = VAVIN = 12V, VOUT = 3.3V, IOUT = 0A.
Symbol
Parameter
Remarks
Min
Typ
Max
Unit
0.588
0.598
0.608
V
VFB-default
Feedback pin factory-default
voltage
ΔVOUT/ΔIOUT
Load Regulation
IOUT = 0.1A to 5A
0.02
%/A
ΔVOUT/ΔVIN
Line Regulation
VPVIN = 3V to 18V
0.01
%/V
RDSonHS
High-Side Switch On
Resistance
IDS = 5A
44
mΩ
RDSonLS
Low-Side Switch On
Resistance
IDS = 5A
22
mΩ
ICL-HS
High-Side Switch Current Limit High-side FET
5.9
7.0
7.87
A
ICL-LS
Low-Side Switch Current Limit Low-side FET (Note 9)
5.9
8.0
10.2
A
INEG-CL-LS
Low-Side Switch Negative
Current Limit
-7.0
-4.1
-1.64
A
ISD
Quiescent Current, disabled
VAVIN = V PVIN = 5V
0.1
2
VAVIN = V PVIN = 18V
1
4.1
IQ
Quiescent Current, enabled,
not switching
VAVIN = V PVIN = 18V
9
9.7
IFB
Feedback Pin Input Bias
Current
VFB = 0.598V
1
nA
GM
Error Amplifier
Transconductance
2400
µS
AVOL
Error Amplifier Voltage Gain
65
dB
Low-side FET
VIH-OVP
OVP Tripping Threshold
Output voltage rising threshold,
percentage of VOUT
VHYST-OVP
OVP Hysteresis Window
Percentage of VOUT
VUVLO-HI-AVIN
µA
mA
103.5
109.5
AVIN UVLO Rising Threshold
2.84
2.93
2.987
V
VUVLO-LO-AVIN
AVIN UVLO Falling Threshold
2.66
2.73
2.83
V
VUVLO-HYS-AVIN
AVIN UVLO Hysteresis
Window
V5V0
Internal LDO1 Output Voltage
Measured at 5V0 pin, 1kΩ load
COUT-CAP-5V0
Recommended Capacitance
connected to 5V0 pin
Ceramic capacitor
ISHORT-5V0
Short Circuit Current of 5V0 pin
V2V5
Internal LDO2 output voltage
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Measured at 2V5 pin, 1kΩ load
4
115
-4.3
%
%
195
mV
4.88
V
1
µF
31
mA
2.47
V
Parameter
Remarks
Min
Ceramic capacitor
Typ
Max
Unit
COUT-CAP-2V5
Recommended Capacitance
connected to 2V5 pin
ISHORT-2V5
Short Circuit Current of 2V5 pin
VFCBOOT-D
Measured between 5V0 and
CBOOT Diode Forward Voltage
CBOOT @ 10 mA
ICBOOT
CBOOT Leakage Current
VCBOOT = 5.5V, not switching
TSTARTUP-DELAY
Startup Time from EN high to
the beginning of internal softstart
SS
Internal Soft-Start
10% to 90% VFB
1.41
2.7
4.15
ms
FOSC-NOM
Oscillator Frequency, nominal
measured at SW pin
RFRQ = 61.9 kΩ, 0.025%
695
750
795
kHz
FOSC-MAX
Maximum Oscillator Frequency
RFRQ = 28.4 kΩ
measured at SW pin
1500
kHz
FOSC-MIN
Minimum Oscillator Frequency
RFRQ = 167.5 kΩ
measured at SW pin
300
kHz
TOFF-MIN
Minimum Off-Time measured at fS = 1.5 MHz, VIN = 3.3V, VFB =
SW pin
1V, voltage divider ratio = 3.3
50
ns
TON-MIN
Minimum On-Time measured at fS = 1.5 MHz, voltage divider
SW pin
ratio = 1
70
ns
100
nF
47
mA
0.76
V
0.65
µA
160
µs
OSCILLATOR
LOGIC
VIH-EN
EN Pin Rising Threshold
1.1
1.2
1.3
V
VHYST-EN
EN Pin Hysteresis Window
130
200
302
mV
IEN-IN
EN Pin Input Current
VEN = 12V
18
23
µA
VIH-UV-PGOOD
PGOOD UV Rising Threshold
Percentage of VOUT
93
97.5
%
VHYST-UV-PGOOD
PGOOD UV Hysteresis
Threshold
Percentage of VOUT
IOL- PGOOD
PGOOD Sink Current
VOL = 0.2V
IOH- PGOOD
PGOOD Leakage Current
VOH = 18V
87.5
-4.2
%
3
mA
460
nA
THERMAL SHUTDOWN
TSD
Thermal Shutdown (Note 10)
160
°C
TSD-HYS
Thermal Shutdown Hysteresis
(Note 10)
10
°C
5
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LM21305
Symbol
LM21305
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the
device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the
Electrical Characteristics tables.
Note 2: The amount of Absolute Maximum power dissipation allowed in the device depends on the ambient temperature and can be calculated using the formula
P = (TJ – TA)/θJA, where TJ is the junction temperature, TA is the ambient temperature and θJA is the junction-to-ambient thermal resistance. Junction-to-ambient
thermal resistance is highly application and board-layout dependent. In applications where high power dissipation exists, special care must be paid to thermal
dissipation issues in PC board design. Internal thermal shutdown circuitry protects the device from permanent damage.
Note 3: For detailed soldering specifications, please refer to National Semiconductor Application Note AN-1187: Leadless Leadframe Package (LLP) (AN-1187).
http://www.national.com/an/AN/AN-1187.pdf
Note 4: The Human Body Model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin (MIL-STD-883 3015.7).
Note 5: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation
of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the following
equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).
Note 6: Junction-to-ambient thermal resistance (θJA) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the
JEDEC standard JESD51-7. The test board is a 4-layer standard JEDEC thermal test board or 4LJEDEC, 4" x 3" in size, with a 3 by 3 array of thermal vias. The
board has two embedded copper layers which cover roughly the same size as the board. The copper thickness for the four layers, starting from the top one, is 2
oz./1oz./1oz./2 oz. For LLP, thermal vias are placed between the die attach pad in the 1st. copper layer and 2nd. copper layer. Detailed description of the board
can be found in JESD 51-7. Ambient temperature in the simulation is 22°C, still air. Power dissipation is 1W. The value of θJA of this product can vary significantly
depending on PCB material, layout, and environmental conditions. In applications with high power dissipation (e.g. high VOUT, high IOUT), special care must be
paid to thermal dissipation issues. For more information on these topics, please refer to Application Note AN-1187: Leadless Leadframe Package (LLP).
Note 7: All limits are guaranteed by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested during production
with TJ = 25°C. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical
process control.
Note 8: Capacitors: low ESR surface-mount ceramic capacitors (MLCCs) are used in setting electrical characteristics.
Note 9: The low-side switch current limit is guaranteed to be higher than the high-side current limit.
Note 10: Guaranteed by design.
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6
Unless otherwise specified: VIN = 12V, VOUT = 3.3V, fS = 500 kHz,
TA = 25°C, L = 3.3 µH, COUT = 100 µF ceramic.
Efficiency with PVIN = AVIN = 12V, fS = 300 kHz
100
100
95
95
90
90
85
85
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency with PVIN = AVIN = 5V, fS = 300 kHz
80
75
70
65
VOUT = 3.3V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 0.8V
60
55
50
0
1
2
3
4
LOAD CURRENT (A)
80
75
70
65
VOUT = 5V
VOUT = 3.3V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 0.8V
60
55
50
5
0
1
2
3
4
LOAD CURRENT (A)
30111137
30111138
Efficiency with PVIN = AVIN = 12V, fS = 500 kHz
100
100
95
95
90
90
85
85
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency with PVIN = AVIN = 5V, fS = 500 kHz
80
75
70
65
VOUT = 3.3V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 0.8V
60
55
50
0
1
2
3
4
LOAD CURRENT (A)
80
75
70
65
VOUT = 5V
VOUT = 3.3V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 0.8V
60
55
50
5
0
1
2
3
4
LOAD CURRENT (A)
30111152
100
95
95
90
90
85
85
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency with PVIN = AVIN = 12V, fS = 1 MHz
100
80
75
70
65
VOUT = 3.3V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 0.8V
55
50
0
1
2
3
4
LOAD CURRENT (A)
5
30111153
Efficiency with PVIN = AVIN = 5V, fS = 1 MHz
60
5
80
75
70
65
VOUT = 5V
VOUT = 3.3V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 0.8V
60
55
50
5
0
30111139
1
2
3
4
LOAD CURRENT (A)
5
30111151
7
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LM21305
Typical Performance Characteristics
LM21305
Load Regulation (%)
Line Regulation (%)
0.10
LINE REGULATION (%)
LOAD REGULATION (%)
0.10
0.05
0.00
-0.05
-0.10
0.05
0.00
-0.05
-0.10
0
1
2
3
4
LOAD CURRENT (A)
5
3
6
9
12
15
INPUT VOLTAGE, PVIN (V)
18
30111127
30111130
VOUT Regulation (%) vs. Temperature
Quiescent Current, Not Switching
10
QUIESCENT CURRENT (mA)
VOUT REGULATION (%)
1.0
0.5
0.0
-0.5
8
7
6
-40°C
25°C
85°C
5
-1.0
-40
9
-20
0
20 40 60
TEMPERATURE (°C)
80
3
100
6
9
12
15
INPUT VOLTAGE (V)
30111159
30111128
High-Side and Low-Side MOSFET RDSon vs. Temperature
Switching Frequency vs. RFRQ
1800
70
High-Side RDSon (mΩ)
1600
FREQUENCY (kHz)
RDSON (mΩ)
60
50
40
30
20
10
-20
0
20
40
60
TEMPERATURE (°C)
1200
1000
800
600
400
0
80
100
-40°C
25°C
125°C
0 20 40 60 80 100 120 140 160 180
RFRQ (kΩ)
30111147
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1400
200
Low-Side RDSon (mΩ)
0
-40
18
30111157
8
LM21305
Soft-Start, No Load
Soft-Start with Resistive Load
30111184
30111192
Soft-Start with 2V Pre-Bias Voltage, No Load
Switching Waveform with 0A Load (DCM Operation)
30111193
30111155
Switching Waveform with 5A Load
Load Transient 0.1A to 5A
30111194
30111145
9
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10
Block Diagram
30111103
LM21305
The LM21305 employs peak current-mode control. The
0.598V reference is compared to the feedback signal at the
error amplifier (EA). The PWM modulator block compares the
on-time current sense information with the summation of the
EA output (control voltage) and slope compensation. The
PWM modulator outputs on/off signals to the high-side and
low-side MOSFET drivers. Adaptive dead-time control is applied to the PWM output such that shoot through current is
avoided. The drivers then amplify the PWM signals to control
the integrated high-side and low-side MOSFETs.
30111104
SWITCHING REGULATOR
The LM21305 employs a buck type (step-down) converter architecture. It utilizes many advanced features to achieve excellent voltage regulation and efficiency. This easy-to-use
regulator features two integrated switches and is capable of
supplying up to 5A of continuous output current. The regulator
utilizes peak current-mode control with slope compensation
scaled with switching frequency to optimize stability and transient response over the entire output voltage and switching
frequency ranges. Peak current-mode control also provides
inherent line feed-forward, cycle-by-cycle current limiting, and
easy loop compensation. The switching frequency can be adjusted between 300 kHz and 1.5 MHz. The device can operate
with a small external L-C filter and still provide very low output
voltage ripple. The precision internal voltage reference allows
the output to be set as low as 0.598V. Using an external compensation circuit, the regulator bandwidth can be selected
based on the switching frequency to provide fast load transient response. The switching regulator is specially designed
for high efficiency operation throughout the load range. Synchronous rectification yields high efficiency for low voltage
and heavy load current situations, while discontinuous conduction and diode emulation modes enable high efficiency
conversion at lighter load currents. Fault protection features
include: high-side and low-side switch current limiting, negative current limiting on the low-side switch, over-voltage protection and thermal shutdown. The device is available in the
LLP-28 package featuring an exposed pad to aid thermal dissipation. The LM21305 can be used in numerous applications
to efficiently step-down from a wide range of input rails: 3V to
18V.
FIGURE 1. Switching Frequency set by External Resistor
The other way is to synchronize the switching frequency to an
external clock in the range of 300 kHz to 1.5 MHz. The external clock should be applied through a 100 pF coupling capacitor, CFRQ, as shown in Figure 2.
30111105
FIGURE 2. Switching Frequency Synchronized to
External Clock
The recommendations for the external clock include peak-topeak voltage above 1.5V, duty cycle between 20% and 80%,
and the edge rate faster than 100 ns. Circuits that use an external clock should still have a resistor connected from the
FREQ pin to analog ground. The external clock frequency
should be within -10% to +50% of the frequency set by
RFRQ. This allows the regulator to continue operating at approximately the same switching frequency if the external clock
fails and the coupling capacitor on the clock side is grounded
or pulled to logic high.
If the external clock fails low, timeout circuits will prevent the
high-side FET from staying off for longer than 1.5 times the
switching period (switching period Ts = 1/fs). At the end of this
timeout period, the regulator will begin to switch at the frequency set by RFRQ.
If the external clock fails high, timeout circuits will again prevent the high-side FET from staying off longer than 1.5 times
the switching period. After this timeout period, the internal oscillator takes over and switches at a fixed 1 MHz until the
voltage on the FREQ pin has decayed to approximately 0.6V.
This decay follows the time constant of CFRQ and RFRQ, and
once it is complete the regulator will switch at the frequency
set by RFRQ.
PEAK CURRENT-MODE CONTROL
In most applications, the peak current-mode control architecture used in the LM21305 only requires two external components to achieve a stable design. External compensation
allows the user to set the crossover frequency and phase
margin, thus optimizing the transient performance of the device. For duty cycles above 50%, all peak current-mode control buck converters require the addition of an artificial ramp
to avoid sub-harmonic oscillation. This linear ramp is commonly referred to as slope compensation. The amount of
slope compensation in the LM21305 will automatically
change depending on the switching frequency: the higher the
switching frequency, the larger the slope compensation. This
allows smaller inductors to be used with high switching frequency to increase the power density.
LIGHT-LOAD OPERATION
The LM21305 offers increased efficiency at light loads by allowing Discontinuous Conduction Mode (DCM). When the
load current is less than half of the inductor ripple current, the
device will enter DCM thus preventing negative inductor current. The current at which this occurs is the critical conduction
boundary and can be calculated according to the following
equation:
SWITCHING FREQUENCY SETTING AND
SYNCHRONIZATION
The LM21305 switching regulator can operate at a frequency
ranging from 300 kHz to 1.5 MHz. The switching frequency
can be set / controlled in two ways. One is by selecting the
external resistor attached to the FREQ pin to set the internal
11
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LM21305
oscillator frequency which controls the switching frequency.
An external 100 pF capacitor, CFRQ, should also be connected
from the FREQ pin to analog ground as a noise filter, as
shown in Figure 1.
Operation Description
LM21305
where D is the duty cycle of the high-side switch, equal to the
high-side switch on-time divided by the switching period. For
more details, please refer to ‘Calculating the Duty Cycle’ section in the Design Guide provided later. Several diagrams are
shown in Figure 3 illustrating continuous conduction mode
(CCM), Discontinuous Conduction Mode (DCM), and the
boundary condition. It can be seen that in DCM, whenever the
inductor current reaches zero, the SW node will become high
impedance. Ringing will occur on this pin as a result of the LC
tank circuit formed by the inductor and the effective parasitic
capacitance at the switch node. At very light loads, usually
below 100 mA, several pulses may be skipped in between
switching cycles, effectively reducing the switching frequency
and further improving light-load efficiency.
30111119
FIGURE 4. Use External Resistor To Set The EN
Threshold
DEVICE ENABLE, SOFT-START AND PRE-BIAS
STARTUP CAPABILITY
The device output can be turned off by removing AVIN or
pulling the EN pin low. To enable the device, EN pin must be
high with the presence of AVIN and PVIN. Once enabled, the
device engages the internal soft-start. The soft-start feature
allows the regulator output to gradually reach the steady state
operating point, thus reducing stresses on the input supply
and controlling startup current. Soft-start begins at the rising
edge of EN with AVIN above UVLO level. It is important to
make sure PVIN is high when soft-start begins. The LM21305
allows AVIN to be higher than PVIN, or PVIN higher than
AVIN, as long as both of them are within their operating voltage ranges.
Soft-start of the LM21305 is controlled internally. It typically
takes 2.7 ms to finish the soft-start sequence. PGOOD will be
high after soft-start is finished.
The LM21305 is in a pre-biased state when the device initiates startup with an output voltage greater than zero. This
often occurs in many multi-rail applications such as when
powering an FPGA, ASIC, or DSP. In these applications, the
output can be pre-biased through parasitic conduction paths
from one supply rail to another. Even though the LM21305 is
a synchronous converter, it will not pull the output low when
a pre-bias condition exists. During startup, the LM21305 will
be in diode emulation mode with low-side switch turned off
when zero crossing of the inductor current is detected.
PEAK CURRENT PROTECTION AND NEGATIVE
CURRENT LIMITING
The LM21305 switching regulator detects the peak inductor
current and limits it to a value of 7A typical. To determine the
average current from the peak current, the inductor size, input
and output voltage, and switching frequency must be known.
The average current limit can be found by :
30111106
FIGURE 3. CCM And DCM Operation
PRECISION ENABLE
The enable (EN) pin allows the output of the device to be enabled or disabled with an external control signal. This pin is a
precision analog input that enables the device when the voltage exceeds 1.2V (typical). The EN pin has 200 mV (typical)
of hysteresis and will disable the output when the enable voltage falls below 1.0V (typical). If the EN pin is not used, it
should be pulled up to AVIN via a 10 kΩ to 100 kΩ resistor.
Since the enable pin has a precise turn-on threshold, it can
be used along with an external resistor divider network from
an external voltage to configure the device to turn on at a
precise voltage. The precision enable circuitry will remain active even when the device is disabled. The turn-on voltage
with a divider can be found by
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When the peak inductor current sensed from the high-side
switch reaches the current limit threshold, an over-current
event is triggered and the internal high-side FET turns off and
the low-side FET turns on allowing the inductor current to
ramp down until the next switching cycle. When the high-side
over-current condition persists, the output voltage will be reduced by the reduced high-side switch on-time.
In cases such as output short circuit or when high-side switch
minimum on-time conditions are reached, the high-side
switch current limiting may not be sufficient to limit the inductor current. The LM21305 features an additional low-side
12
internal circuitry, further pushing the LDOs into their RMS
current ratings and increasing power dissipation and die temperature.
The LM21305 allows AVIN to be as low as 3V which makes
the voltage at the 5V0 LDO lower than 5V. Low supply voltage
at the MOSFET drivers can increase on-time resistance of the
high-side and low-side MOSFETs and reduce efficiency of the
regulator. When AVIN is between 3V and 5.5V, the best practice is to short the 5V0 pin to AVIN to avoid the voltage drop
on the internal LDO. However, the device can be damaged if
the 5V0 pin is pulled to a voltage higher than 5.5V. For efficiency considerations, it is best to use AVIN = 5V if possible.
When AVIN is above 5V, reduced efficiency can be observed
at light load due to the power loss of the LDOs. When AVIN
is close to 3V, increased MOSFET on-state resistance can
reduce efficiency at high load current levels.
MINIMUM ON-TIME CONSIDERATIONS
Minimum on-time, TON-MIN, is the smallest duration of time that
the high-side MOSFET can be on. This time is typically 70 ns
in the LM21305. In CCM operation, the minimum on-time limit
imposes a minimum duty cycle of
PGOOD AND OVER- / UNDER-VOLTAGE HANDLING
PGOOD should be pulled high with an external resistor
(10kΩ to 100kΩ recommended). When the FB voltage is typically within -7% to +9.5% of the reference voltage, PGOOD
will be high. Otherwise, an internal open-drain pull-down device will pull PGOOD low. PGOOD should be tied to ground
if the function is not required.
The LM21305 has built-in under- and over-voltage comparators that control the power switches. Whenever there is an
excursion in output voltage above the set OVP threshold, the
device will terminate the present on-pulse, turn on the lowside FET, and pull PGOOD low. The low-side FET will remain
on until either the FB voltage falls back into regulation or the
inductor current zero-cross is detected which in turn tri-states
the FETs. If the output reaches the UVP threshold, the part
will continue switching and PGOOD will be asserted and go
low. To avoid false tripping during transient glitches, PGOOD
has 16 μs of built-in deglitch time to both rising and falling
edges. OVP is disabled during soft-start to prevent false triggering.
For a given output voltage, minimum on-time imposes limits
on the switching regulator when operating simultaneously at
high input voltage and high switching frequency. As the equation shows, reducing the operating frequency will alleviate the
minimum duty cycle constraint. With a given switching frequency and desired output voltage, the maximum allowed
PVIN can be approximated by
Similarly, if the PVIN input rail is fixed, the maximum switching
frequency without imposing minimum on-time can be found
by:
UVLO
The LM21305 has a built-in under-voltage lockout (UVLO)
protection circuit that prevents the device from switching until
the AVIN voltage reaches 2.93V (typical). The UVLO threshold has typically 190 mV of hysteresis that keeps the device
from responding to power-on glitches during startup.
In rare cases where steady-state operation at minimum duty
cycle is unavoidable, the regulator will automatically skip cycles to keep VOUT regulated, similar to light-load DCM operation.
INTERNAL REGULATORS
The LM21305 contains two internal low dropout (LDO) regulators to produce internal driving and bias voltage rails from
AVIN. One LDO produces 5V to power the internal MOSFET
drivers, the other produces 2.5V to power the internal bias
circuitry. Both the 5V0 or 2V5 LDOs should be bypassed to
analog ground (AGND) with an external ceramic capacitor (1
μF and 0.1 μF recommended, respectively). Good bypassing
is necessary to supply the high transient currents required by
the power MOSFET gate drivers. Applications with high input
voltage and high switching frequency will increase die temperature because of the higher power dissipation within the
LDOs. Connecting a load to the 5V0 or 2V5 pins is not recommended since it will degrade their driving capability to
THERMAL PROTECTION
Internal thermal shutdown circuitry is provided to protect the
integrated circuit in the event that the maximum junction temperature is exceeded. When activated, typically at 160°C, the
LM21305 tri-states the power MOSFETs and resets soft-start.
After the junction temperature cools to approximately 150°C,
the LM21305 starts up using the normal startup routine. This
feature is provided to prevent catastrophic failures from due
to device overheating.
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LM21305
switch current limit to prevent the inductor current from running away. The low-side switch current limit is set higher than
the high-side current limit, 8A typical. When the low-side
switch current is higher than the limit level, PWM pulses will
be skipped until the low-side over-current event is not detected during the entire low-side switch conduction time. Normal
PWM switching subsequently occurs when the condition is
removed. High-side and low-side current protections result in
a current limit that does not aggressively foldback for brief
over-current events, while at the same time providing frequency and voltage foldback protection during hard short
circuit conditions. The low-side switch also has negative current limit (-4.1A typical) for secondary protection, and this can
engage duing response to over-voltage events. If the negative
current limit is triggered, the low-side switch will be turned off.
The negative current will be forced to go through the high-side
switch body diode and will quickly reduce.
LM21305
account and highlighted throughout this discussion. To facilitate component selection discussions, the typical application
circuit shown below may be used as a reference. Unless otherwise indicated, all formulae assume units of Amps (A) for
current, Farads (F) for capacitance, Henries (H) for inductance, Volts (V) for voltages and Hertz (Hz) for frequencies.
Design Guide
This section walks the designer through the steps necessary
to select the external components to build a fully functional
efficient step-down power supply. As with any DC-DC converter, numerous tradeoffs are possible to optimize the design
for efficiency, size, and performance. These will be taken into
30111116
LM21305 Typical Application Circuit
In applications with low output voltage (<1.2V) and high load
current (> 3A), the losses should not be ignored when calculation the duty cycle. Considering the effect of conduction
losses associated with the MOSFETs and inductor, the duty
cycle can be approximated by:
SETTING THE OUTPUT VOLTAGE
The FB pin of the LM21305 can be connected to VOUT directly
or through a resistor divider. With an external resistor divider,
the output voltage can be scaled up from the 0.598V feedback
voltage. Figure 5 shows the connection of the divider and the
FB pin.
RDSonHS and RDSonLS are the on-state parasitic resistances of
the high-side and low-side MOSFETs, respectively. Rdcr is the
equivalent DC resistance of the inductor used in the output
filter. Other parasitics, such as PCB trace resistance, can be
included if desired. IOUT is the load current. It is also equal to
the average inductor current. The duty cycle will increase
slightly with increase of load current.
30111117
FIGURE 5. Setting the Output Voltage by Resistor Divider
The output voltage can be found by:
SUPPLY POWER AND INPUT CAPACITORS
PVIN is the supply voltage for the switcher power stage. It is
the input source that delivers the output power to the load.
The input capacitors on the PVIN rail supply the large AC
switching current drawn by the switching action of the internal
power MOSFETs. The input current of a buck converter is
discontinuous and the ripple current supplied by the input capacitor can be quite large. The input capacitor must be rated
to handle this current. To prevent large voltage transients, a
low ESR input capacitor sized for the maximum RMS current
should be used. The maximum RMS current is given by:
For example, if the desired output voltage is 1.2V, RFB1 = 10
kΩ and RFB2 = 10 kΩ can be used.
CALCULATING THE DUTY CYCLE
The first equation to calculate for any buck converter is duty
cycle. In an ideal (no loss) buck converter, the duty cycle can
be found by:
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14
LM21305
The power dissipation of the input capacitor is given by:
PD_CIN = I2RMS_CIN RESR_CIN(W) where RESR_CIN is the ESR of
the input capacitor. This equation has a maximum at PVIN =
2VOUT, where IRMS_CIN ≅ IOUT/2 and D ≅ 50%. This simple
worst-case condition is commonly used for design purposes
because even significant deviations from the worst case duty
cycle operating point do not offer much relief. Note that ripple
current ratings from capacitor manufacturers are often based
on only 2000 hours of life which makes it advisable to further
derate the capacitor, or choose a capacitor rated at a higher
temperature than required. Several capacitors may also be
paralleled to meet size or height requirements in the design.
For low input voltage applications, sufficient bulk input capacitance is needed to minimize transient effects during output load current changes. A 1 µF ceramic bypass capacitor is
also recommended directly adjacent the IC between the PVIN
and PGND pins.
Please refer to Figure 13 and the 'PCB Layout Considerations' section provided later in this document.
30111136
FIGURE 6. External Resistor Selection to Set
the Switching Frequency
AVIN FILTER
An RC filter should be added to prevent any switching noise
on PVIN from interfering with the internal analog circuitry connected to AVIN. These can be seen on the schematic as
components RF and CF. There is a practical limit to the size
of resistor RF as the AVIN pin will draw a short 60 mA burst
of current during startup and if RF is too large the resulting
voltage drop can trigger the UVLO comparator. A recommended 1 μF capacitor coupled with a 1Ω resistor provides
approximately 10 dB of attenuation at 500 kHz switching frequency.
INDUCTOR
A general recommendation for the filter inductor in an
LM21305 application is to keep a peak-to-peak ripple current
between 20% and 40% of the maximum DC load current of
5A. It also should have a sufficiently high saturation current
rating and a DCR as low as possible.
The peak-to-peak current ripple can be calculated by:
SWITCHING FREQUENCY SELECTION
The LM21305 supports a wide range of switching frequencies: 300 kHz to 1.5 MHz. The choice of switching frequency
is usually a compromise between conversion efficiency and
the size of the circuit. Lower switching frequency implies reduced switching losses (including gate charge losses, switch
transition losses, etc.) and usually results in higher overall efficiency. But higher switching frequency allows use of smaller
LC output filters and hence a more compact design. Lower
inductance also helps transient response (higher large-signal
slew rate of inductor current) and reduces the DCR losses.
The optimal switching frequency is usually a tradeoff in a given application and thus needs to be determined on a caseby-case basis. It is related to the input voltage, output voltage,
most common load current level, external component choices, and circuit size requirements. The choice of switching
frequency may also be limited if an operating condition triggers TON-MIN or TOFF-MIN. Please refer to the aforementioned
'Minimum On-Time Considerations' section.
The following equation or Figure 6 can be used to calculate
the resistance to obtain a desired frequency of operation:
It is recommended to choose L such that:
The inductor should be rated to handle the maximum load
current plus the ripple current:
IL(MAX) = ILOAD(MAX) + ΔiL(MAX)/2
An inductor with saturation current higher than the over-current protection limit is a safe choice. In general, it is desirable
to have lower inductance in switching power supplies, because it usually corresponds to faster transient response,
smaller DCR, and reduced size for more compact designs.
But too low of an inductance can generate too large of an
inductor ripple current such that over-current protection at the
full load could be falsely triggered. It also generates more
conduction loss, since the RMS inductor current is slightly
higher relative to that with lower current ripple at the same DC
current. Larger inductor ripple current also implies larger output voltage ripple with the same output capacitors. With peak
current-mode control, it is recommended to not have too small
of an inductor current ripple so that the peak current comparator has enough signal-to-noise ratio.
Once the inductance is determined, the type of inductor must
be selected. Ferrite designs have very low core losses and
are preferred at high switching frequencies, so design goals
can concentrate on copper loss and preventing saturation.
Ferrite core material saturates hard, which means that inductance collapses abruptly when the saturation current is exceeded. The ‘hard’ saturation results in an abrupt increase in
fs [kHz] = 31000 x RFRQ-0.9[kΩ]
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LM21305
X7R to maintain proper tolerance. Other types of capacitors
also can be used, particularly if large bulk capacitance is
needed (such as tantalum, POSCAP and OSCON). Such
electrolytic capacitors have lower ESR zero {1/(2πESR
*COUT} frequency than ceramic capacitors. The lower ESR
zero frequency can influence the control loop, particularly if it
occurs close to the desired crossover frequency. If high
switching frequency and high loop crossover frequency are
warranted, an all ceramic design can be more appropriate.
inductor ripple current and consequent output voltage ripple.
Do not allow the core to saturate!
OUTPUT CAPACITOR
The device is designed to be used with a wide variety of LC
filters. It is generally desirable to use as little output capacitance as possible to keep cost and size down. The output
capacitor(s), COUT, should be chosen with care since it directly
affects the steady state output voltage ripple, loop stability
and the voltage over/undershoot during a load current transient.
The output voltage ripple is essentially composed of two
parts. One is caused by the inductor current ripple going
through the equivalent series resistance (ESR) of the output
capacitors: ΔVOUT-ESR = ΔiLp-p * ESR.
The other is caused by the inductor current ripple charging
and discharging the output capacitors:
EFFICIENCY CONSIDERATIONS
The efficiency of a switching regulator is defined as the output
power divided by the input power times 100%. Efficiency also
can be found by:
It is often useful to analyze individual losses to determine what
is limiting the efficiency and what change would produce the
most improvement. Although all dissipative elements in the
circuit produce losses, three main sources usually account for
most of the losses in LM21305-based converters: 1) conduction losses; 2) switching and gate drive losses; 3) bias losses.
Conduction losses are the I2R losses in parasitic resistances
including on-state resistances of the internal switches RDSon,
equivalent inductor DC resistance Rdcr, and PC board trace
resistances Rtrace. The conduction loss can be approximated
by:
Figure 7 shows an illustration of the two ripple components.
Since the two ripple components are not in phase, the actual
peak-to-peak ripple is smaller than the sum of the two peaks:
The total conduction loss can be reduced by reducing these
parasitic resistances. For example, the LM21305 is designed
to have low RDSon internal MOSFET switches. The inductor
DCR should be small. The traces that conduct the current
should be wide, thick and as short as possible. Obviously, the
conduction losses affect the efficiency more at heavier load.
Switching losses include all the losses generated by the
switching action of the two power MOSFETs. Each time the
switch node swings from low to high or vice versa, charges
are applied or removed from the parasitic capacitance from
the SW node to GND. Each time a power MOSFET gate is
switched from low to high to low again, a packet of charge
moves from 5V0 to ground. Furthermore, each time a power
MOSFET is turned on or off, a transition loss is generated
related to the overlap of voltage and current. MOSFET parasitic diodes generate reverse recovery loss and dead time
conduction loss. RMS currents through the input and output
capacitor ESR also generate loss. All of these losses should
be evaluated and carefully considered to design a high efficiency switching power converter. Since these losses only
occur during ‘switching’, reducing the switching frequency always helps to reduce the switching loss and the resultant
improvement in efficiency is more pronounced at lighter load.
Since the 5V0 rail is an LDO output from AVIN, the current
drawn from AVIN is the same as iDrive and the associated
power loss is VAVIN * iDrive. The other portion of AVIN power
loss is the bias current through the 2V5 rail which equals
VAVIN* ibias. Powering AVIN from a 5V system rail provides an
optimal tradeoff between bias power loss and switching loss.
30111120
FIGURE 7. Two Components of VOUT Ripple
Output capacitance is usually limited by system transient performance specifications if the system requires tight voltage
regulation with presence of large current steps and fast slew
rates. When a fast large load transient occurs, output capacitors provide the required charge before the inductor current
can slew to the appropriate level. The initial output voltage
step is equal to the load current step multiplied by the ESR.
VOUT continues to droop until the control loop response increases or decreases the inductor current to supply the load.
To maintain a small over- or undershoot during a transient,
small ESR and large capacitance are desired. But these also
come with the penalty of higher cost and size. Thus, the motivation is to seek a fast control loop response to reduce the
output voltage deviation.
One or more ceramic capacitors are generally recommended
because they have very low ESR and remain capacitive up to
high frequencies. The capacitor dielectric should be X5R or
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30111188
Derating of maximum load current when D > 50% is also illustrated in Figure 8.
FIGURE 10. LM21305 Compensation Network
The overall loop transfer function is a product of the power
stage transfer function, internal amplifier gains and the feedback network transfer function and can be expressed by:
T(s) = Gain0Fp(s)Fh(s)Fcomp(s)
where Gain0 includes all the DC gains in the loop, Fp(s) represents the power stage pole and zero (including the inner
current loop), Fh(s) represents the sampling effect in such a
current-mode converter and Fcomp(s) is the transfer function
of the external compensator. Figure 11 shows an asymptotic
approximation plot of the loop gain.
30111195
FIGURE 8. LM21305 Maximum Load Current Derating
when D > 50%
CONTROL LOOP COMPENSATION
30111169
FIGURE 11. LM21305 Loop Gain Asymptotic
Approximation
The loop gain determines both static and dynamic performance of the converter. The power stage response is fixed
by the selection of the power components and the compensator is therefore designed around the power stage response
to achieve the desired loop response. The goal is to design a
control loop characteristic with high crossover frequency (or
loop bandwidth) and adequate gain and phase margins under
all operation conditions.
30111164
COMPENSATION COMPONENTS SELECTION
To select the compensation components, a desired crossover
frequency needs to be selected. It is recommended to select
fc equal to or lower than 1/6 of the switching frequency. The
effect of F h(s) can be ignored to simplify the design. The capacitor ESR zero is also assumed to be at least 3 times higher
than fc. The compensation resistor can be found by:
FIGURE 9. Control Block Diagram of a Peak CurrentMode Controlled Buck Converter
This section will not provide a rigorous analysis of currentmode control, but rather a simplified yet relatively accurate
method to determine the control loop compensation network.
The LM21305 employs a peak current-mode controller and
therefore the control loop block diagram representation involves two feedback loops (see Figure 9). The inner feedback
loop derives its feedback from the sensed inductor current
while the outer loop monitors the output voltage. The
LM21305 compensation components from COMP to AGND
are shown in Figure 10. The purpose of the compensator
block is to stabilize the control loop and achieve high performance in terms of the load transient response, audio suscep-
Cc1 does not affect the crossover frequency fc, but it sets the
compensator zero fZcomp and affects the phase margin of the
loop. For a fast design, Cc1 = 4.7 nF gives adequate performance in most LM21305 applications. Larger Cc1 capacitance
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LM21305
tibility and output impedance. The LM21305 will typically
require only a single resistor Rc and capacitor Cc1 for compensation. However, depending on the location of the power
stage ESR zero, a second (small) capacitor, Cc2, may be required to create a high frequency pole.
LOAD CURRENT DERATING WHEH DUTY CYCLE
EXCEEDS 50%
The LM21305 is optimized for lower duty cycle operation, e.g.
high input to output voltage ratio. The high-side MOSFET is
designed to be half the size of the low-side MOSFET thus
optimizing the relative levels of switching loss in the high-side
switch and the conduction loss in the low-side switch. The
continuous current rating of the low-side switch is the maximum load current of 5A, while the high-side MOSFET is rated
at 2.5A. If the LM21305 is operating with duty cycles higher
than 50%, the maximum output current should be derated.
LM21305
gives higher phase margin but at the expense of longer transient response settling time. It is recommended to set the
compensation zero no higher than fc/3 to ensure enough
phase margin, implying:
HIGH FREQUENCY CONSIDERATIONS
Fh(s) represents the additional magnitude and phase drop
around f s/2 caused by the switching behavior of the currentmode converter. Fh(s) contains a pair of double poles with
quality factor Qp at half of the switching frequency. It is a good
idea to check that Qp is between 0.15 and 2, ideally around
0.6. If Qp is too high, the resonant peaking at fs/2 could become severe and coincide with subharmonic oscillations in
the duty cycle and inductor current. If Qp is too low, the two
complex poles split, the converter begins to act like a voltagemode controlled converter and the compensation scheme
used above should be changed.
Fp(s) also contains the ESR zero of the output capacitors:
PLOTTING THE LOOP GAIN
To include the effect of Fh(s) and the ESR zero, the complete
loop gain can be plotted using a software tool such as MATLAB, Mathcad, or Excel. The components in the loop gain can
be determined as follows. The DC gain of the power stage
can be found by:
In a typical ceramic capacitor design, fESR is at least three
times higher than the desired crossover frequency fc. If fESR
is lower than fs/2, an additional capacitor Cc2 can be added
between the COMP pin and AGND to give a high-frequency
pole:
where fs is the switching frequency,
and D' = 1 − D.
Minimum ROUT should be used in the
ROUT = VOUT/IOUT. Fp(s) can be expressed by:
calculation
Cc2 should be much smaller than Cc1 to avoid affecting the
compensation zero.
BOOTSTRAP CAPACITOR
A capacitor is needed between the CBOOT pin and the SW
node to supply the gate drive charge when the high-side
switch is turning ON. The capacitor should be large enough
to supply the charge without significant voltage drop. A 0.1 µF
ceramic bootstrap capacitor is recommended in LM21305 applications.
where the power stage pole considering the slope compensation effect is:
5V0 AND 2V5 CAPACITORS
5V0 and 2V5 pins are internal LDO outputs. As previously
mentioned, the two LDOs are used for internal circuits only
and should not be substantially loaded. Output capacitors are
needed to stabilize the LDOs. Ceramic capacitors within a
specified range should be used to meet stability requirements. The dielectric should be X5R, X7R, or better and rated
for the required operating temperature range. Use the following table to choose a suitable LDO output capacitor:
The high frequency behavior Fh(s) can be expressed by:
Output Voltage
NOMINAL
where:
5V0
4.88V
1 µF ± 20% 16V
2V5
2.47V
0.1 µF ± 20% 10V
PCB LAYOUT CONSIDERATIONS
PC board layout is an important and critical part of any DCDC converter design. Poor PC board layout can disrupt the
performance of a DC-DC converter and surrounding circuitry
by contributing to EMI, ground bounce, resistive voltage loss
in the traces, and thermal problems. Erroneous signals can
reach the DC-DC converter, possibly resulting in poor regulation or instability.
Good PCB layout with an LM21305-based converter can be
implemented by following a few simple design rules.
The compensator network transfer function is:
With the above equations, the loop gain T(s) can be plotted
and more accurate loop performance metrics (crossover frequency and phase margin) can be determined.
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Capacitance (Recommended
Value and Minimum Voltage
Rating)
18
2.
3.
4.
5.
Provide adequate device heat sinking by utilizing the
PCB ground planes as the primary thermal path. As such,
the use of thermal vias facilitates the transfer of heat from
the LM21305 into the system board. Use at least a 4layer PCB with the copper thickness for the four layers,
starting from the top layer, of 2 oz/1oz/1oz/2 oz. Use a 3
by 3 array of 10mil thermal vias to connect the DAP to
the system ground plane heat sink. The vias should be
evenly distributed under the DAP. The system ground
planes should predominately be PGND planes
(representing input and output capacitor return paths,
input and output DC current return paths, etc.).
It is imperative that the input capacitors are located as
close as possible to the PVIN and PGND pins; the
inductor should be placed as close as possible to the SW
pins and output capacitors. This is to minimize the area
of switching current loops and reduce the resistive loss
of the high current path. Based the LM21305 pinout, a 1
µF to 10 µF ceramic capacitor can be placed right by pins
1, 2 and pin 7, across the SW node trace, as an addition
to the bulk input capacitors. Using a size 1206 or 1210
capacitor allows enough copper width for the switch node
to be routed underneath the capacitor for good
conduction (see LM21305 evaluation board layout
detailed in National Semiconductor Application Note
AN-2042).
The copper area of the switch node should be thick and
short to both provide a good conduction path for the
switch node current to the inductor and to minimize
radiated EMI. This also requires the inductor be placed
as close as possible to the SW pins.
The feedback trace from VOUT to the feedback divider
resistors should be routed away from the SW pin and
inductor to avoid contaminating this feedback signal with
switch noise. This is most important when high
resistances are used to set the output voltage. It is
recommended to route the feedback trace on a different
layer than the inductor and SW node trace such that a
ground plane exists between the feedback trace and
inductor/SW node polygon. This provides further
cancellation of EMI on the feedback trace.
If voltage accuracy at the load is important, make sure
feedback voltage sense is made directly at the load
terminals. Doing so will correct for voltage drops in the
PCB planes and traces and provide optimal output
voltage setpoint accuracy and load regulation. It is
6.
7.
8.
always better to place the resistor divider closer to the FB
node, rather than close to the load, as the FB node is the
input to the error amplifier and is thus noise sensitive.
COMP is also a noise sensitive node and the
compensation components should be located as close
as possible to the IC.
Make input and output power bus connections as wide
and short as possible. This reduces any voltage drops on
the input or output of the converter and can improve
efficiency. Use copper plates/planes on top to connect
the multiple PVIN pins and PGND pins together.
The 0.1 µF boot capacitor connected between the
CBOOT pin and SW node should be placed as close as
possible to the CBOOT and SW pins.
The frequency set resistor and its associated capacitor
should be placed as close as possible to the FREQ pin.
Thermal Considerations
The thermal characteristics of the LM21305 are specified using the parameter θJA, which relates junction temperature to
ambient temperature in a particular LM21305 application. Although the value of θJA is dependent on many variables, it still
can be used to approximate the operating junction temperature of the device.
To obtain an estimate of the device junction temperature, one
may use the following relationship: TJ = PDθJA + TA where
PD =
PIN x (1 − Efficiency) − 1.1 x IOUT2x Rdcr
TJ =
Junction temperature of the LM21305 in °C
PIN =
Input power in Watts (PIN = VIN x IIN)
θJA =
TA =
Junction-to-ambient thermal resistance of the
LM21305 in °C/W
Ambient temperature in °C
IOUT =
Output (load) current
Rdcr =
Inductor parasitic DC resistance
It is important to always keep the LM21305 operating junction
temperature (TJ) below 125°C to assure reliable operation. If
the junction temperature exceeds 160°C, the device will cycle
in and out of thermal shutdown. If thermal shutdown occurs,
it is a sign of inadequate heat-sinking and/or excessive power
dissipation in the device. PC board heat-sinking can be improved by using more thermal vias, a larger board, or more
heat-spreading layers within that board.
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LM21305
1.
LM21305
Application Circuit Example
30111170
FIGURE 12. LM21305 Application Circuit Example
Bill Of Materials (500kHz Switching
Frequency)
VOUT
1.2V
1.8V
2.5V
3.3V
5V
Package
CIN1
TANT 47 µF 25V
TANT 47 µF 25V
TANT 47 µF 25V
TANT 47 µF 25V
TANT 47 µF 25V
CASE D
CIN2
10 µF 25V
10 µF 25V
10 µF 25V
10 µF 25V
10 µF 25V
1210
CIN3
1.0 µF 25V
1.0 µF 25V
1.0 µF 25V
1.0 µF 25V
1.0 µF 25V
1206
CF
1.0 µF 25V
1.0 µF 25V
1.0 µF 25V
1.0 µF 25V
1.0 µF 25V
0603
C2V5, CBOOT
0.1 µF 16V
0.1 µF 16V
0.1 µF 16V
0.1 µF 16V
0.1 µF 16V
0603
C5V0
1.0 µF 16V
1.0 µF 16V
1.0 µF 16V
1.0 µF 16V
1.0 µF 16V
0603
CFRQ
100 pF 50V
100 pF 50V
100 pF 50V
100 pF 50V
100 pF 50V
0603
Cc
3300 pF 25V
3300 pF 25V
4700 pF 25V
4700 pF 25V
4700 pF 25V
0603
COUT1,
COUT2
47 µF 6.3V X5R
47 µF 6.3V X5R
47 µF 6.3V X5R
47 µF 10V X5R
47 µF 10V X5R
1210
L
1.5 µH 10A
2.2 µH 10A
2.2 µH 10A
3.3 µH 10A
3.3 µH 10A
SMD
RF
1Ω 1%
1Ω 1%
1Ω 1%
1Ω 1%
1Ω 1%
0603
RFRQ, RPG
100 kΩ 1%
100 kΩ 1%
100 kΩ 1%
100 kΩ 1%
100 kΩ 1%
0603
RFB2, REN
10 kΩ 1%
10 kΩ 1%
10 kΩ 1%
10 kΩ 1%
10 kΩ 1%
0603
Rc
3.32 kΩ 1%
4.22 kΩ 1%
5.10 kΩ 1%
7.15 kΩ 1%
8.2 kΩ 1%
0603
RFB1
10 kΩ 1%
20 kΩ 1%
31.6 kΩ 1%
45.3 kΩ 1%
73.2 kΩ 1%
0603
www.national.com
20
LM21305
PCB Layout
30111107
FIGURE 13. PCB Top Layer Copper and Silkscreen
An example of an LM21305 PCB layout is shown in Figure
13. Only the top layer copper and top silkscreen are shown.
For more details, please refer to National Semiconductor Application Note AN-2042.
21
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LM21305
Physical Dimensions inches (millimeters) unless otherwise noted
LLP-28 Package
NS Package Number SQA28B
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22
LM21305
Notes
23
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LM21305 5A Adjustable Frequency Synchronous Buck Regulator
Notes
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