54F/74F190 Up/Down Decade Counter with Preset and Ripple Clock General Description Features The ’F190 is a reversible BCD (8421) decade counter featuring synchronous counting and asynchronous presetting. The preset feature allows the ’F190 to be used in programmable dividers. The Count Enable input, the Terminal Count output and the Ripple Clock output make possible a variety of methods of implementing multistage counters. In the counting modes, state changes are initiated by the rising edge of the clock. Y Commercial Y Y Y High-speedÐ125 MHz typical count frequency Synchronous counting Asynchronous parallel load Cascadable Package Number Military Package Description N16E 16-Lead (0.300× Wide) Molded Dual-In-Line J16A 16-Lead Ceramic Dual-In-Line M16A 16-Lead (0.150× Wide) Molded Small Outline, JEDEC 54F190FM (Note 2) W16A 16-Lead Cerpack 54F190LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C 74F190PC 54F190DM (Note 2) 74F190SC (Note 1) Note 1: Devices also available in 13× reel. Use suffix e SCX. Note 2: Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB. Logic Symbols Connection Diagrams Pin Assignment for DIP, SOIC and Flatpak Pin Assignment for LCC TL/F/9494–1 IEEE/IEC TL/F/9494 – 2 TL/F/9494 – 3 TL/F/9494–4 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/9494 RRD-B30M75/Printed in U. S. A. 54F/74F190 Up/Down Decade Counter with Preset and Ripple Clock November 1994 Unit Loading/Fan Out 54F/74F Pin Names CE CP P0 – P3 PL U/D Q0 – Q3 RC TC Description U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL Count Enable Input (Active LOW) Clock Pulse Input (Active Rising Edge) Parallel Data Inputs Asynchronous Parallel Load Input (Active LOW) Up/Down Count Control Input Flip-Flop Outputs Ripple Clock Output (Active LOW) Terminal Count Output (Active HIGH) 1.0/3.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 50/33.3 50/33.3 20 mA/b1.8 mA 20 mA/b0.6 mA 20 mA/b0.6 mA 20 mA/b0.6 mA 20 mA/b0.6 mA b 1 mA/20 mA b 1 mA/20 mA b 1 mA/20 mA Functional Description Two types of outputs are provided as overflow/underflow indicators. The Terminal Count (TC) output is normally LOW and goes HIGH when a circuit reaches zero in the countdown mode or reaches 9 in the count-up mode. The TC output will then remain HIGH until a state change occurs, whether by counting or presetting or until U/D is changed. The TC output should not be used as a clock signal because it is subject to decoding spikes. The TC signal is also used internally to enable the Ripple Clock (RC) output. The RC output is normally HIGH. When CE is LOW and TC is HIGH, the RC output will go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again. This feature simplifies the design of multistage counters. For a discussion and illustrations of the various methods of implementing multistage counters, please see the ’F191 data sheet. The ’F190 is a synchronous up/down BCD decade counter containing four edge-triggered flip-flops, with internal gating and steering logic to provide individual preset, count-up and count-down operations. It has an asynchronous parallel load capability permitting the counter to be preset to any desired number. When the Parallel Load (PL) input is LOW, information present on the Parallel Data inputs (P0 – P3) is loaded into the counter and appears on the Q outputs. This operation overrides the counting functions, as indicated in the Mode Select Table. A HIGH signal on the CE input inhibits counting. When CE is LOW, internal state changes are initiated synchronously by the LOW-to-HIGH transition of the clock input. The direction of counting is determined by the U/D input signal, as indicated in the Mode Select Table, CE and U/D can be changed with the clock in either state, provided only that the recommended setup and hold times are observed. RC Truth Table Inputs Mode Select Table Output Inputs Mode CE TC* CP RC PL CE U/D CP L H X H X L ß X X ß H H H H L H L L X H L H X X L L X X *TC is generated internally H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial L e LOW-to-HIGH Clock Transition ß e LOW Pulse Count Up Count Down Preset (Asyn.) No Change (Hold) State Diagram TL/F/9494 – 5 2 Logic Diagram TL/F/9494 – 6 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b 65§ C to a 150§ C Ambient Temperature under Bias Junction Temperature under Bias Plastic b 55§ C to a 125§ C Free Air Ambient Temperature Military Commercial b 55§ C to a 125§ C 0§ C to a 70§ C Supply Voltage Military Commercial b 55§ C to a 175§ C b 55§ C to a 150§ C a 4.5V to a 5.5V a 4.5V to a 5.5V VCC Pin Potential to Ground Pin b 0.5V to a 7.0V b 0.5V to a 7.0V Input Voltage (Note 2) b 30 mA to a 5.0 mA Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0.5V to VCC Standard Output b 0.5V to a 5.5V TRI-STATEÉ Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol 54F/74F Parameter Min VIH Input HIGH Voltage VIL Input LOW Voltage Typ Units VCC Conditions Max 2.0 V Recognized as a HIGH Signal 0.8 V Recognized as a LOW Signal b 1.2 V Min IIN e b18 mA V Min IOH e b1 mA IOH e b1 mA IOH e b1 mA IOL e 20 mA IOL e 20 mA VCD Input Clamp Diode Voltage VOH Output HIGH Voltage 54F 10% VCC 74F 10% VCC 74F 5% VCC VOL Output LOW Voltage 54F 10% VCC 74F 10% VCC 0.5 0.5 V Min IIH Input HIGH Current 54F 74F 20.0 5.0 mA Max VIN e 2.7V IBVI Input HIGH Current Breakdown Test 54F 74F 100 7.0 mA Max VIN e 7.0V ICEX Output HIGH Leakage Current 54F 74F 250 50 mA Max VOUT e VCC VID Input Leakage Test 74F V 0.0 IID e 1.9 mA All Other Pins Grounded IOD Output Leakage Circuit Current 74F 3.75 mA 0.0 VIOD e 150 mV All Other Pins Grounded IIL Input LOW Current b 0.6 b 1.8 mA Max VIN e 0.5V, except CE VIN e 0.5V, CE IOS Output Short-Circuit Current b 150 mA Max VOUT e 0V ICCL Power Supply Current 55 mA Max VO e LOW 2.5 2.5 2.7 4.75 b 60 38 4 AC Electrical Characteristics Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V CL e 50 pF TA, VCC e Mil CL e 50 pF TA, VCC e Com CL e 50 pF Max Min Max Min Units Min Typ fmax Maximum Clock Frequency 100 125 tPLH tPHL Propagation Delay CP to Qn 3.0 5.0 5.5 8.5 7.5 11.0 3.0 5.0 9.5 13.5 3.0 5.0 8.5 12.0 tPLH tPHL Propagation Delay CP to TC 6.0 5.0 10.0 8.5 13.0 11.0 6.0 5.0 16.5 13.5 6.0 5.0 14.0 12.0 tPLH tPHL Propagation Delay CP to RC 3.0 3.0 5.5 5.0 7.5 7.0 3.0 3.0 9.5 9.0 3.0 3.0 8.5 8.0 tPLH tPHL Propagation Delay CE to RC 3.0 3.0 5.0 5.5 7.0 7.0 3.0 3.0 9.0 9.0 3.0 3.0 8.0 8.0 tPLH tPHL Propagation Delay U/D to RC 7.0 5.5 11.0 9.0 18.0 12.0 7.0 5.5 22.0 14.0 7.0 5.5 20.0 13.0 tPLH tPHL Propagation Delay U/D to TC 4.0 4.0 7.0 6.5 10.0 10.0 4.0 4.0 13.5 12.5 4.0 4.0 11.0 11.0 tPLH tPHL Propagation Delay Pn to Qn 3.0 6.0 4.5 10.0 7.0 13.0 3.0 6.0 9.0 16.0 3.0 6.0 8.0 14.0 ns tPLH tPHL Propagation Delay PL to Qn 5.0 5.5 8.5 9.0 11.0 12.0 5.0 5.5 13.0 14.5 5.0 5.5 12.0 13.0 ns 75 Max 90 MHz ns ns ns AC Operating Requirements Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V TA, VCC e Mil TA, VCC e Com Min Min Min Max Max Units Max ts(H) ts(L) Setup Time, HIGH or LOW Pn to PL 4.5 4.5 6.0 6.0 5.0 5.0 th(H) th(L) Hold Time, HIGH or LOW Pn to PL 2.0 2.0 2.0 2.0 2.0 2.0 ts(L) Setup Time, LOW CE to CP 10.0 10.5 10.0 th(L) Hold Time, LOW CE to CP 0 0 0 ts(H) ts(L) Setup Time, HIGH or LOW U/D to CP 12.0 12.0 12.0 12.0 12.0 12.0 th(H) th(L) Hold Time, HIGH or LOW U/D to CP 0 0 0 0 0 0 tw(L) PL Pulse Width, LOW 6.0 8.5 6.0 tw(L) CP Pulse Width, LOW 5.0 7.0 5.0 ns trec Recovery Time PL to CP 6.0 7.5 6.0 ns ns ns 5 ns ns Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74F 190 S Temperature Range Family 74F e Commercial 54F e Military C X Special Variations X e Devices shipped in 13× reels QB e Military grade device with environmental and burn-in processing shipped in tubes Device Type Package Code P e Plastic DIP D e Ceramic DIP F e Flatpak L e Leadless Chip Carrier (LCC) S e Small Outline SOIC JEDEC Temperature Range C e Commercial (0§ C to a 70§ C) M e Military (b55§ C to a 125§ C) 6 7 Physical Dimensions inches (millimeters) 20-Lead Ceramic Leadless Chip Carrier (L) NS Package Number E20A 16-Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A 8 Physical Dimensions inches (millimeters) (Continued) 16-Lead (0.150× Wide) Molded Small Outline Package, JEDEC (S) NS Package Number M16A 16-Lead (0.300× Wide) Molded Dual-In-Line Package (P) NS Package Number N16E 9 54F/74F190 Up/Down Decade Counter with Preset and Ripple Clock Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flatpak (F) NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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