54F/74F169 4-Stage Synchronous Bidirectional Counter General Description Features The ’F169 is a fully synchronous 4-stage up/down counter. The ’F169 is a modulo-16 binary counter. Features a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the LOW-to-HIGH transition of the clock. Y Commercial Y Y Asynchronous counting and loading Built-in lookahead carry capability Presettable for programmable operation Package Number Military Package Description N16E 16-Lead (0.300× Wide) Molded Dual-In-Line J16A 16-Lead Ceramic Dual-In-Line 74F169SC (Note 1) M16A 16-Lead (0.150× Wide) Molded Small Outline, JEDEC 74F169SJ (Note 1) M16D 16-Lead (0.300× Wide) Molded Small Outline, EIAJ 74F169PC 54F169DM (Note 2) Note 1: Devices also available in 13× reel. Use suffix e SCX and SJX. Note 2: Military grade device with environmental and burn-in processing. Use suffix e DMQB. Logic Symbols IEEE/IEC ’F169 TL/F/9488 – 3 TL/F/9488 – 9 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/9488 RRD-B30M75/Printed in U. S. A. 54F/74F169 4-Stage Synchronous Bidirectional Counter November 1994 Connection Diagrams Pin Assignment for DIP, SOIC and Flatpak Pin Assignment for LCC TL/F/9488–1 TL/F/9488 – 2 Unit Loading/Fan Out 54F/74F Pin Names CEP CET CP P0 – P3 PE U/D Q0 – Q3 TC Description U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL Count Enable Parallel Input (Active LOW) Count Enable Trickle Input (Active LOW) Clock Pulse Input (Active Rising Edge) Parallel Data Inputs Parallel Enable Input (Active LOW) Up-Down Count Control Input Flip-Flop Outputs Terminal Count Output (Active LOW) 1.0/1.0 1.0/2.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 50/33.3 20 mA/b0.6 mA 20 mA/b1.2 mA 20 mA/b0.6 mA 20 mA/b0.6 mA 20 mA/b0.6 mA 20 mA/b0.6 mA b 1 mA/20 mA b 1 mA/20 mA Functional Description CET is LOW, when a counter reaches zero in the Count Down mode or reaches 15 for the ’F169 in the Count Up mode. The TC output state is not a function of the Count Enable Parallel (CEP) input level. Since the TC signal is derived by decoding the flip-flop states, there exists the possibility of decoding spikes on TC. For this reason the use of TC as a clock signal is not recommended (see logic equations below). 1) Count Enable e CEP # CET # PE The ’F169 uses edge-triggered J-K type flip-flops and has no constraints on changing the control or data input signals in either state of the clock. The only requirement is that the various inputs attain the desired state at least a setup time before the rising edge of the clock and remain valid for the recommended hold time thereafter. The parallel load operation takes precedence over other operations, as indicated in the Mode Select Table. When PE is LOW, the data on the P0 – P3 inputs enters the flip-flops on the next rising edge of the clock. In order for counting to occur, both CEP and CET must be LOW and PE must be HIGH; the U/D input then determines the direction of counting. The Terminal Count (TC) output is normally HIGH and goes LOW, provided that 2) Up: (’F169): TC e Q0 # Q1 # Q2 # Q3 # (Up) # CET 3) Down: TC e Q0 # Q1 # Q2 # Q3 # (Down) # CET 2 Logic Diagram ’F169 TL/F/9488 – 5 Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. Mode Select Table PE CEP CET U/D Action on Rising Clock Edge L H H H H X L L H X X L L X H X H L X X Load (Pn x Qn) Count Up (Increment) Count Down (Decrement) No Change (Hold) No Change (Hold) State Diagram ’F169 TL/F/9488 – 7 3 H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b 65§ C to a 150§ C Ambient Temperature under Bias Junction Temperature under Bias Plastic b 55§ C to a 125§ C Free Air Ambient Temperature Military Commercial b 55§ C to a 125§ C 0§ C to a 70§ C Supply Voltage Military Commercial b 55§ C to a 175§ C b 55§ C to a 150§ C a 4.5V to a 5.5V a 4.5V to a 5.5V VCC Pin Potential to Ground Pin b 0.5V to a 7.0V b 0.5V to a 7.0V Input Voltage (Note 2) b 30 mA to a 5.0 mA Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0.5V to VCC Standard Output b 0.5V to a 5.5V TRI-STATEÉ Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol 54F/74F Parameter Min VIH Input HIGH Voltage VIL Input LOW Voltage Typ Units VCC Conditions Max 2.0 V Recognized as a HIGH Signal 0.8 V Recognized as a LOW Signal b 1.2 V Min IIN e b18 mA V Min IOH e b1 mA IOH e b1 mA IOH e b1 mA IOL e 20 mA IOL e 20 mA VCD Input Clamp Diode Voltage VOH Output HIGH Voltage 54F 10% VCC 74F 10% VCC 74F 5% VCC VOL Output LOW Voltage 54F 10% VCC 74F 10% VCC 0.5 0.5 V Min IIH Input HIGH Current 54F 74F 20.0 5.0 mA Max VIN e 2.7V IBVI Input HIGH Current Breakdown Test 54F 74F 100 7.0 mA Max VIN e 7.0V ICEX Output HIGH Leakage Current 54F 74F 250 50 mA Max VOUT e VCC VID Input Leakage Test 74F V 0.0 IID e 1.9 mA All Other Pins Grounded IOD Output Leakage Circuit Current 74F 3.75 mA 0.0 VIOD e 150 mV All Other Pins Grounded IIL Input LOW Current b 0.6 b 1.2 mA Max VIN e 0.5V (except CET) VIN e 0.5V (CET) IOS Output Short-Circuit Current b 150 mA Max VOUT e 0V ICCL Power Supply Current 52 mA Max VO e LOW 2.5 2.5 2.7 4.75 b 60 35 4 ’F169 AC Electrical Characteristics Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V CL e 50 pF TA, VCC e Mil CL e 50 pF TA, VCC e Com CL e 50 pF Min Typ Max Min Max Min 60 Units Max fmax Maximum Count Frequency 90 tPLH tPHL Propagation Delay CP to Qn (PE HIGH or LOW) 3.0 4.0 6.5 9.0 8.5 11.5 3.0 4.0 12.0 16.0 3.0 4.0 70 9.5 13.0 MHz ns tPLH tPHL Propagation Delay CP to TC 5.5 4.0 12.0 8.5 15.5 12.5 5.5 4.0 20.0 15.0 5.5 4.0 17.5 13.0 ns tPLH tPHL Propagation Delay CET to TC 2.5 2.5 4.5 8.5 6.5 11.0 2.5 2.5 9.0 12.0 2.5 2.5 7.0 12.0 ns tPLH tPHL Propagation Delay U/D to TC 3.5 4.0 8.5 8.0 11.5 12.0 3.5 4.0 16.0 14.0 3.5 4.0 12.5 13.0 ns AC Operating Requirements Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V TA, VCC e Mil TA, VCC e Com Min Min Min Max Max ts(H) ts(L) Setup Time, HIGH or LOW Pn to CP 4.0 4.0 4.5 4.5 4.5 4.5 th(H) th(L) Hold Time, HIGH or LOW Pn to CP 3.0 3.0 3.5 3.5 3.5 3.5 ts(H) ts(L) Setup Time, HIGH or LOW CEP or CET to CP 7.0 5.0 8.0 8.0 8.0 6.5 th(H) th(L) Hold Time, HIGH or LOW CEP or CET to CP 0 0.5 0 1.0 0 0.5 ts(H) ts(L) Setup Time, HIGH or LOW PE to CP 8.0 8.0 10.0 10.0 9.0 9.0 th(H) th(L) Hold Time, HIGH or LOW PE to CP 1.0 0 1.0 0 1.0 0 ts(H) ts(L) Setup Time, HIGH or LOW U/D to CP 11.0 7.0 14.0 12.0 12.5 8.5 th(H) th(L) Hold Time, HIGH or LOW U/D to CP 0 0 0 0 0 0 tw(H) tw(L) CP Pulse Width HIGH or LOW 4.0 7.0 6.0 9.0 4.5 8.0 5 Units Max ns ns ns ns ns Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74F 169 S Temperature Range Family 74F e Commercial 54F e Military C X Special Variations X e Devices shipped in 13× reels QB e Military grade device with environmental and burn-in processing shipped in tubes Device Type Package Code P e Plastic DIP D e Ceramic DIP S e Small Outline Package SOIC JEDEC SJ e Small Outline SOIC EIAJ Temperature Range C e Commercial (0§ C to a 70§ C) M e Military (b55§ C to a 125§ C) Physical Dimensions inches (millimeters) 16-Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A 6 Physical Dimensions inches (millimeters) (Continued) 16-Lead (0.150× Wide) Molded Small Outline Package, JEDEC (S) NS Package Number M16A 16-Lead (0.300× Wide) Molded Dual-In-Line Package (P) NS Package Number N16E 7 54F/74F169 4-Stage Synchronous Bidirectional Counter Physical Dimensions inches (millimeters) (Continued) 16-Lead (0.300× Wide) Molded Small Outline Package, EIAJ (SJ) NS Package Number M16D LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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