54F/74F161A # 54F/74F163A Synchronous Presettable Binary Counter General Description Features The ’F161A and ’F163A are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multi-stage counters. The ’F161A has an asynchronous Master-Reset input that overrides all other inputs and forces the outputs LOW. The ’F163A has a Synchronous Reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset on the rising edge of the clock. The ’F161A and ’F163A are high-speed versions of the ’F161 and ’F163. Y Commercial Package Number Military 74F161APC 54F161ADM (Note 2) Y Y Y Synchronous counting and loading High-speed synchronous expansion Typical count frequency of 120 MHz Guaranteed 4000V minimum ESD protection Package Description N16E 16-Lead (0.300× Wide) Molded Dual-In-Line J16A 16-Lead Ceramic Dual-In-Line 74F161ASC (Note 1) M16A 16-Lead (0.150× Wide) Molded Small Outline, JEDEC 74F161ASJ (Note 1) M16D 16-Lead (0.300× Wide) Molded Small Outline, EIAJ 54F161AFM (Note 2) W16A 16-Lead Cerpack 54F161ALM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C N16E 16-Lead (0.300× Wide) Molded Dual-In-Line J16A 16-Lead Ceramic Dual-In-Line 74F163ASC (Note 1) M16A 16-Lead (0.150× Wide) Molded Small Outline, JEDEC 74F163ASJ (Note 1) M16D 16-Lead (0.300× Wide) Molded Small Outline, EIAJ 54F163AFM (Note 2) W16A 16-Lead Cerpack 54F163ALM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C 74F163APC 54F163ADM (Note 2) Note 1: Devices also available in 13× reel. Use suffix e SCX and SJX. Note 2: Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB. Connection Diagrams Pin Assignment for DIP, SOIC and Flatpak ’F161A Pin Assignment for LCC ’F161A TL/F/9486–1 TL/F/9486 – 2 Pin Assignment for DIP, SOIC and Flatpak ’F163A TL/F/9486 – 7 Pin Assignment for LCC ’F163A TL/F/9486 – 8 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/9486 RRD-B30M75/Printed in U. S. A. 54F/74F161A # 54F/74F163A Synchronous Presettable Binary Counter November 1994 Logic Symbols ’F161A ’F163A TL/F/9486–3 TL/F/9486 – 9 IEEE/IEC ’F161A IEEE/IEC ’F163A TL/F/9486–6 TL/F/9486 – 10 Unit Loading/Fan Out 54F/74F Pin Names Description U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL CEP CET CP MR (’F161A) SR (’F163A) P0 – P3 PE Q 0 – Q3 TC Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input (Active Rising Edge) Asynchronous Master Reset Input (Active LOW) Synchronous Reset Input (Active LOW) Parallel Data Inputs Parallel Enable Input (Active LOW) Flip-Flop Outputs Terminal Count Output 1.0/1.0 1.0/2.0 1.0/1.0 1.0/1.0 1.0/2.0 1.0/1.0 1.0/2.0 50/33.3 50/33.3 20 mA/b0.6 mA 20 mA/b1.2 mA 20 mA/b0.6 mA 20 mA/b0.6 mA 20 mA/b1.2 mA 20 mA/b0.6 mA 20 mA/b1.2 mA b 1 mA/20 mA b 1 mA/20 mA 2 Functional Description flip-flops on the next rising edge of CP. With PE and MR (’F161A) or SR (’F163A) HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting. The ’F161A and ’F163A use D-type edge triggered flip-flops and changing the SR, PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. The Terminal Count (TC) output is HIGH when CET is HIGH and the counter is in state 15. To implement synchronous multi-stage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. Please refer to the ’F568 data sheet. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, counters or registers. Logic Equations: Count Enable e CEP # CET # PE The ’F161A and ’F163A count in modulo-16 binary sequence. From state 15 (HHHH) they increment to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs (except due to Master Reset of the ’F161A) occur as a result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence: asynchronous reset (’F161A), synchronous reset (’F163A), parallel load, count-up and hold. Five control inputsÐMaster Reset (MR, ’F161A), Synchronous Reset (SR, ’F163A), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET)Ðdetermine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. A LOW signal on SR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the TC e Q0 # Q1 # Q2 # Q3 # CET State Diagram Mode Select Table *SR PE CET CEP L H H H H X L H H H X X H L X X X H X L Action on the Rising Clock Edge (L) Reset (Clear) Load (Pn x Qn) Count (Increment) No Change (Hold) No Change (Hold) *For ’F163A only H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial TL/F/9486 – 5 3 TL/F/9486 – 4 Block Diagram 4 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b 65§ C to a 150§ C Ambient Temperature under Bias Junction Temperature under Bias Plastic b 55§ C to a 125§ C Free Air Ambient Temperature Military Commercial b 55§ C to a 125§ C 0§ C to a 70§ C Supply Voltage Military Commercial b 55§ C to a 175§ C b 55§ C to a 150§ C a 4.5V to a 5.5V a 4.5V to a 5.5V VCC Pin Potential to Ground Pin b 0.5V to a 7.0V b 0.5V to a 7.0V Input Voltage (Note 2) b 30 mA to a 5.0 mA Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0.5V to VCC Standard Output b 0.5V to a 5.5V TRI-STATEÉ Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) ESD Last Passing Voltage (Min) 4000V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol 54F/74F Parameter Min VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage 54F 10% VCC 74F 10% VCC 74F 5% VCC VOL Output LOW Voltage 54F 10% VCC 74F 10% VCC IIH Input HIGH Current IBVI Typ Units VCC Conditions Max 2.0 V 0.8 V b 1.2 V 2.5 2.5 2.7 Recognized as a HIGH Signal Recognized as a LOW Signal Min IIN e b18 mA IOH e b1 mA V Min 0.5 0.5 V Min IOL e 20 mA 54F 74F 20.0 5.0 mA Max VIN e 2.7V Input HIGH Current Breakdown Test 54F 74F 100 7.0 mA Max VIN e 7.0V ICEX Output HIGH Leakage Current 54F 74F 250 50 mA Max VOUT e VCC VID Input Leakage Test 74F V 0.0 IID e 1.9 mA All Other Pins Grounded IOD Output Leakage Circuit Current 74F 3.75 mA 0.0 VIOD e 150 mV All Other Pins Grounded IIL Input LOW Current b 0.6 b 1.2 mA mA Max Max VIN e 0.5V (CEP, CP, MR, P0 –P3) VIN e 0.5V (CET, PE, SR) IOS Output Short-Circuit Current b 150 mA Max VOUT e 0V ICC Power Supply Current 55 mA Max 4.75 b 60 37 5 AC Electrical Characteristics Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V CL e 50 pF TA, VCC e Mil CL e 50 pF TA, VCC e Com CL e 50 pF Max Min Max Min Units Min Typ fmax Maximum Count Frequency 100 120 tPLH tPHL Propagation Delay CP to Qn (PE Input HIGH) 3.5 3.5 5.5 7.5 7.5 10.0 3.5 3.5 9.0 11.5 3.5 3.5 8.5 11.0 tPLH tPHL Propagation Delay CP to Qn (PE Input LOW) 4.0 4.0 6.0 6.0 8.5 8.5 4.0 4.0 10.0 10.0 4.0 4.0 9.5 9.5 tPLH tPHL Propagation Delay CP to TC 5.0 5.0 10.0 10.0 14.0 14.0 5.0 5.0 16.5 15.5 5.0 5.0 15.0 15.0 ns tPLH tPHL Propagation Delay CET to TC 2.5 2.5 4.5 4.5 7.5 7.5 2.5 2.5 9.0 9.0 2.5 2.5 8.5 8.5 ns tPHL Propagation Delay MR to Qn (’F161A) 5.5 9.0 12.0 5.5 14.0 5.5 13.0 ns tPHL Propagation Delay MR to TC (’F161A) 4.5 8.0 10.5 4.5 12.5 4.5 11.5 ns 75 Max 90 MHz ns AC Operating Requirements Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V TA, VCC e Mil TA, VCC e Com Min Min Min Max Max Units Max ts(H) ts(L) Setup Time, HIGH or LOW Pn to CP 5.0 5.0 5.5 5.5 5.0 5.0 th(H) th(L) Hold Time, HIGH or LOW Pn to CP 2.0 2.0 2.5 2.5 2.0 2.0 ts(H) ts(L) Setup Time, HIGH or LOW PE or SR to CP 11.0 8.5 13.5 10.5 11.5 9.5 th(H) th(L) Hold Time, HIGH or LOW PE or SR to CP 2.0 0 3.6 0 2.0 0 ts(H) ts(L) Setup Time, HIGH or LOW CEP or CET to CP 11.0 5.0 13.0 6.0 11.5 5.0 th(H) th(L) Hold Time, HIGH or LOW CEP or CET to CP 0 0 0 0 0 0 tw(H) tw(L) Clock Pulse Width (Load) HIGH or LOW 5.0 5.0 5.0 5.0 5.0 5.0 ns tw(H) tw(L) Clock Pulse Width (Count) HIGH or LOW 4.0 6.0 5.0 8.0 4.0 7.0 ns tw(L) MR Pulse Width, LOW (’F161A) 5.0 5.0 5.0 ns trec Recovery Time MR to CP (’F161A) 6.0 6.0 6.0 ns 6 ns ns ns Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74F 161A/163A Temperature Range Family 74F e Commercial 54F e Military S C X Special Variations QR e Commercial grade device with burn-in QB e Military grade device with environmental and burn-in processing X e Devices shipped in 13× reel Device Type Package Code P e Plastic DIP D e Ceramic DIP F e Flatpak L e Leadless Chip Carrier (LCC) S e Small Outline Package SOIC JEDEC SJ e Small Outline Package SOIC EIAJ Temperature Range C e Commercial (0§ C to a 70§ C) M e Military (b55§ C to a 125§ C) Physical Dimensions inches (millimeters) 20-Lead Ceramic Leadless Chip Carrier (L) NS Package Number E20A 7 Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A 16-Lead (0.150× Wide) Molded Small Outline Package, JEDEC (S) NS Package Number M16A 8 Physical Dimensions inches (millimeters) (Continued) 16-Lead (0.300× Wide) Molded Small Outline Package, EIAJ (SJ) NS Package Number M16D 16-Lead (0.300× Wide) Molded Dual-In-Line Package (P) NS Package Number N16E 9 54F/74F161A # 54F/74F163A Synchronous Presettable Binary Counter Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flatpak (F) NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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