CD4514BM/CD4514BC, CD4515BM/CD4515BC 4-Bit Latched/4-to-16 Line Decoders General Description Features The CD4514B and CD4515B are 4-to-16 line decoders with latched inputs implemented with complementary MOS (CMOS) circuits constructed with N- and P-channel enhancement mode transistors. These circuits are primarily used in decoding applications where low power dissipation and/or high noise immunity is required. The CD4514B (output active high option) presents a logical ‘‘1’’ at the selected output, whereas the CD4515B presents a logical ‘‘0’’ at the selected output. The input latches are R – S type flip-flops, which hold the last input data presented prior to the strobe transition from ‘‘1’’ to ‘‘0’’. This input data is decoded and the corresponding output is activated. An output inhibit line is also available. Y Y Y Y Y Y Y Wide supply voltage range High noise immunity Low power TTL compatibility Low quiescent power dissipation 3.0V to 15V 0.45 VDD (typ.) fan out of 2 driving 74L 0.025 mW/package @ 5.0 V DC Single supply operation Input impedance e 1012X typically Plug-in replacement for MC14514, MC14515 Logic and Connection Diagrams TL/F/5994 – 1 Dual-In-Line Package Order Number CD4514B or CD4515B TL/F/5994 – 2 Top View TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/5994 RRD-B30M105/Printed in U. S. A. CD4514BM/CD4514BC, CD4515BM/CD4515BC 4-Bit Latched/4-to-16 Line Decoders February 1988 Absolute Maximum Ratings (Notes 1 and 2) Recommended Operating Conditions (Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. DC Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering, 10 seconds) DC Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) CD4514BM, CD4515BM CD4514BC, CD4515BC b 0.5V to a 18V b 0.5V to VDD a 0.5V b 65§ C to a 150§ C 3V to 15V 0V to VDD b 55§ C to a 125§ C b 40§ C to a 85§ C 700 mW 500 mW 260§ C DC Electrical Characteristics CD4514BM, CD4515BM (Note 2) Symbol Parameter b 55§ C Conditions Min a 25§ C Max Min a 125§ C Min Units Typ Max Max 5 10 20 0.005 0.010 0.015 5 10 20 150 300 600 mA mA mA 0.05 0.05 0.05 0 0 0 0.05 0.05 0.05 0.05 0.05 0.05 V V V IDD Quiescent Device Current VDD e 5V, VIN e VDD or VSS VDD e 10V, VIN e VDD or VSS VDD e 15V, VIN e VDD or VSS VOL Low Level Output Voltage VIH e VDD, lIOl k 1 mA VDD e 5V, VIL e 0V VDD e 10V VDD e 15V High Level Output Voltage VIH e VDD, lIOl k 1 mA VDD e 5V, VIL e 0V VDD e 10V VDD e 15V Low Level Input Voltage VO e 0.5V or 4.5V VDD e 5V, lIOl k 1 mA VDD e 10V, VO e 1.0V or 9.0V VDD e 15V, VO e 1.5V or 13.5V High Level Input Voltage VO e 0.5V or 4.5V VDD e 5V, lIOl k 1 mA VDD e 10V, VO e 1.0V or 9.0V VDD e 15V, VO e 1.5V or 13.5V 3.5 7.0 11.0 3.5 7.0 11.0 2.75 5.50 8.25 3.5 7.0 11.0 V V V IOL Low Level Output Current (Note 3) VDD e 5V, VO e 0.4V VDD e 10V, VO e 0.5V VDD e 15V, VO e 1.5V 0.64 1.6 4.2 0.51 1.3 3.4 0.88 2.25 8.80 0.36 0.90 2.40 mA mA mA IOH High Level Output Current (Note 3) VDD e 5V, VO e 4.6V VDD e 10V, VO e 9.5V VDD e 15V, VO e 13.5V b 0.64 b 1.6 b 4.2 b 0.51 b 1.3 b 3.4 b 0.88 b 2.25 b 8.80 b 0.36 b 0.90 b 2.40 mA mA mA IIN Input Current VDD e 15V, VIN e 0V VDD e 15V, VIN e 15V VOH VIL VIH 4.95 9.95 14.95 4.95 9.95 14.95 1.5 3.0 4.0 5 10 15 2.25 4.50 6.75 4.95 9.95 14.95 V V V 1.5 3.0 4.0 1.5 3.0 4.0 b 0.1 b 10 b 5 b 0.1 b 1.0 0.1 10b5 0.1 1.0 V V V mA mA DC Electrical Characteristics CD4514BC, CD4515BC (Note 2) Symbol Parameter b 40§ C Conditions Min IDD Quiescent Device Current VDD e 5V, VIN e VDD or VSS VDD e 10V, VIN e VDD or VSS VDD e 15V, VIN e VDD or VSS VOL Low Level Output Voltage VIL e 0V, VIH e VDD, lIOl k 1 mA VDD e 5V VDD e 10V VDD e 15V VOH High Level Output Voltage VIL e 0V, VIH e VDD, lIOl k 1 mA VDD e 5V VDD e 10V VDD e 15V 4.95 9.95 14.95 2 Max a 25§ C Min a 85§ C Max 20 40 80 0.005 0.010 0.015 20 40 80 150 300 600 mA mA mA 0.05 0.05 0.05 0 0 0 0.05 0.05 0.05 0.05 0.05 0.05 V V V 4.95 9.95 14.95 5.0 10.0 15.0 Min Units Typ 4.95 9.95 14.95 Max V V V DC Electrical Characteristics CD4514BC, CD4515BC (Note 2) (Continued) Symbol Parameter b 40§ C Conditions Min Max a 25§ C Min a 85§ C Typ Max 2.25 4.50 6.75 1.5 3.0 4.0 Min Units Max Low Level Input Voltage lIOl k 1 mA VDD e 5V, VO e 0.5V or 4.5V VDD e 10V, VO e 1.0V or 9.0V VDD e 15V, VO e 1.5V or 13.5V High Level Input Voltage lIOl k 1 mA VDD e 5V, VO e 0.5V or 4.5V VDD e 10V, VO e 1.0V or 9.0V VDD e 15V, VO e 1.5V or 13.5V 3.5 7.0 11.0 3.5 7.0 11.0 2.75 5.50 8.25 3.5 7.0 11.0 V V V IOL Low Level Output Current (Note 3) VDD e 5V, VO e 0.4V VDD e 10V, VO e 0.5V VDD e 15V, VO e 1.5V 0.52 1.3 3.6 0.44 1.1 3.0 0.88 2.25 8.8 0.36 0.90 2.4 mA mA mA IOH High Level Output Current (Note 3) VDD e 5V, VO e 4.6V VDD e 10V, VO e 9.5V VDD e 15V, VO e 13.5V b 0.52 b 1.3 b 3.6 b 0.44 b 1.1 b 3.0 b 0.88 b 2.25 b 8.8 b 0.36 b 0.90 b 2.4 mA mA mA IIN Input Current VDD e 15V, VIN e 0V VDD e 15V, VIN e 15V VIL VIH 1.5 3.0 4.0 1.5 3.0 4.0 V V V b 0.3 b 10 b 5 b 0.3 b 1.0 0.3 10b5 0.3 1.0 mA mA AC Electrical Characteristics* All types CL e 50 pF, TA e 25§ C, tr e tf e 20 ns unless otherwise specified Typ Max Units tTHL, tTLH Symbol Transition Times Parameter VDD e 5V VDD e 10V VDD e 15V Conditions Min 100 50 40 200 100 80 ns ns ns tPLH, tPHL Propagation Delay Times VDD e 5V VDD e 10V VDD e 15V 550 225 150 1100 450 300 ns ns ns tPLH, tPHL Inhibit Propagation Delay Times VDD e 5V VDD e 10V VDD e 15V 400 150 100 800 300 200 ns ns ns tSU Setup Time VDD e 5V VDD e 10V VDD e 15V 125 50 38 250 100 75 ns ns ns tWH Strobe Pulse Width VDD e 5V VDD e 10V VDD e 15V 175 50 38 350 100 75 ns ns ns CPD Power Dissipation Capacitance Per Package (Note 5) 150 CIN Input Capacitance Any Input (Note 4) 5 pF 7.5 pF *AC Parameters are guaranteed by DC correlated testing. Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for actual device operation. Note 2: VSS e 0V unless otherwise specified. Note 3: IOH and IOL are tested one output at a time. Note 4: Capacitance is guaranteed by periodic testing. Note 5: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see 54C and 74C Family Characteristics application note, AN-90. 3 Truth Table Decode Truth Table (Strobe e 1) Data Inputs D C B A Selected Output CD4514 e Logic ‘‘1’’ CD4515 e Logic ‘‘0’’ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 S0 S1 S2 S3 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 S4 S5 S6 S7 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 S8 S9 S10 S11 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 S12 S13 S14 S15 1 X X X X All Outputs e 0, CD4514 All Outputs e 1, CD4515 Inhibit X e Don’t Care AC Test Circuit and Switching Time Waveforms TL/F/5994 – 4 TL/F/5994 – 3 FIGURE 1 4 Applications 8 times faster than the shift frequency of the input registers, the most significant bit (MSB) from each register could be selected for transfer to the data bus. Therefore, all of the most significant bits from all of the registers can be transferred to the data bus before the next most significant bit is presented for transfer by the input registers. Information from the TRI-STATE bus is redistributed by the CD4514B 4-bit latch/decoder. Using the 4-bit address, INA – IND, the information on the inhibit line can be transferred to the addressed output line to the desired output registers, A – P. This distribution of data bits to the output registers can be made in many complex patterns. For example, all of the most significant bits from the input registers can be routed into output register A, all of the next most significant bits into register B, etc. In this way horizontal, vertical, or other methods of data slicing can be implemented. Two CD4512 8-channel data selectors are used here with the CD4514B 4-bit latch/decoder to effect a complex data routing system. A total of 16 inputs from data registers are selected and transferred via a TRI-STATEÉ data bus to a data distributor for rearrangement and entry into 16 output registers. In this way sequential data can be re-routed or intermixed according to patterns determined by data select and distribution inputs. Data is placed into the routing scheme via the 8 inputs on both CD4512 data selectors. One register is assigned to each input. The signals on A0, A1 and A2 choose 1-of-8 inputs for transfer out to the TRI-STATE data bus. A fourth signal, labelled Dis, disables one of the CD4512 selectors, assuring transfer of data from only one register. In addition to a choice of input registers, 1–16, the rate of transfer of the sequential information can also be varied. That is, if the CD4512 were addressed at a rate that is TL/F/5994 – 5 5 CD4514BM/CD4514BC, CD4515BM/CD4515BC 4-Bit Latched/4-to-16 Line Decoders Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number CD4514BMJ, CD4514BCJ, CD4515BMJ or CD4515BCJ NS Package Number J24A Molded Dual-In-Line Package (N) Order Number CD4514BMN, CD4514BCN, CD4515BMN or CD4515BCN NS Package Number N24A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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