NSC LM2686

LM2686
Regulated Switched Capacitor Voltage Converter
General Description
Features
The LM2686 CMOS charge-pump voltage converter operates as an input voltage doubler and a +5V regulator for an
input voltage in the range of +2.85V to +6.5V. Three low cost
capacitors are used in this circuit to provide up to 50mA of
output current at +5.0V ( ± 5%). The LM2686 operates at a
130 kHz switching frequency to reduce output resistance
and voltage ripple. With an operating current of only 450µA
(operating efficiency greater than 80% with most loads) and
6.0µA typical shutdown current, the LM2686 is ideal for use
in battery powered systems. The device is in a small 14-pin
TSSOP package.
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+5V regulated output
Doubles input supply voltage
TSSOP 14 package
80% typical conversion efficiency at 25mA
Input voltage range of 2.85V to 6.5V
Independent shutdown control pins
Applications
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Cellular phones
Pagers
PDAs
Handheld Instrumentation
3.3V to 5V Voltage Conversion Applications
Typical Application and Connection Diagram
DS101141-2
14-Pin TSSOP
DS101141-1
Ordering Information
Order Number
Package Type
NSC Package
Drawing
Supplied As
LM2686MTC
TSSOP-14
MTC14
94 Units, Rail
LM2686MTCX
TSSOP-14
MTC14
2.5k Units, Tape and Reel
© 1999 National Semiconductor Corporation
DS101141
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LM2686 Regulated Switched Capacitor Voltage Converter
November 1999
LM2686
Pin Description
Pin No.
Name
1
VIN*
2
GND**
Power supply ground.
3
GND**
Power supply ground.
4
GND**
Power supply ground.
5
CE
6
Function
Power supply input voltage.
Chip enable input. This pin is high for normal operation and low for shutdown and VPSW
load disconnect.
SD
Shutdown input. This pin is low for normal operation and high for shutdown and VPSW
load disconnect.
7
VIN*
Power supply input voltage.
8
NC
No connection.
9
NC
No connection.
10
V05
Regulated +5V output.
11
VPSW
V05 output connected through a series switch, PSW.
12
VDBL
Output of doubled input voltage.
13
C1+
The positive terminal of doubling charge-pump capacitor, C1.
14
C1−
The negative terminal of doubling charge-pump capacitor, C1.
* All VIN pins, pin 1 and pin 7 must be tied together for proper operation.
** All ground pins, pin 2, pin 3 and pin 4 must be tied together for proper operation.
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2
TJMAX (Note 3)
θJA (Note 3)
Supply Voltage (VIN to GND)
SD, CE
6.8V
(GND − 0.3V) to
(VIn + 0.3V)
V05 Continuous Output Current
Indefinite
Continuous Power Dissipation (TA
= 25˚C) (Note 3)
600mW
Operating Ambient Temp. Range
−40˚C to 85˚C
Operating Junction Temperature
Range
−40˚C to 125˚C
Storage Temp. Range
−65˚C to 150˚C
Lead Temp. (Soldering, 10 sec.)
80mA
V05 Short-Circuit Duration to GND
(Note 2)
150˚C
140˚C/W
300˚C
ESD Rating (Note 4)
2kV
Electrical Characteristics
Limits with standard typeface apply for TJ = 25˚C, and limits in boldface type apply over the full temperature range. Unless
otherwise specified VIN = 3.6V, C1 = C3 = 2.2µF. C2 = 4.7µF. (Note 5)
Symbol
Parameter
Conditions
V+
Supply Voltage
IQ
Supply Current
ISD
Shutdown Supply Current
VSD
Shutdown Pin Input Voltage for
CE, SD
Logic Input Low @ 6.5V
Output Current at V05
2.85V < VIN < 6.5V
IL (+5V)
No Load
VIN = 6.5V
Logic Input High @ 6.5V
FSW
Switch Frequency
PEFF
Average Power Efficiency at V05
2.85V < VIN < 6.5V
IL = 25mA to GND
Output Regulation
1mA < IL < 50mA, VIN = 6.5V
(Note 6)
1mA < IL < 50mA, VIN = 6.5V
(Note 6)
V05
GLINE
GLOAD
RSW
Line Regulation
Min
Typ
2.85
Max
Units
6.5
V
450
950
µA
6
30
µA
2.4
V
0.8
50
mA
180
kHz
85
130
4.848
5.05
5.252
V
4.797
5.05
5.303
V
%
82
2.85V < VIN < 3.6V
0.25
3.6V < VIN < 6.5V
0.05
Load Regulation
1mA < IL < 50mA, VIN = 6.5V
0.3
Series Switch Resistance from
V05 to VPSW
VIN > 2.85V
5.0
%/V
%
1.0
Ω
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: V05 may be shorted to GND without damage. For temperature above 85˚C, V05 must not be shorted to GND or device may be damaged.
Note 3: The maximum allowable power dissipation is calculated by using PDMAX = (TJMAX — TA)/θJA, where TJMAX is the maximum junction temperature, TAis the
ambient temperature and θJA is the junction-to-ambient thermal resistance of the specified package.
Note 4: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.
Note 5: In the typical operating circuit, capacitors C1 and C3 are 2.2µF, 0.3Ω maximum ESR capacitors. Capacitors with higher ESR will increase output resistance,
reduce output voltage and efficiency.
Note 6: The 50mA maximum current assumes no current is drawn from VDBL pin. See Voltage Doubler section in the Detailed Device Description.
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LM2686
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
LM2686
Typical Performance Characteristics
Supply Current vs Input Voltage
Unless otherwise specified, TA = 25˚C, VIN = 3.6V.
Supply Current vs Temperature
DS101141-6
Efficiency vs Load Current (VIN =
3.0V)
DS101141-7
DS101141-8
Output Resistance (VDBL) vs.
Temperature (VIN = 3.6V)
Switch Frequency vs. Temperature
(VIN = 3.6V)
Line Transient Response (with 5mA
Load)
DS101141-14
DS101141-12
V05 Load Transient Response
DS101141-13
VPSW Response to CE
(with 5mA Load)
A: INPUT VOLTAGE: VIN = 3.2V to 6.0V, 5V/div
B: OUTPUT VOLTAGE: VPSW: 100mV/div
V05 Response to SD (with 5mA
Load)
DS101141-15
A: LOAD CURRENT: ILOAD = 5mA to 39.6mA,
10mA/div
B: OUTPUT VOLTAGE: V05: 10mV/div
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DS101141-17
A: CE INPUT: 5V/div
B: OUTPUT VOLTAGE: VPSW: 5V/div
4
DS101141-18
A: SD INPUT: 5V/div
B: OUTPUT VOLTAGE: 5V/div
LM2686
Typical Performance Characteristics
Unless otherwise specified, TA = 25˚C, VIN =
3.6V. (Continued)
Output Voltage (V05) vs. Load
Current
(VIN = 3.6V)
Output Resistance (VDBL) vs. Input
Voltage
V05 Voltage vs. Input Voltage
DS101141-19
DS101141-11
DS101141-9
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LM2686
Detailed Device Description
DS101141-3
FIGURE 1. Functional Block Diagram
+5 LDO Regulator
VDBL is the input to an LDO regulator that regulates it to a +5
output voltage at V05. VPSW is tied to V05 through a series
switch PSW. The LDO output capacitor (4.7µF Tantalum)
may be connected to either V05 or VPSW.
The LM2686 CMOS charge pump voltage converter operates as an input voltage doubler, +5V regulator for an input
voltage in the range of +2.85V to +6.5V. It delivers maximum
load currents of 50mA for the regulated +5V, with an operating current of only 450µA. It also has a typical shutdown current of 6µA. All these performance qualities make the
LM2686 an ideal device for battery powered systems.
The LM2686 has two main functional blocks: a voltage doubler and a low dropout (LDO) regulator. Figure 1 shows the
LM2686 functional block diagram.
Shutdown and Load Disconnect
In addition to the nominal charge pump and regulator functions, the LM2686 features shutdown and load disconnect
circuitry. CE (chip enable) and SD (shutdown positive) perform the same task with opposite input polarities. When CE
is low or SD is high, all circuit blocks are disabled and V05
falls to ground potential. This is the same result as when the
die temperature exceeds 150˚C, and the device’s internal
thermal shutdown is triggered.
The LM2686 incorporates a low impedance switch tied to the
V05 output, because some special applications require load
disconnect and this is achievable via the switch. Switch PSW
connects V05 to VPSW. In normal operation, this switch is
closed, allowing 5V loads to be tied to either V05 or VPSW.
Forcing CE low or SD high opens the PSW.
Voltage Doubler
The voltage doubler ties directly to VIN and doubles the input
voltage in the range from +2.85V to +5.4V up to 5.7V to
10.8V at the VDBL pin. For VIN above 5.4V, the doubler shuts
off and the input voltage is passed directly to VDBL via an internal power switch.
The doubler contains four large CMOS switches which are
switched in a sequence to double the input supply voltage.
Figure 2 illustrates the voltage conversion scheme. When S2
and S4 are closed, C1 charges to the supply voltage VIN.
During this time interval, switches S1 and S3 are open. In the
next time interval, S2 and S4 are opened at the same time,
S1 and S3 are closed, the sum of the input voltage VIN and
the voltage across C1 gives the 2VIn and the voltage across
C2 gives the 2VIN at VDBL output. VDBL supplies the LDO
regulator. It is recommended not to load VDBL when V05 has
a load of 50mA. For proper operation, the sum of VDBL and
V05 loads must not be more than 50mA.
Application Information
Capacitor Selection
The output resistance and ripple voltage are dependent on
the capacitance and ESR values of the external capacitors.
Voltage Doubler External Capacitors
The selection of capacitors are based on the specifications
of the dropout voltage (which equals IOUT ROUT), the output
voltage ripple, and the converter efficiency.
where RSW is the sum of the ON resistance of the internal
MOSFET switches as shown in Figure 2.
The peak-to-peak output voltage ripple is determined by the
oscillator frequency, the capacitance and ESR of the capacitor C3.
DS101141-4
FIGURE 2. Voltage Doubler Principle
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LM2686
Application Information
(Continued)
High capacitance (2.2µF to higher), low ESR capacitors can
reduce the output resistance and the voltage ripple.
where IQ(V+) is the quiescent power loss of the IC device,
and I2LR is the conversion loss associated with the switch
on-resistance, the two external capacitors and their ESRs.
Low ESR capacitors (table to be referenced) are recommended to maximize efficiency, reduce the output voltage
drop and voltage ripple.
+5 LDO Regulator External Capacitors
The voltage doubler output capacitor, C3, serves as the input
capacitor of the 5 LDO regulator. The output capacitor C4,
must meet the requirement for minimum amount of capacitance and appropriate ESR (Equivalent Serving Resistance)
for proper operations. The ESR value must remain within the
regions of stability as shown in Figure 3, Figure 4 and Figure
5 to ensure output’s stability. A minimum capacitance of 1µF
is required at the output. This can be increased without limit,
but a 4.7µF tantalum capacitor is recommended for loads
ranging upto the maximum specification. In lighter loads of
less or equal to 10mA, ceramic capacitor of at least 1µF and
ESR in the milliohms can be used. This has to be connected
to VPSW pin instead of the V05 pin.
Any output capacitor used should have a good tolerance
over temperature for capacitance and ESR values. The
larger the capacitor, with ESR within the stable region, the
better the stability and noise performance.
DS101141-25
FIGURE 3. ESR Curve for COUT = 2.2µF
DS101141-26
FIGURE 4. ESR Curve for COUT = 4.7µF
DS101141-27
FIGURE 5. ESR Curve for COUT = 10µF
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LM2686 Regulated Switched Capacitor Voltage Converter
Physical Dimensions
inches (millimeters) unless otherwise noted
TSSOP-14 Package
14-Lead Thin Shrink Small-Outline Package
For Ordering, Refer to Ordering Information Table
NS Package Number MTC14
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