a FEATURES Push-Pull Charge Pump Doubler Reduces Output Ripple +3.0 V to +3.6 V Operation V OUT > +5.4 V @ 320 mA Maximum Load Output Impedance, RTOTAL ≤ 1.66 V Shutdown Capability Overvoltage Protection: VIN > +4 V Operating Temperature Range: –208C to +858C Thermally Enhanced 16-Lead TSSOP Package 320 mA Switched Capacitor Voltage Doubler ADP3610 FUNCTIONAL BLOCK DIAGRAM CP1 CM1 CP2 CM2 VOUT VIN GND APPLICATIONS High Current Doublers LCD Panels Cellular Phones Inductorless Boost Converters DRV DRV ADP3610 DRIVE LOGIC OVERVOLTAGE PROTECTION 1MHz OSC SD GENERAL DESCRIPTION The ADP3610 is a push-pull switched-capacitor converter voltage doubler. The term “push-pull” refers to two charge pumps working in parallel and in opposing phase to deliver charge to support the output voltage. When one capacitor is pumping charge to the output, the other is recharging. This technique minimizes voltage loss and output voltage ripple. The converter accommodates input voltages from +3 V to +3.6 V and can provide 320 mA using 2.2 µF MLCC pump capacitors. Converter operation can be enabled or disabled simply by an input signal. The package is enhanced with Analog Devices’ proprietary Thermal Coastline feature, which allows up to 980 mW of power dissipation at room temperature. The exceptionally thin TSSOP-16 package and the requirement of only capacitors (no inductors) to support the converter operation allows slim designs, e.g., for TFT or LCD display panels. CP1 2.2mF VOUT VIN CIN 1mF VIN CO 1mF VOUT ADP3610 GND SD CP2 2.2mF Figure 1. Typical Application Circuit REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 (–208C ≤ TA ≤ +858C, VIN = +3.3 V, CP1 = CP2 = 2.2 mF, CO = 1 mF, SD = GND, ADP3610–SPECIFICATIONS unless otherwise noted) Parameter Symbol OPERATING SUPPLY RANGE VIN QUIESCENT CURRENT IQ INPUT OVP THRESHOLD 1, 2, 3 Condition Min Typ 3.0 SD = VIN SD = GND, IL = 0 mA 0.3 8.6 VOVP Max Units 3.6 V 10 µA mA 4 4 TOTAL OUTPUT IMPEDANCE RTOTAL IO = 0 mA to 320 mA 1 OUTPUT VOLTAGE VO OUTPUT CURRENT IO 320 OUTPUT SWITCHING FREQUENCY fSW 400 SD INPUT Logic Input High Input Current Logic Input Low Input Current VIH IIH VIL IIL 2.0 IO = 240 mA, VIN = +3 V IO = 320 mA, VIN = +3 V IO = 240 mA, VIN = +3.3 V IO = 320 mA, VIN = +3.3 V 5.6 5.47 6.2 6.07 V 1.66 5.75 5.65 6.35 6.27 Ω V V V V mA 560 650 0.1 0.8 0.1 kHz V µA V µA NOTES 1 Capacitors in the test circuit are multilayer ceramic type. 2 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. 3 Junction temperature is influenced by ambient temperature, device mounting and heatsinking, and power dissipation which is a function of I/O voltages and load. 4 RTOTAL includes the switch resistance, and the equivalent series resistance of the 2.2 µF (X7R) MLCC pump capacitors. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS 1 ORDERING GUIDE Input Voltage (V+ to GND) . . . . . . . . . . . . . . . . . . . . +4.0 V Output Short Circuit to GND (<1 A) . . . . . . . . . . . . . . 60 sec Power Dissipation θJA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +102°C/W Operating Ambient Temperature Range . . . . –20°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering 10 sec) . . . . . . . +300°C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C Model Temperature Range Package Description Package Option ADP3610ARU –20°C to +85°C Thin Shrink Small RU-16 Outline Package (TSSOP-16) NOTES 1 This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. 2 θJA is specified for worst case conditions with device soldered on a FR-4, 1 oz. copper clad four layer circuit board. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3610 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –2– WARNING! ESD SENSITIVE DEVICE REV. A ADP3610 Table I. Other Members of ADP36xx Family 1 PIN FUNCTION DESCRIPTIONS Model Output Current Package Options2 Comments ADP3603 50 mA SO-8 Nom –3 V ± 3% Inverter ADP3604 120 mA SO-8 Nom –3 V ± 3% Inverter ADP3605-3 120 mA SO-8, Nom –3 V ± 5% Inverter TSSOP-14 ADP3607-5 50 mA SO-8 Nom 5 V ± 5% Boost ADP3607 SO-8 Adjustable ± 5% Boost 50 mA NOTES 1 See individual data sheets for detailed ordering information. 2 SO = Small Outline; TSSOP = Thin Shrink Small Outline Package. Pin Name Function 1, 8, 9, 15, 16 VIN 2 SD 3 4, 5, 6, 13 7 10 11, 12 CM1 GND CM2 CP2 VOUT 14 CP1 Table II. Alternative Capacitor Technologies Type Life High Freq Aluminum Electrolytic Capacitor Fair Multilayer Ceramic Capacitor Solid Tantalum Capacitor OS-CON Capacitor Temp Size Cost PIN CONFIGURATION Fair Long Good Fair Poor* Small Fair Low High Above Avg Above Avg Avg Good Avg Good Avg Good Avg Avg Manufacturer Capacitor Capacitor Type Sprague 672D, 673D, 674D, 678D 675D, 173D, 199D PF and PL TDC and TDL MLCC GRM Aluminum Electrolytic REV. A 16 VIN SD 2 15 VIN CM1 3 14 CP1 ADP3610 GND TOP VIEW GND 5 (Not to Scale) 12 VOUT Table III. Recommended Capacitor Manufacturers Nichicon Mallory TOKIN MuRata VIN 1 GND 4 *Refer to capacitor manufacturer’s data sheet for operation below 0°C. Sprague Input Voltage. Pins 1, 8, 9, 15 and 16 must be connected together for proper operation. Shutdown. A logic low input allows normal operation. A logic high input shuts the device off. Pump Capacitor C1 Negative Input Ground. Pins 4, 5, 6, and 13 must be connected together for proper operation. Pump Capacitor C2 Negative Input Pump Capacitor C2 Positive Input Output Voltage. Pins 11 and 12 must be connected together for proper operation. Pump Capacitor C1 Positive Input Tantalum Aluminum Electrolytic Tantalum Multilayer Ceramic Multilayer Ceramic –3– 13 GND 6 11 VOUT CM2 7 10 CP2 VIN 8 9 VIN ADP3610 –Typical Performance Characteristics 9.7 6.62 6.59 9.5 VIN = +3.6V 9.3 565 560 555 9.1 8.9 8.7 VIN = +3.3V 8.5 8.3 8.1 2.8 2.9 3.0 3.1 3.2 3.3 3.4 SUPPLY VOLTAGE – Volts 560 VIN = +3.6V 6.35 VIN = +3.3V IL = 320mA 6.32 6.29 5 20 35 50 TEMPERATURE – 8C 65 6.23 –20 –10 80 85 5 20 35 50 TEMPERATURE – 8C 65 80 85 Figure 4. Output Voltage vs. Temperature, VIN = +3.3 V 6.1 0.4 VIN = +3.6V VIN = +3.3V 0.2 VIN = +3.0V 550 545 –20 –10 5 20 35 50 TEMPERATURE – 8C 65 0 –20 –10 80 85 Figure 5. Oscillator Frequency vs. Temperature 6.7 7.3 6.6 7.2 6.5 6.4 6.3 100 200 300 LOAD CURRENT – mA 400 Figure 8. Output Voltage vs. Load Current for VIN = +3.3 V 5 20 35 50 TEMPERATURE – 8C 65 80 85 Figure 6. Supply Current in Shutdown Mode vs. Temperature OUTPUT VOLTAGE – Volts OUTPUT VOLTAGE – Volts 6.38 OUTPUT VOLTAGE – Volts SUPPLY CURRENT – mA OSCILLATOR FREQUENCY – kHz VIN = +3.3V 0 6.41 VIN = +3.0V 565 6.2 6.44 0.6 575 555 6.47 Figure 3. Supply Current vs. Temperature Figure 2. Oscillator Frequency vs. Supply Voltage 570 6.50 6.26 7.7 –20 –10 3.5 3.6 6.53 VIN = +3.0V 7.9 550 2.7 VIN = +3.3V IL = 0mA 6.56 OUTPUT VOLTAGE – Volts IL = 0mA SUPPLY CURRENT – mA OSCILLATOR FREQUENCY – kHz 570 6.0 5.9 5.8 5.7 5.6 0 100 200 300 LOAD CURRENT – mA 400 Figure 7. Output Voltage vs. Load Current for VIN = +3.0 V␣ 7.1 7.0 6.9 6.8 0 100 200 300 LOAD CURRENT – mA 400 Figure 9. Output Voltage vs. Load Current for VIN = +3.6 V –4– REV. A ADP3610 100 80 IL = 320mA EFFICIENCY – % QUIESCENT CURRENT – IQ (mA) 20 15 10 IL = 0mA 5 3.0 60 40 20 5 3.2 3.4 3.6 0 VIN – Volts Figure 10. Quiescent Current vs. Input Voltage 80 160 240 LOAD CURRENT – mA 320 Figure 11. Efficiency vs. Load Current, VIN = +3.3 V 10V VOUT 5V VO 0V SD VIN Figure 12. Output Voltage Ripple (IO = 320 mA, CP1 = CP2 = 2.2 µF, CO = 1 µF) REV. A Figure 13. Start-Up Under Full Load (VIN = +3.6 V, IO = 320 mA) –5– Figure 14. Shutdown at Full Load (VIN = +3.3 V, IO = 320 mA) ADP3610 THEORY OF OPERATION PHASE 1 The ADP3610 is an unregulated switched capacitor voltage doubler that provides an output voltage greater than 5.4 V from a +3.0 V to +3.6 V input. The unique push-pull voltage doubling architecture allows it to deliver a maximum of 320 mA output current. A typical application circuit, as shown in Figure 20, requires five small external capacitors. The ADP3610 has an internal 1 MHz oscillator that is divided by two and used to generate two nonoverlapping phase clocks. VIN f S1 CP1 S4 f S5 f f VIN C + CP2 S6 A f S1 S3 A VIN B VOUT f A f A f (a) B f B VOUT + CP1 S4 f S2 f S7 B B f A f A + f S4 A S7 B S8 PHASE 2 S2 B S5 f f + The basic principle behind a conventional switched capacitor voltage doubler is shown in Figure 15. During phase one, S1 and S2 are ON, charging the pump capacitor to the input voltage. In phase two, switches S1 and S2 are turned OFF and S3 and S4 are turned ON. During phase two, the pump capacitor is placed in series with the input voltage, thereby charging the output capacitor to the sum of input voltage and pump capacitor voltage, resulting in voltage doubling at the output terminal. S1 S3 A CP2 B VOUT f S8 A + f A S6 f B P S3 f (b) f S2 B f A B Figure 17. (a) Phase 1 “Push” Charging␣ (b) Phase 2 “Pull” Charging PHASE PHASE 1 2 Overvoltage Protection Figure 15. Conventional Voltage Doubler Configuration The input voltage is scaled with a resistor network and compared to the bandgap reference voltage of 1.25 V by a 50 mV hysteresis comparator. When the input voltage exceeds 4.0 V, the overvoltage protection signal stops the oscillator. The ADP3610 has two sets of switched capacitor voltage doublers connected in parallel delivering charge to the output as shown in Figure 16. S1 VIN f S3 A f B VIN VOUT + S4 f S5 f B ADP3610 R1 CP1 S2 f S7 f 50mV A OSC B A BANDGAP = 1.25V + CP2 S8 f A EN R2 S6 f B Figure 18. Overvoltage Protection Shutdown Mode Figure 16. Switch Configuration Charging the Pump Capacitor The ADP3610’s output can be disabled by pulling the SD pin high to a TTL/CMOS logic compatible level which will stop the internal oscillator. In shutdown mode, all analog circuitry including overvoltage protection is shut off, thereby reducing the quiescent current to 10 µA typical. Applying a digital low level or tying the SD pin to ground will turn on the output. If the shutdown feature is not used, SD pin should be tied to the ground pin. The output voltage in shutdown mode is approximately VIN – 0.6 V. The two voltage doublers run in opposite phases, i.e., when one pump capacitor is being charged, the other is charging the output, as shown in Figure 17. In this architecture, one of the pump capacitors is always delivering charge to the output. As a result, output ripple is at a frequency that is double the switching frequency. This allows the use of a smaller output capacitor compared to a conventional voltage doubler. –6– REV. A ADP3610 APPLICATION INFORMATION Capacitor Selection Pump Capacitor The ADP3610 alternately charges CP to the input voltage when it is switched in parallel with the input supply, and then transfers charge to CO when it is switched in series with the input and connected to the output. The ADP3610’s high internal oscillator frequency permits the use of small capacitors for both the pump and the output capacitors. For a given load current, factors affecting the output voltage performance are: • Pump (CP) and output (CO) capacitance 10 • ESR of the CP and CO When selecting the capacitors, keep in mind that not all manufacturers guarantee capacitor ESR in the range required by the circuit. In general, the capacitor’s ESR is inversely proportional to its physical size, so larger capacitance values and higher voltage ratings tend to reduce ESR. Since the ESR is also a function of the operating frequency, when selecting a capacitor, make sure its value is rated at the circuit’s operating frequency. Another factor affecting capacitor performance is temperature. Figure 19 illustrates the temperature effect on various capacitors. Aluminium electrolytic capacitors lose their capacitance at low temperatures and their ESR increases considerably. Some capacitor technologies do offer improved performance over temperature; for example, certain tantalum capacitors provide good low temperature ESR but at a higher cost. Table II provides the ratings for different types of capacitor technologies to help the designer select the right capacitors for the application. The exact values of CIN and CO are not critical. However, low ESR capacitors such as solid tantalum and multilayer ceramic capacitors are recommended to minimize voltage loss at high currents. Table III shows a partial list of the recommended low ESR capacitor manufacturers. ALUMINUM CERAMIC 1.0 ESR – V TANTALUM ORGANIC SEMIC TANTALUM 0.1 ORGANIC SEMIC CERAMIC ALUMINUM 0.01 –50 0 50 100 TEMPERATURE – 8C Figure 19. ESR vs. Temperature Power Dissipation The power dissipation of the ADP3610 circuit must be limited so the junction temperature of the device does not exceed the maximum junction temperature rating. Total power dissipation is calculated as follows: Input Capacitor PD = (2 VIN – VOUT) IOUT + VIN (IS) A small 1 µF input bypass capacitor, preferably with low ESR, such as tantalum or multilayer ceramic, is recommended to reduce noise and supply transients and supply part of the peak input current drawn by the ADP3610. A large capacitor is recommended if the input supply is connected to the ADP3610 through long leads, or if the pulse current drawn by the device might affect other circuitry through supply coupling. Where IOUT and IS are output current and supply current, VIN and VOUT are input and output voltages respectively. For example: assuming worst case conditions, VIN = 3 V, VOUT = 5.62 V, IOUT = 320 mA and IS = 14 mA. Calculated device power dissipation is: PD ≈ (6 V – 5.62 V) × 0.32 + 3 × (0.014) = 163.6 mW Output Capacitor The output capacitor (CO) is alternately charged to the sum of input voltage and pump capacitor voltage when CP is switched in series with CO. The ESR of CO introduces steps in the VOUT waveform whenever the charge pump charges CO, which tends to increase VOUT ripple. Thus, ceramic or tantalum capacitors are recommended for CO to minimize ripple on the output. Note that as the capacitor value increases beyond the point where the dominant contribution to the output ripple is due to the ESR, no significant reduction in VOUT ripple is achieved by added capacitance. The proprietary thermal coastline package used in the ADP3610 has a thermal resistance of 102°C/W. Therefore, the rise in junction temperature for this application would be: TRISE = 0.164 W × 102°C/W = 16.7°C General Board Layout Guidelines Since the ADP3610’s internal switches turn on and off very fast, good PC board layout practices are critical to ensure optimal operation of the device. Improper layouts will result in poor load regulation, especially under heavy loads. Following these simple layout guidelines will improve output performance. Multiple smaller capacitors can be connected in parallel to yield lower ESR and potential cost savings. For lighter loads, proportionally smaller capacitors are required. To reduce high frequency noise, bypass the output with a 0.1 µF ceramic capacitor. 1. Use adequate ground and power traces or planes. 2. Use single point ground for device ground and input and output capacitor grounds. 3. Keep external components as close to the device as possible. 4. Use short traces from the input and output capacitors to the input and output pins respectively. 5. All multiple GND, VIN and VOUT pins must be connected together for proper operation. REV. A –7– ADP3610 SLOPE = RTOTAL = 6 – 5.62 = 1.18V 0.32 Unregulated Voltage Doubler Figure 20 shows a typical application for the ADP3610 in unregulated voltage doubling mode. The inherent limit on the output voltage for a voltage doubler is two times the input voltage. However, due to the losses in the switches and ESR of capacitors, this scaling factor is somewhat reduced. Figure 21 shows the magnitude of unregulated output voltage as the load current is increased from 0 mA to 320 mA. This gives a measure of the equivalent resistance RTOTAL. RTOTAL is comprised of internal switch resistance and ESR of the capacitors. 6.0 OUTPUT VOLTAGE – Volts (5.62, 320 mA) CP1 2.2mF CIN1 1mF INPUT VIN = 3.3V ADP3610 VIN 2 SD 3 CM1 4 GND GND 13 5 GND VOUT 12 GND VOUT 11 7 CM2 CP2 10 6 CIN2 1mF 8 3.0 1.5 0 VIN 16 1 4.5 VIN 15 0 100 200 LOAD CURRENT – mA VIN = 3 V 300 400 Figure 21. Load Regulation CP1 14 OUTPUT VO = 6.2V CO @320mA 1mF VIN 9 VIN CP2 2.2mF Figure 20. Unregulated Voltage Doubler –8– REV. A ADP3610 TFT LCD System Design The ADP3610 is very useful for applications like notebook LCD displays which require a low profile solution. Figure 22 shows a typical LCD display application. A TFT LCD display requires +5 V main voltage and +17 V and –5 V auxiliary voltages. The ADP3610 doubles the input voltage, which is then fed through a discrete linear regulator to generate +5 V. The main voltage is also fed to the ADP3605, which inverts the input voltage to generate –5 V. The CP+ node of the ADP3605 pump capacitor is fed to a diode-capacitor ladder network to quadruple the main voltage, i.e., 4 × VMAIN – 6 × VDIODE ≈ 17 V. CP1 2.2mF ADP3610 VIN = 3.0V TO 3.6V VIN 2 SD 3 CM1 4 GND GND 13 5 GND VOUT 12 1mF 1mF VIN 16 1 VIN 15 CP1 14 6 GND VOUT 11 7 CM2 CP2 10 8 VIN VMAIN = 5V @ 150mA 1mF 1kV 0.1mF 25.5kV 1mF TL431 VIN 9 24.9kV 470V CP2 2.2mF VGH = 17V @ 3mA 2.2mF 2.2mF 1mF 1mF ADP3605 CP+ VIN GND VOUT 1mF 2.2mF CP– SD NC 2.2mF VGL = –5V @ 30mA VSNS NC = NO CONNECT Figure 22. LCD Display Application REV. A –9– 1mF 1mF ADP3610 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead Thin Shrink Small Outline Package (TSSOP) (RU-16) 9 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) 16 C3442a–0–7/99 0.201 (5.10) 0.193 (4.90) 1 8 PIN 1 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 8° 0° 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) PRINTED IN U.S.A. 0.0256 SEATING (0.65) PLANE BSC 0.0433 (1.10) MAX –10– REV. A