NSC DS34RT5110SQE

DS34RT5110
May 11, 2009
DVI, HDMI Retimer with Input Equalization and Output DeEmphasis
General Description
Features
The DS34RT5110 is a 10.2 Gbps (3 x 3.4 Gbps) high performance re-clocking device that supports 3 Transition Minimized Differential Signaling (TMDS®) data channels and a
single clock channel over DVI™ v1.0, and HDMI™ v1.3a data
rates up to 3.4 Gbps for each data channel. The device incorporates a configurable receive equalizer, a clock and data
recovery (CDR) circuit and a de-emphasis driver on each data
channel. The clock channel feeds a high-performance phaselocked loop (PLL) that regenerates a low jitter output clock for
data recovery.
The DS34RT5110 equalizes and retimes greater than 25 meters 28 AWG of HDMI cable for 1080p resolution with 12 bit
deep color depth (2.25 Gbps), to a low jitter version of the
clock and data signal outputs, reducing both deterministic and
random jitter. Several devices can be cascaded for long links
without degrading signal fidelity. Obtaining total jitter is 0.09
UI or less over the supported data rates. This low level of output jitter provides system designers with extra margin and
flexibility when working with stringent timing budgets.
The transmitter supports configurable transmit de-emphasis
so the output can be optimized for driving additional lengths
of cables or FR4 traces.
■ Optimized for HDMI/DVI repeater applications
■ TMDS compatible inputs with configurable receive
equalization supporting data rates up to 3.4 Gbps
■ TMDS compatible outputs with configurable transmit deemphasis
■ Dedicated CDR on each data channel reduces jitter
■
■
■
■
■
■
■
■
■
transfer, enabling multiple devices to be cascaded without
impairing signal fidelity
Capable of multi-hop extension of HDMI/DVI applications
at data rates between 250 Mbps and 3.4 Gbps
Resistor adjustable differential output voltage for AC
coupled Cat5e and Cat6 extension applications
2 equalizer settings for a wide range of cable reaches at
different data rates
Total Output Jitter of 0.09 UI at 2.25 Gbps
Total Output Jitter of 0.10 UI at 3.4 Gbps
DVI 1.0 and HDMI v1.3a compatible TMDS source and
sink interface
7 mm x 7 mm 48 pin LLP package
>8 kV HBM ESD protection
0 °C to +70 °C operating temperature
Applications
■ Repeater Applications
— Digital Routers
— HDMI / DVI Extender Multi-hops
■ Source Applications
— Video Cards
— Blu-ray DVD Players
— Game Consoles
■ Sink Applications
— High Definition Displays
— Projectors
Application Diagram
30087353
© 2009 National Semiconductor Corporation
300873
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DS34RT5110 DVI, HDMI Retimer with Input Equalization and Output De-Emphasis
PRELIMINARY
DS34RT5110
Pin Descriptions
Pin Name
Pin Number
I/O, Type
Description
High Speed Differential I/O
C_IN−
C_IN+
1
2
I, CML
Inverting and non-inverting TMDS Clock inputs to the equalizer. An on-chip 50 Ω terminating
resistor connects C_IN+ to VDD and C_IN- to VDD.
D_IN0−
D_IN0+
4
5
I, CML
Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50 Ω terminating
resistor connects D_IN0+ to VDD and D_IN0- to VDD.
D_IN1−
D_IN1+
8
9
I, CML
Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50 Ω terminating
resistor connects D_IN1+ to VDD and D_IN1- to VDD.
D_IN2−
D_IN2+
11
12
I, CML
Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50 Ω terminating
resistor connects D_IN2+ to VDD and D_IN2- to VDD.
C_OUTC_OUT+
36
35
O, CML
Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
D_OUT0−
D_OUT0+
33
32
O, CML
Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
D_OUT1–
D_OUT1+
29
28
O, CML
Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
D_OUT2−
D_OUT2+
26
25
O, CML
Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
Equalization Control
EQ2
EQ1
EQ0
37
38
39
I, LVCMOS EQ2, EQ1 and EQ0 select the equalizer boost level for EQ channels. Internally pulled LOW
as default. See Table 1.
De-Emphasis Control
DE1
DE0
42
43
I,
LVCMOS
DE1, DE0 select the DE-emphasis level for output drivers. Internally pulled low as default.
Refer to Table 2.
BYPASS
47
I,
LVCMOS
Reclocker enable control. Internally pulled low as default.
H = Reclock and De-Emphasis function is bypassed.
L = Normal operation.
EN
44
I, LVCMOS Enable Output Drivers. Internally pulled HIGH as default.
H = normal operation (enabled).
L = standby mode.
MODE
21
I, LVCMOS Clock channel mode control. Internally pulled LOW as default.
H = Clock channel is bypassed.
L = Normal operation.
SD
45
O, LVCMOS Signal Detect Output pin.
H = signal detected on all channels.
L = no signal detected on one or more channels.
LOCK
14
O, LVCMOS Lock Indicator Output pin.
H = PLL is locked.
L = PLL is not locked.
VOD_CRL
48
I,
Analog
VOD control pin. Refer to Table 3. See Functional Description.
External resistance = 24 kΩ to GND, Output DC Coupled Application.
External resistance = 12 kΩ to GND, Output AC Coupled Application.
LFp
LFn
40
41
I,
Analog
Loop filter capacitor pins.
See Functional Description.
Device Control
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2
Pin Number
I/O, Type
Description
VDD
3, 6, 7,
10, 13,
15, 46
Power
VDD = 3.3 V ±5%. VDD pins should be tied to the VDD plane through a low inductance path.
A 0.1 µF bypass capacitor should be connected between each VDD pin to the GND planes.
See Power Supply Bypassing for additional details.
GND
22, 24,
27, 30,
31, 34
GND
Ground reference. GND should be tied to a solid ground plane through a low impedance
path.
DAP
GND
Ground reference. The exposed pad at the center of the package must be connected to the
ground plane.
Power
Exposed
DAP
Other
Reserv
16, 17,
18, 19,
20, 23
Note: I = Input, O = Output,
Reserved. Do not connect. Leave open.
IO =Input/Output,
Connection Diagram
30087352
TOP VIEW — Not to Scale
Ordering Information
NSID
Package
Tape & Reel QTY
Package Number
DS34RT5110SQE
48 Lead LLP
250
SQA48A
DS34RT5110SQ
48 Lead LLP
1,000
SQA48A
DS34RT5110SQX
48 Lead LLP
2,500
SQA48A
3
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DS34RT5110
Pin Name
DS34RT5110
Absolute Maximum Ratings (Note 1)
ESD Rating
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
HBM, 1.5 kΩ, 100 pF
Thermal Resistance
θJA, No Airflow
Supply Voltage (VDD)
LVCMOS Input Voltage
LVCMOS Output Voltage
CML Input/Output Voltage
Junction Temperature
Storage Temperature
Lead Temp. (Soldering, 5 sec.)
-0.5V to 4.0 V
-0.5V to (VDD+ 0.5) V
-0.5V to (VDD+ 0.5) V
-0.5V to (VDD+ 0.5) V
+125°C
-65°C to +150°C
+260°C
>8 kV
33°C/W
Recommended Operating
Conditions (Notes 3, 4)
Supply Voltage
(VDD to GND)
Supply Noise Tolerance
(100 Hz to 50 MHz)
Ambient Temperature
Min
3.135
Typ
3.3
Max
3.465
100
0
25
Units
V
mVp-p
+70
°C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. All parameters are guaranteed by test,
statistical analysis, or design unless otherwise specified. (Note 3)
Symbol
Parameter
Condition
Min
Typ
Max
Units
Power
P
Power Supply
Consumption
EN = H, Device Enabled
PRBS15 pattern, fCLK=340
MHz
RT= 50Ω to AVCC, Figure 2
1100
1250
mW
EN = L, Standby Mode
PRBS15 pattern, fCLK=340
MHz
RT= 50Ω to AVCC, Figure 2
850
1000
mW
LVCMOS / LVTTL DC Specifications
VIH
High Level Input
Voltage
2
VDD
V
VIL
Low Level Input
Voltage
GND
0.8
V
VOH
High Level Output
Voltage
IOH = -3 mA
VOL
Low Level Output
Voltage
IOL = 3 mA
IIH
2.4
VIN = VDD, EQ2, EQ1, EQ0,
DE1, DE0, BYPASS, MODE
Input High Current
pins (pull down)
VIN = VDD, EN pin (pull up)
IIL
V
Input Low Current
0.4
V
60
mA
-15
mA
VIN = 0 V, EQ2, EQ1, EQ0,
DE1, DE0, BYPASS, MODE
pins (pull down)
15
VIN = 0 V, EN pin (pull up)
μA
μA
-20
Signal Detect
SDH
Default Input signal level to
Signal Detect High assert SD pin
80
mVp-p
SDL
Default Input signal level to
deassert SD
20
mVp-p
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Signal Detect Low
4
Parameter
Condition
Min
Typ
Max
Unit
VTX
Input Voltage
Swing (Launch
Amplitude)
Measured differentially at
TPA, Figure 1, note 4
800
1000
1560
mVp-p
VICMDC
Input CommonMode Voltage
DC-Coupled requirement
Measured at TPB,
VINmin = 800mV,
VINmax = 1200mV, Figure 1
VDD-0.3
VDD-0.2
V
VIN
Input Voltage
Sensitivity
Measured differentially at
TPB, Figure 1
3.4 Gbps, Clock Pattern
150
1560
mVp-p
RIN
Input resistance
IN+ to VDD and IN- to VDD
40
60
Ohms
RLI
Differential output
return loss
100 MHz – 1125 MHz
VOFF
Standby Output
Voltage
Measured DC outputs at
TPC, RT = 50Ω when DUT
VDD is off with OUT+ and
OUT- terminated by RT=
50Ω to AVCC, Figure 2
VO
External resistor = 24 kΩ at
VOD_CRL pin.Measured
Differential Output
differentially with OUT+ and
voltage swing
OUT- terminated by
RT=50Ω to AVCC, Figure 2
VOCM
Output commonmode Voltage
Measured single-ended,
>1.65 Gbps, Figures 2, 3
tR, tF
Transition time
20% to 80% of differential
output voltage, measured
within 1” from output pins,
Figure 3
80
tCCSK
Inter Pair Data
Channel-toChannel Skew (all
3 data channels)
Difference in 50% crossing
between channels
3.4 Gbps, Clock Pattern
(Note 4)
2
tPPSK
Inter Pair Data
Channels ParttoPart Skew
Difference in 50% crossing
between channels of any two
devices
3.4 Gbps, Clock Pattern
50
ps
tDD
Data Channels
Latency
3.4 Gbps, Clock Pattern,
Figure 4
520
ps
tCD
Clock Channel
Latency
3.4 Gbps, Clock Pattern,
Figure 4
600
ps
SD to LOCK time
Figure 4
10
ms
fCLK
Clock Frequency
Clock Path
(Note 4)
25
340
MHz
bR
Bit Rate
Data Paths
(Note 4)
0.25
3.4
Gbps
CML Inputs
50
10
dB
CML Outputs
AVCC - 10
AVCC+ 10
mV
800
1200
mVp-p
AVCC- 0.35
AVCC- 0.20
V
ps
3
ps
LVCMOS Outputs
tSL
Bit Rate
5
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DS34RT5110
Symbol
DS34RT5110
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Data Channel Random Jitter
RJ
Random Jitter
(Notes 4, 5, 6)
3
psrms
Data Channel CDR Jitter Generation
TROJ1
Data Paths, measured at
Total Output Jitter
TPC PRBS7, EQ [2:0] = 000
0.25 Gbps
Figure 1, (Notes 4, 5, 6)
0.03
0.05
UIp-p
TROJ2
Data Paths, measured at
Total Output Jitter
TPC PRBS7, EQ [2:0] = 000
1.65 Gbps
Figure 1, (Notes 4, 5, 6)
0.08
0.14
UIp-p
TROJ3
Data Paths, measured at
Total Output Jitter
TPC PRBS7, EQ [2:0] = 000
2.25 Gbps
Figure 1, (Notes 4, 5, 6)
0.09
0.16
UIp-p
TROJ4
Data Paths, measured at
Total Output Jitter
TPC PRBS7, EQ [2:0] = 000
3.4 Gbps
Figure 1, (Notes 4, 5, 6)
0.10
0.17
UIp-p
BWLOOP
CDR Loop
Bandwidth
0.25 Gbps data rate
0.25
MHz
1.65 Gbps data rate
1.65
MHz
2.25 Gbps data rate
2.25
MHz
3.4 Gbps data rate
2.25
MHz
Clock Channel PLL Jitter Generation
TROJ5
Clock Path, measured at TPC
Total Output Jitter
Figure 1
25 MHz
(Notes 4, 5, 6)
0.03
0.045
UIp-p
TROJ6
Clock Path, measured at TPC
Total Output Jitter
Figure 1
165 MHz
(Notes 4, 5, 6)
0.07
0.13
UIp-p
TROJ7
Clock Path, measured at TPC
Total Output Jitter
Figure 1
225 MHz
(Notes 4, 5, 6)
0.08
0.135
UIp-p
TROJ8
Clock Path, measured at TPC
Total Output Jitter
Figure 1
340 MHz
(Notes 4, 5, 6)
0.09
0.14
UIp-p
Note 1: “Absolute Maximum Ratings” are the ratings beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits.
Note 2: Allowed supply noise (mVp-p sine wave) at typical condition.
Note 3: Typical parameters are measured at VDD = 3.3 V, TA = 25 °C. They are for reference purposes, and are not production-tested.
Note 4: Parameter is guaranteed by statistical analysis and/or design.
Note 5: Deterministic jitter is measured at the differential outputs (TPC of Figure 1), minus the deterministic jitter before the test channel (TPA of Figure 1). Random
jitter is removed through the use of averaging or similar means.
Note 6: Total Jitter is defined as peak-to-peak deterministic jitter from + 12 times random jitter (ps).
Note 7: Random jitter contributed by the equalizer is defined as sq rt (JOUT2 − JIN2). JOUT is the random jitter at equalizer outputs in ps-rms, see TPC of Figure
1; JIN is the random jitter at the input of the equalizer in ps-rms, see TPA of Figure 1.
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DS34RT5110
Setup and Timing Diagrams
30087310
FIGURE 1. Test Setup Diagram
30087312
FIGURE 2. CML Output Swings at A/B (VOD_CRL = 24 kΩ)
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DS34RT5110
30087311
FIGURE 3. CML Output Transition Times
30087313
FIGURE 4. CML Latency Delay Time
30087314
FIGURE 5. SD – LOCK Delay Time
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The DS34RT5110 DVI, HDMI Retimer with Input Equalization
and Output De-Emphasis consists of three data channels and
30087315
FIGURE 6. Block Diagram
PHASE-LOCKED-LOCKED LOOP (PLL)
The clock channel has a high-performance PLL that creates
a low jitter sampling clock for the clock and data recovery units
in the data channels. An external loop filter, composed of 2.2
nF (+ 5% tolerance) capacitor and a 3.3 kΩ (+ 5% tolerance)
resistor in series, are required between the LFp and the LFn
pins.
INPUT EQUALIZATION
The input data channel equalizers support eight programmable levels of equalization boost Table 1 by the EQ
pins (EQ [2:0]). The range of boost settings provided enables
the DS34RT5110 to address a wide range of transmission line
path loss scenarios, enabling support for a variety of data
rates and formats. See Applications Information for recommended EQ settings.
CLOCK-DATA RECOVERY UNIT (CDR)
Each TMDS data channel has a CDR that operates independently from other TMDS data channels. Each CDR aligns the
sampling clock edges by digitally interpolating the clock from
PLL of the TMDS clock channel. The device is designed to
connect to DVI/HDMI compatible transmitter and receiver at
any data rate between 250 Mbps to 3.4 Gbps. The loop bandwidth of the CDR is approximately baud_rate/1000, i.e. 2.25
MHz for 2.25 Gbps data.
OUTPUT DE-EMPHASIS
De-emphasis is the conditioning function for use in compensating against backplane and cable transmission loss. The
DS34RT5110 provides four steps of de-emphasis ranging
from 0, 3, 6 and 9 dB, user-selectable dependent on the loss
profile of output channels. Table 2. shows the De-emphasis
control with default VO = 1000 mVp-p, and Figure 7. shows a
driver de-emphasis waveform.
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DS34RT5110
a clock channel. Each data channel consists of a TMDS compatible receiver with a power efficient equalizer, a dedicated
clock-data recovery (CDR) unit, and a TMDS compatible
transmitter.
Functional Description
DS34RT5110
in Table 3. Users should restrict the external resistor values
used to be 12 kΩ to 24 kΩ. +5% tolerance is recommended.
OUTPUT VO CONTROL
Output differential voltage (VO) is controlled through
VOD_CRL pin ties an external resistor to the ground as shown
TABLE 1. Equalization Control
INPUTS
RESULT
EQ2
EQ1
EQ0
Equalization in dB (1.7 GHz)
0
0
0
0 (default)
0
0
1
10
0
1
0
16
0
1
1
19
1
0
0
23
1
0
1
25
1
1
0
26
1
1
1
27
TABLE 2. De-Emphasis Control
INPUTS
RESULT
DE1
DE0
VO De-Emphasis level in mVpp
(VODE w/VOD_CRL = 24 kΩ
0
0
1000 (default)
0 (default)
0
1
710
-3
1
0
500
-6
1
1
355
-9
VO De-Emphasis in dB
TABLE 3. VO Control
External Resistor Value
(VOD_CRL pin)
Applications
VO Level (mVp-p)
24 kΩ
DC Coupled
1000
12 kΩ
AC Coupled
1000
30087316
FIGURE 7. Output De-Emphasis Differential Waveform (showing all de-emphasis steps)
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SIGNAL DETECT
The DS34RT5110 features a signal detect circuit on all channels. The status of the input signals can be determined by the
state of the SD pin. A logic HIGH indicates the presence of
signals that have exceeded a specified maximum threshold
value (called SD_ON) on all channels. A logic LOW means
that the signals have fallen below a minimum threshold value
(called SD_OFF) on one or more channels.
CLOCK CHANNEL MODE CONTROL
During the normal operation mode, the clock channel signal
is regenerated by the PLL and the CDR. Holding a LOW state
(default) on the MODE pin places the DS34RT5110 in this
normal operation mode. A HIGH state on the MODE pin bypasses the clock channel. This clock channel mode feature
enables the multi-hop applications. (Refer to Application Information – Multiple Hop Application for detailed information)
AUTOMATIC ENABLE FEATURE
During normal operation (i.e. BYPASS pin is LOW), the
DS34RT5110 can be configured to automatically enter
STANDBY mode, if the PLL of the DS34RT5110 is not locked.
The STANDBY mode can be implemented by connecting the
LOCK DETECT (LOCK) pin to the external (LVCMOS) Enable (EN) pin. If the LOCK pin is connected to the EN pin, a
logic HIGH on the LOCK pin will enable the device; thus the
DS34RT5110 will automatically enter the ACTIVE state. If the
PLL is unlocked, then the LOCK pin will be asserted LOW,
causing the aforementioned blocks to be placed in the
STANDBY state.
DEVICE STATE AND ENABLE CONTROL
The DS34RT5110 has an Enable feature which provides the
ability to control device power consumption. This feature can
be controlled via the Enable Pin (EN Pin). If Enable is activated, the data channels and clock channel are placed in the
ACTIVE state and all device blocks function as described.
The DS34RT5110 can also be placed in STANDBY mode to
save power. In this mode, the output drivers of the device are
disabled. The CML outputs are in the HIGH (AVCC) state. All
LVCMOS outputs are in the HiZ state.
LOCK DETECT
When the PLL of the DS34RT5110 is locked, and the generated reference phases are successfully interpolated by the
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DS34RT5110
CDR, this status is indicated by a logic HIGH on the LOCK
pin. The LOCK pin may be connected to the Enable (EN) pin
input to disable the data channels and clock channel when no
data signal is being received.
RETIMING AND DE-EMPHASIS BYPASS
The retiming and De-emphasis BYPASS pin provides the
flexibility to configure the device to an equalizer only mode.
The device is in normal operation, when holding a LOW state
on the BYPASS pin. The retiming and De-emphasis features
are disabled, when a HIGH state is applied.
DS34RT5110
peater device, see Figure 8. As the source device, the output
de-emphasis setting should be configured based on the driving cable length. When used as the sink device, the levels of
the equalization boost of the input data channels should be
optimized based on the receiving cable length. The
DS34RT5110 can also be used as a repeater in an external
extender box with the equalization and de-emphasis level
settings optimized to provide the maximum cable reach.
Application Information
The DS34RT5110 is a DVI/HDMI video signal reconditioning
device. The device conforms to DVI v1.0 and HDMI v1.3a
standards supporting up to 10.2 Gbps total throughput TMDS
data for 1080p with 48 bit deep color depth.
TYPICAL APPLICATION
In general, the DS34RT5110 in the default mode (MODE = L)
is used as a DVI/HDMI source device, sink device, or a re-
30087353
FIGURE 8. Typical Application Diagram
device at the first hop (using two hop application), or at the
first and the second hops (using three hop application shown
in Figure 9) is recommended to be set HIGH to minimize the
jitter accumulation in multiple hops. The MODE pin of the device for the final hop should be set to a LOW state to clean up
the clock jitter, in order to drive the maximum cable length to
the Sink.
MULTIPLE HOP APPLICATION
For DVI/HDMI home theater and professional studio systems
with extensive lengths of cable, multi-hops with 2 or more
cascaded DS34RT5110 devices can be implemented as
shown in Figure 9. In order to reach the maximum cable
length, the levels of the equalization and de-emphasis should
be optimized for each individual hop. The MODE pin(s) of the
30087317
FIGURE 9. Multiple Hop Systems
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30087318
FIGURE 10. Matrix Switch Systems
DS34RT5110 devices are configured as shown in Figure 11.
This configuration is only recommended for a single dual link
repeater application.
DUAL LINK APPLICATION
The DS34RT5110 supports DVI dual link applications requiring ultra-high resolutions for QXGA and WQXGA. Two
30087319
FIGURE 11. DVI/HDMI Dual Link Application
ground potential difference, or to use one CAT5/6 cable between two chassis. To optimize the DS34RT5110 performance, the external resistance of 12 kΩ at the VOD_CRL pin
should be used on the Source DS34RT5110, and a pair of 50
Ω pull-up resistors should be placed close to the outputs of
the Source DS34RT5110, in order to DC bias the output driver. Meanwhile, 622Ω pull-down resistors should be placed at
the inputs of the Sink DS34RT5110 device, in order to set the
input common mode to a 3.05 V. Note AC coupled configuration is not compliant to the HDMI specification of Source
requirement (See Figure 13).
DC AND AC COUPLED APPLICATIONS
The DS34RT5110 is designed to support TMDS differential
pairs with DC coupled transmission lines. It contains integrated termination resistors (50Ω), pulled up to VDD at the input
stage, and open collector outputs for DVI / HDMI signaling.
Figure 12 shows the DC coupled connection between the
HDMI Source (ie. DS34RT5110) and HDMI Sink (ie.
DS34RT5110) devices. In the DC coupled application, the
external resistance of 24 kΩ at VOD_CRL pin is used at the
Source to ensure the VO level of 1000 mVp-p. The AC coupled method connecting between the Source and the Sink
devices may be preferred to eliminate the impact of the
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DS34RT5110
quirement from the Sources, clean the system jitter due to the
complexity of PCB routings, and regenerate clean TMDS signals to the Sinks as shown in Figure 10.
MATRIX SWITCH APPLICATION
For the security system with matrix DVI/HDMI switches, the
DS34RT5110 is ideal to equalize the long cable reach re-
DS34RT5110
30087320
FIGURE 12. DC Coupled Application
30087321
FIGURE 13. AC Coupled Application
24 AWG UTP (LOW SKEW UNSHIELDED TWIST PAIRS)
CABLES
The DS34RT5110 can be used to extend the length of low
skew grade UTP cables, such as Cat5e and Cat6 to distances
greater than 30 meters at 1.65 Gbps with < 0.20 UI of jitter.
Note that for non-standard DVI/HDMI cables, the user must
ensure the inter pair skew requirements are met. Table 5
shows the recommended EQ control settings for various data
rates and cable lengths for UTP configurations.
CABLE SELECTION AND INTER-PAIR SKEW
DVI v1.0 and HDMI v1.3a specify Inter-Pair Skew requirements for the system. The DS34RT5110 intends to extend the
longer cable reach with STP (DVI / HDMI) cable, or UTP
(Cat5 / Cat5e / Cat6) cable, and it does not have a de-skew
function to compensate any cable Inter-Pair Skews. Long cable with Inter-Pair Skew exceeding the DVI / HDMI standard
limit tolerance could cause system distortion. Therefore, National suggests the consideration of Inter-Pair Skew budget
during the system design, and recommends Low-Skew Video
grade cables for cable extending applications.
TABLE 5. EQ Control Setting for UTP Cable
28 AWG STP (SHIELDED TWIST PAIRS) DVI / HDMI
CABLES RECOMMENDED EQ SETTINGS
Table 4 provides the recommended EQ control settings for
various data rates and cable lengths for 28 AWG DVI/HDMI
compliant configurations. The EQ setting is made via three
EQ [2:0] pins.
TABLE 4. EQ Control Setting for STP Cable
Format (Data Rate)
0 ~ 10m
> 10m
1080P 48-bit (3.4 Gbps)
Setting 0x01
Setting 0x06
1080P 36-bit (2.25 Gbps)
Setting 0x01
Setting 0x06
1080P (1.65 Gbps)
Setting 0x01
Setting 0x06
1080I (750 Mbps)
Setting 0x06
Setting 0x06
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14
Format (Data Rate)
0 ~ 10m
> 10m
1080P 48-bit (3.4 Gbps)
Setting 0x01
Setting 0x05
1080P 36-bit (2.25 Gbps) Setting 0x01
Setting 0x05
1080P (1.65 Gbps)
Setting 0x01
Setting 0x05
1080I (750 Mbps)
Setting 0x05
Setting 0x05
The DS34RT5110 is a high performance circuit capable of
delivering excellent performance. To achieve optimal performance, careful attention must be paid to the details associated with high-speed design as well as providing a clean
power supply. Refer to the LVDS Owner’s Manual for more
detailed information on high-speed design tips as well as
many other available resources addressing signal integrity
design issues.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL
PAIRS
The TMDS differential inputs and outputs must have a controlled differential impedance of 100 Ω. It is preferable to route
TMDS lines exclusively on one layer of the board, particularly
for the input traces. The use of vias should be avoided if possible. If vias must be used, they should be used sparingly and
must be placed symmetrically for each side of a given differential pair. Route the TMDS signals away from other signals
and noise sources on the printed circuit board. All traces of
TMDS differential inputs and outputs must be equal in length
to minimize intra-pair skew.
EQUIVALENT I/O STRUCTURES
Figure 14 shows the DS34RT5110 CML output structure and
ESD protection circuitry.
Figure 15 shows the DS34RT5110 CML input structure and
ESD protection circuitry.
LLP FOOTPRINT RECOMMENDATIONS
See National application note: AN-1187, “Leadless Leadframe Package (LLP)” for additional information on LLP packages footprint and soldering information.
30087322
FIGURE 14. Equivalent Output Structure
30087323
FIGURE 15. Equivalent Input Structure
15
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DS34RT5110
POWER SUPPLY BYPASSING
Two approaches are recommended to ensure the
DS34RT5110 is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) pins should be
connected to power planes routed on adjacent layers of the
printed circuit board. The layer thickness of the dielectric
should be minimized so the VDD and GND planes create a
low inductance supply with distributed capacitance. Second,
careful attention to supply bypassing through the proper use
of bypass capacitors is required. A 0.1 μF bypass capacitor
should be connected to each VDD pin such that the capacitor
is placed as close as possible to the DS34RT5110. Smaller
body size capacitors can help facilitate proper component
placement. Additionally, two capacitors with capacitance in
the range of 2.2 μF to 10 μF should be incorporated in the
power supply bypassing design as well. These capacitors can
be either tantalum or an ultra-low ESR ceramic and should be
placed as close as possible to the DS34RT5110.
General Recommendations
DS34RT5110
Typical Performance
Characteristics as a Repeater
30087309
FIGURE 16. Simplified Test Setup as a Single Repeater
30087355
30087356
FIGURE 17. System Source Eye Diagram at TPA
(3.4 Gbps)
FIGURE 18. Device Sink Eye Diagram at TPB
(3.4 Gbps, Cable A = 20m 28 AWG HDMI)
30087358
30087357
FIGURE 20. Device Source Eye Diagram at TPC
(3.4 Gbps, Cable A = 20m 28 AWG HDMI,
EQ = 0x05, BYPASS = 0, DE = -3dB)
FIGURE 19. Device Source Eye Diagram at TPC
(3.4 Gbps, Cable A = 20m 28 AWG HDMI,
EQ = 0x05, BYPASS = 0, DE = 0dB)
30087359
FIGURE 21. System Sink Eye Diagram at TPd
(3.4 Gbps, Cable A = 20m 28 AWG HDMI, Cable B = 5m 28AWG
HDMI, EQ = 0x05, BYPASS = 0, DE = -3dB)
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16
DS34RT5110
30087360
30087361
FIGURE 22. System Source Eye Diagram at TPA
(2.25 Gbps)
FIGURE 23. Device Sink Eye Diagram at TPB
(2.25 Gbps, Cable A = 25m 28 AWG HDMI)
30087363
30087362
FIGURE 25. Device Source Eye Diagram at TPC
(2.25 Gbps, Cable A = 25m 28 AWG HDMI,
EQ = 0x05, BYPASS = 0, DE = -3dB)
FIGURE 24. Device Source Eye Diagram at TPC
(2.25 Gbps, Cable A = 25m 28 AWG HDMI,
EQ = 0x05, BYPASS = 0, DE = 0dB)
30087364
FIGURE 26. System Sink Eye Diagram at TPD
(2.25 Gbps, Cable A = 25m 28 AWG HDMI, Cable B = 7.5m
28AWG HDMI, EQ = 0x05, BYPASS = 0, DE = -3dB)
17
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DS34RT5110
30087365
30087366
FIGURE 27. System Source Eye Diagram at TPA
(1.65 Gbps)
FIGURE 28. Device Sink Eye Diagram at TPB
(1.65 Gbps, Cable A = 35m 28 AWG HDMI)
30087367
30087368
FIGURE 29. Device Source Eye Diagram at TPC
(1.65 Gbps, Cable A = 35m 28 AWG HDMI,
EQ = 0x05, BYPASS = 0, DE = 0dB)
FIGURE 30. Device Source Eye Diagram at TPC
(1.65 Gbps, Cable A = 35m 28 AWG HDMI,
EQ = 0x05, BYPASS = 0, DE = -6dB)
30087369
FIGURE 31. System Sink Eye Diagram at TPD
(1.65 Gbps, Cable A = 35m 28 AWG HDMI, Cable B = 10m
28AWG HDMI, EQ = 0x05, BYPASS = 0, DE = -6dB)
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18
DS34RT5110
Physical Dimensions inches (millimeters) unless otherwise noted
7mm x 7mm 48-pin LLP Package
Order Number DS34RT5110SQ
Package Number SQA48A
19
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DS34RT5110 DVI, HDMI Retimer with Input Equalization and Output De-Emphasis
Notes
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