4 Channel 6Gbps SAS/SATA Signal Repeater 89HP0604SB Data Sheet ® Device Overview Features The IDT 89HP0604SB (P0604SB) is a 6Gbps SAS/SATA® Repeater device featuring IDT EyeBoost™ technology that compensates for cable and board trace attenuations and ISI jitter, thereby extending connection reach. The device is optimized for SAS/SATA high speed serial data streams and contains four data channels, each able to process 6Gbps transmission rates. Each channel consists of an input equalizer and amplifier, signal detection with glitch filter, as well as programmable output swing and de-emphasis. Allowing for application specific optimization, the P0604SB, with its configurable receiver and transmitter features, is ideal for SAS/SATA applications using a wide combination of cables and board trace materials. All modes of active data transfer are designed with minimized power consumption. In full shutdown mode, the part consumes less than 40mW in worst case environmental conditions. Applications Blade servers, rack servers SAS/SATA instrumentation Storage systems Cabled SAS/SATA devices Compensates for cable and PCB trace attenuation and ISI jitter Programmable receiver equalization up to 24db Programmable transmitter swing and de-emphasis Recovers data stream even when the differential signal eye is completely closed due to trace attenuation and ISI jitter Full SAS/SATA protocol support Configurable via external pins Leading edge power minimization in active and shutdown modes No external bias resistors or reference clocks required Channel mux mode, demux mode, 1 to 2 channels multicast, and Z-switch function mode Available in a 36-pin QFN package (4.0 x 7.5mm with 0.5mm pitch) Benefits Extends maximum cable length to over 8 meters and trace length over 48 inches in SAS/SATA applications Minimizes BER Typical Application Figure 1 IDT Repeaters in Blade Servers IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 © 2011 Integrated Device Technology, Inc February 8, 2011 IDT 89HP0604SB Data Sheet SAS/SATA Compliance The device was designed to provide end users with features needed to comply with SAS/SATA system application requirements: – SAS/SATA Out-of-Band (OOB) Support – Jitter, eye opening, and all other AC and DC specifications. Block Diagram The P0604SB contains four high speed channels as shown in Figure 2. Each channel can be routed to different outputs. Depending on user configuration via mode selections, input traffic can be muxed or demuxed. Powerdown (PDB) is provided for state and channel control. Figure 2 Block Diagram 2 February 8, 2011 Table of Contents Device Overview ................................................................................................................................ 1 Applications........................................................................................................................................ 1 Features............................................................................................................................................. 1 Benefits .............................................................................................................................................. 1 Typical Application ............................................................................................................................. 1 SAS/SATA Compliance ..................................................................................................................... 2 Block Diagram.................................................................................................................................... 2 Functional Description ....................................................................................................................... 5 Power-Up................................................................................................................................... 6 Power Sequencing..................................................................................................................... 6 IDT EyeBoost™ Technology ..................................................................................................... 6 Eye Diagram Parameters .......................................................................................................... 7 Modes of Operation ................................................................................................................... 7 Electrical Specifications ................................................................................................................... 11 Absolute Maximum Ratings ..................................................................................................... 11 Recommended Operating Conditions...................................................................................... 11 Power Consumption ................................................................................................................ 12 Package Thermal Considerations............................................................................................ 12 DC Specifications .................................................................................................................... 13 AC Specifications..................................................................................................................... 13 Pin Description................................................................................................................................. 17 Package Pinout — 36-QFN Signal Pinout ....................................................................................... 19 Pin Diagram ..................................................................................................................................... 19 QFN Package Dimension ................................................................................................................ 20 Revision History ............................................................................................................................... 21 Ordering Information........................................................................................................................ 22 3 February 8, 2011 IDT 89HP0604SB Data Sheet PAGE INTENTIONALLY LEFT BLANK 4 February 8, 2011 IDT 89HP0604SB Data Sheet Functional Description The P0604SB has 4 channels, each with the individually programmable features listed below. Figure 3 diagrams the channel and Table 1 summarizes key configuration options. OOB/LOS detection with glitch filter Channel power-down Programmable equalizer + _ Input termination ٛ 100 ohm 0 to 14dB Programmable Transmitter ٛ De-emphasis: 0 to -6.5dB ٛ Voltage swing: 500mV to Up to 10dB Auto-boost 950mV ٛ ٛ ٛ Output termination 100 ohm + _ Figure 3 Channel Block Diagram with Channel Features Per-channel programmable features used at the Receive side. – Input equalization with 3 levels: 2 to 14dB compensation for high frequency signal attenuation due to cables and board traces. Additionally, up to 10dB boost is added automatically by the equalizer for applications using long cables. The total equalization range is between 2dB and 24dB. – Input high impedance control via channel enable: disabled (active mode) and hi-Z (power-down). Per-channel programmable features used at the Transmit side. – Output de-emphasis with 8 levels: 0 to -6.5dB. The de-emphasis boosts the magnitude of higher frequencies sent by the transmitter to compensate for high frequency losses travelling through output side cable or output side board traces. This ensures that the final received signal has a wider eye opening. – Output differential swing with 3 levels: 0.5V to 0.95V (peak-to-peak). – Loss of signal detection: When the incoming differential peak-peak amplitude falls below 110mV, the device enters loss of signal mode and the corresponding transmitter stops toggling, maintains its common mode voltage level, and meets all loss of signal specifications described in the AC Specifications section of this data sheet. In addition, the device contains global configuration of the data path: – Transfer modes: direct connect, cross-connect, multicast. 5 February 8, 2011 IDT 89HP0604SB Data Sheet Power-Up After the power supplies reach their minimum required levels, the P0604SB powers up by setting all input and output pins to known states: All the device's input configuration pins are set internally to VSS or VDD for 2-level pins and to VDD/2 for 3-level pins. High speed differential input and output pins depend on various conditions described below: – High speed differential input and output pins are in high impedance if any of the following conditions is true: • Powerdown is set (PDB pin = 0V) or • No receiver termination was detected at TX outputs In all other cases, high speed differential input and output pins are set to 50 ohms per pin, with 100 ohms differential impedance. Also refer to Table 2, Power Reducing Modes. The power ramp up time for the P0604SB should be less than 1ms. Power Sequencing There are no power sequencing constraints for the P0604SB. IDT EyeBoost™ Technology IDT EyeBoost™ technology is a method of data stream recovery even when the differential signal eye is completely closed due to cable or trace attenuation and ISI jitter. With IDT EyeBoost™, the system designer can both recover the incoming data and retransmit it to target device with a maximized eye width and amplitude. An example of IDT EyeBoost™ usage in a system application and eye diagram results are shown in Figure 4. In this figure, the (a) diagram shows incoming differential signal (closed eye) after 62 inch FR4 connection from signal source and the (b) diagram shows differential signal at the output of repeater maximized eye opening with IDT EyeBoost™. (a) (b) Figure 4 Eye Diagram 6 February 8, 2011 IDT 89HP0604SB Data Sheet Eye Diagram Parameters Parameter Names for Programming via Pins Feature Feature Type Input equalization Main eye optimization A0RXEQ, A1RXEQ, B0RXEQ, B1RXEQ Range: 0dB to 14dB (plus additional autoboost up to 10dB for long connections) Output differential signal swing (peak-to-peak) and output de-emphasis Main eye optimization A0TXSW, A1TXSW, B0TXSW, B1TXSW Range: 0.5V to 0.95V for swing Range: 0 to -6.5dB for de-emphasis Table 1 Quick Reference: Parameters Used for Eye Optimization Modes of Operation The device supports several data transfer modes, loss of signal mode, and one power reducing mode. Loss of Signal Mode When the input signal is lost, the transmitter stops toggling and maintains its common-mode voltage level. The device detects loss-of-signal (LOS) when the envelope of the incoming signal on a given channel has fallen below a programmable threshold level. Power Reducing Modes The Repeater supports five power-down states and one active state as shown in Table 2. The user can choose between full chip power-down or channel based power-down. Power reducing modes are selected via PDB and channel enable pins (A0EN, A1EN, etc.). Power Reducing Mode Required Signal Values State Description PDB Full IC powerdown 0 All channels are powered-down Rx termination is set to Hi-Z Tx termination is set to 1kΩ Tx common-mode is at VDD Channel enabled and active. No power-down 1 Tx output is active Receiver terminations set to 50Ω Transmitter terminations set to 50Ω Table 2 Power Reducing Modes 7 February 8, 2011 IDT 89HP0604SB Data Sheet Channel Muxing The P0604SB repeater permits a variety of muxing, demuxing, and switching configurations, and it can mux/de-mux 1 or 2 bi-directional SAS/ SATA lanes (4 SAS/SATA channels) into 2 target devices. These configurations require the selection of specific pins for input and output ports. In the following sections, each configuration is described in terms of pin connectivity to external upstream and downstream devices. The configurations shown are those often used in system designs: – Uni-directional 2:1 Mux (1 or 2 instances) – Uni-directional 1:2 De-Mux (1 or 2 instances) – Bi-directional 2:1 Mux/De-Mux – Bi-directional Z-function (also called Partial Cross Function) The P0604SB supports channel muxing in both upstream and downstream channel directions via the CHSEL pin, as shown below. Figure 5 shows the channel/reference muxing modes and Table 3 shows how CHSEL (Channel transfer selection) pin allows for various modes of data transfers: Multicast mode, Direct-connect, and Cross-connect. Both Direct-connect, and Cross-connect modes are used to build uni-directional and bi-directional 2:1 mux and Z-switch functions. Figure 5 Diagram of Channel/Reference Muxing Modes Input Pins Output Pins CHSEL A0RX[P,M] A1RX[P,M] B0RX[P,M] B1RX[P,M] A0TX[P,M] A1TX[P,M] B0TX[P,M] B1TX[P,M] CHSEL=VSS (Multicast Mode) A0 DATA X B0 DATA X A0 DATA A0 DATA B0 DATA B0 DATA CHSEL=Open (Direct-Connect Mode) A0 DATA A1 DATA B0 DATA B1 DATA A0 DATA A1 DATA B0 DATA B1 DATA CHSEL=VDD (Cross-Connect Mode) A0 DATA X B0 DATA X Squelched A0 DATA Squelched B0 DATA Table 3 Description of Channel Muxing/De-Muxing Functionality 8 February 8, 2011 IDT 89HP0604SB Data Sheet Uni-directional 2:1 Mux or Two Instances of Unidirectional 2:1 Mux This function can be achieved by using the CHSEL pin as a mux control signal. CHSEL should be set to either VDD or OPEN. The ports should be configured as shown in Figure 6. Device #1 A0RX(P,N) A OUT A1TX(P,N) Device #3 B Device #2 A1RX(P,N) CHSEL CHSEL = VDD: OUT = A CHSEL = OPEN: OUT = B Figure 6 Implementation of Unidirectional 2:1 Mux As an alternative, different chip channels can also be selected as shown in Figure 7. This solution can be combined with the previous one to obtain two instances of Uni-directional 2:1 Mux. Device #1 or #4 B0RX(P,N) A OUT B1TX(P,N) Device #3 or #6 B Device #2 or #5 B1RX(P,N) CHSEL CHSEL = VDD: OUT = A CHSEL = OPEN: OUT = B Figure 7 Implementation of Second Instance of Unidirectional 2:1 Mux Uni-directional 1:2 De-Mux or Two Instances of Unidirectional 1:2 De-Mux This function can be achieved by using CHSEL pin as a de-mux control signal. CHSEL should be set to either VDD or OPEN. The ports should be configured as shown in Figure 8. A Device #1 A0RX(P,N) A0TX(P,N) Device #2 IN B A1TX(P,N) Device #3 CHSEL CHSEL = OPEN: A = IN CHSEL = VDD: B = IN Figure 8 Implementation of Unidirectional 1:2 De-Mux 9 February 8, 2011 IDT 89HP0604SB Data Sheet As an alternative, different chip channels can also be selected as shown in Figure 9. This solution can be combined with the previous one to obtain two instances of Uni-directional 1:2 De-Mux. B0TX(P,N) A Device #1 or #4 B0RX(P,N) Device #2 or #5 IN B B1TX(P,N) Device #3 or #6 CHSEL CHSEL = OPEN: A = IN CHSEL = VDD: B = IN Figure 9 Implementation of Second Instance of Unidirectional 1:2 De-Mux Bi-directional 2:1 Mux/De-Mux The bi-directional Mux and De-Mux function can also be achieved by using the CHSEL pin as a mux control signal. CHSEL should be set to either VDD or OPEN. The ports should be configured as shown in Figure 10. Device #1 A0RX(P,N) B1TX(P,N) A I/O A1TX(P,N) B0RX(P,N) Device #3 B Device #2 A1RX(P,N) B0TX(P,N) CHSEL CHSEL = VDD: I/O = A CHSEL = OPEN: I/O = B Figure 10 Implementation of Bi--directional 2:1 Mux/De-Mux Bi-directional Z-function (also called Partial Cross Function) This function can also be achieved by using the CHSEL pin as a flow control signal. CHSEL should be set to either VDD or OPEN. The ports should be configured as shown in Figure 11. Device #1 A0TX(P,N) B1RX(P,N) CHSEL=OPEN S CH Device #2 A1TX(P,N) B0RX(P,N) A0RX(P,N) B1TX(P,N) Device #3 A1RX(P,N) B0TX(P,N) Device #4 DD =V L E CHSEL=OPEN Figure 11 Implementation of Z-function 10 February 8, 2011 IDT 89HP0604SB Data Sheet Electrical Specifications Absolute Maximum Ratings Note: All voltage values, except differential voltages, are measured with respect to ground pins. Parameter Value Unit –0.5 to 1.35 V Voltage range Differential I/O –0.5 to VDD +0.5 V Control I/O –0.5 to VDD + 0.5 V ESD requirements: Electrostatic discharge Human body model ±2000 V ESD requirements: Charged-Device Model (CDM) ±500 V ESD requirements: Machine model ±125 V -55 to 150 °C Supply voltage range VDD Storage ambient temperature Table 4 Absolute Maximum Ratings Warning: Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Notes Min Typical Max Unit 1.2V DC analog supply voltage (specified at bump pins) 1.14 1.2 1.26 V 0 — 70 °C -40 — 85 °C 0 — 125 °C Power Supply Pin Requirements VDD Temperature Requirements TA Ambient operating temperature - Commercial Ambient operating temperature - Industrial TJUNCTION Junction operating temperature Table 5 P0604SB Operating Conditions 11 February 8, 2011 IDT 89HP0604SB Data Sheet Power Consumption Table 6 below lists power consumption values under typical and maximum operating conditions. Parameter Notes Min Typical Max Unit — Active Mode IVDD Current into VDD supply 330 500 mA PD Full chip power1 400 600 mW PD-ch Power per channel1 100 150 mW Standby Mode Full chip standby 30 40 mW Table 6 Power Consumption 1. Maximum power under all conditions. Power is reduced by selecting smaller de-emphasis settings (closer or equal to 0dB). Package Thermal Considerations The data in Table 7 below contains information that is relevant to the thermal performance of the 36-pin QFN package. Symbol θJA(effective) Parameter Effective Thermal Resistance, Junction-to-Ambient Value Conditions Units 49.8 Zero air flow oC/W 44.8 1 m/S air flow oC/W 42.2 2 m/S air flow o C/W θJB Thermal Resistance, Junction-to-Board 39.3 NA oC/W θJC Thermal Resistance, Junction-to-Case 34.5 NA oC/W Table 7 Thermal Specifications for 36-QFN Package Note: It is important for the reliability of this device in any user environment that the junction temperature not exceed the TJ(max) value specified in Table 7. Consequently, the effective junction to ambient thermal resistance (θJA) for the worst case scenario must be maintained below the value determined by the formula: θJA = (TJ(max) - TA(max))/P Given that the values of TJ(max), TA(max), and P are known, the value of desired θJA becomes a known entity to the system designer. How to achieve the desired θJA is left up to the board or system designer, but in general, it can be achieved by adding the effects of θJC (value provided in Table 7), thermal resistance of the chosen adhesive (θCS), that of the heat sink (θSA), amount of airflow, and properties of the circuit board (number of layers and size of the board). 12 February 8, 2011 IDT 89HP0604SB Data Sheet DC Specifications Parameter Description Min Typ Max Unit VIL Digital Input Signal Voltage Low Level1 -0.3 — 0.25*VDD-0.1 V VIM Digital Input Signal Voltage Mid Level2 0.25*VDD+ 0.1 0.75*VDD-0.1 V VIH Digital Input Signal Voltage High Level1 0.75*VDD+ 0.1 VDD+ 0.3 V VHYS Hysteresis of Schmitt Trigger Input 0.1 — V IIL Input Current3 — 100 µA IIH Input Current4 — 100 µA IIL1 Input Current2 — 180 µA IIH1 Input Current2 — 180 µA RWEAK_PD_2L Internal weak pull-down resistor at 2-level input pads4 11 — K ohm RWEAK_PU_2L Internal weak pull-up resistor at 2-level input pads3 11 — K ohm RWEAK_PD_3L Internal weak pull-down resistor at all 3-level input pads 6.3 — K ohm RWEAK_PU_3L Internal weak pull-up resistor at all 3-level input pads 6.3 — K ohm Table 8 DC Specification 1. Applies to all input pins. 2. Applies to all 3-level input pins. 3. Applies only to 2-level input pins with default values set to VDD in the Pin Description table (Table 12). 4. Applies only to 2-level input pins with default values set to VSS in the Pin Description table (Table 12). AC Specifications Latency Specification Parameter Description Min Typical Max Unit TPD Input to output signal propagation device — 300 — ps TSIGDET-ATTACK Signal Detect Valid Signal Attack Time (Turn-on time) — — 15 ns TSIGDET-DECAY Signal Detect Valid Signal Decay Time (Turn-off time) — — 15 ns TSIGDET-ATT-DECAY-MIS Signal Detect Attack / Decay Time Mismatch — — 5 ns Min Typical Max Unit Table 9 P0604SB Latency Specification Receiver Specifications Parameter Description Receiver Input Jitter Specification TRX-DJ Receive input, Data Dependant Jitter (Inter-SymbolInterference) — — >1 UI TRX-TJ Receive input, Total Jitter — — >1 UI TRX-EYE Receiver eye time opening (can recover from closed eye due to trace/cable jitter) 0 — — UI Table 10 P0604SB Receiver Electrical Specifications (Part 1 of 2) 13 February 8, 2011 IDT 89HP0604SB Data Sheet Parameter Description Min Typical Max Unit Receiver Input Eye Specification VDIFF-RX Receiver Differential Peak-Peak Voltage1 0 — 2000 mV tskew-RX RX Differential Skew — — 30 ps VCM-AC-RX Receiver AC Common Mode Voltage — — 100 mVp-p Vthresh OOB Signal Detection Threshold 50 110 160 mVppd 0 MHz - 150 MHz 18 — — dB 150 MHz - 300 MHz 18 — — 300 MHz - 600 MHz 14 — — 600 MHz - 1.2 GHz 10 — — 1.2 GHz - 2.4 GHz 8 — — 2.4 GHz - 3.0 GHz 3 — — 3.0 GHz - 5.0 GHz 1 — — Receiver Return Loss RLDD11,RX RX Differential Mode Return Loss RLRXslope Slope of RX Differential Mode Return Loss (From 300MHz) — -13 — dB/dec RLRX-freq-max RX Differential Mode Return Loss Max Frequency — 6 — GHz RLCC11,RX RX Common Mode Return Loss 0 MHz - 300 MHz 5 — — dB 300 MHz - 600 MHz 5 — — 600 MHz - 1.2 GHz 2 — — 1.2 GHz - 2.4 GHz 1 — — 2.4 GHz - 3.0 GHz 1 — — 3.0 GHz - 5.0 GHz — — — Receiver DC Impedance ZDIFF-RX Differential impedance , RX pair 85 — 115 Ohm ZCM-RX Common-Mode Receive Impedance 20 — 40 Ohm Table 10 P0604SB Receiver Electrical Specifications (Part 2 of 2) 1. The minimum value of 0 mV represents the case when Eye is completely closed. Transmitter Specifications Parameter Description Min Typical Max Unit Output Eye and Common Voltage Specification VTX-DIFF-PP Differential Transmitter swing [A:B]xTXSW=1 [A:B]xTXSW=open 800 700 950 800 1100 950 mV VTX-DIFF-PP-LOW Low power differential p-p Transmitter swing [A:B]xTXSW=0 400 500 650 mV Table 11 P0604SB Transmitter Electrical Requirements (Part 1 of 2) 14 February 8, 2011 IDT 89HP0604SB Data Sheet Parameter Description Min Typical Max Unit 0 dB VTX-DE-RATIO Tx de-emphasis level ratio -6.5 VTX-DE-RATIO-3.5dB Tx de-emphasis level ratio [A:B]xTXSW=open -4.0 — -3.0 dB VTX-DE-RATIO-6dB Tx de-emphasis level [A:B]xTXSW=1 -6.5 — -5.5 dB TRES-DJ-6.25GBPS-1 Residual Deterministic Jitter at output pins (1 inch FR4 trace before receiver input pins, 6.25Gbps)1 — — <0.1 UI TRES-DJ-6.25GBPS-2 Residual Deterministic Jitter at output pins (40 inch FR4 trace before receiver input pins, 6.25Gbps)1 — 0.18 0.25 UI T20-80TX TX Rise/Fall Time (20-80%) 33 — 90 ps TskewTX TX Differential Skew — — 20 ps R/Fbal TX Rise/Fall Imbalance — — 20 % AMPbal TX Amplitude Balance — — 10 % VCM,AC-TX-PP Tx AC Common Mode Voltage (Peak to peak) — — 50 mVp-p VTX-CM-RMS-AC RMS AC Common Mode Voltage Variation — — 20 mV CTX AC Coupling Capacitor 12 — 200 nF Transmitter DC Impedance ZTX-DIFF-DC Transmitter Output Differential DC Impedance 85 100 115 Ohm ITX-SHORT Transmitter short-circuit current limit — — 90 mA DC TX Differential Mode Return Loss 14 — — dB DC TX Differential Mode Return Loss (FBAUD/2) 6 — — RLTXslope Slope of TX Differential Mode Return Loss (From 300MHz) — -13 — dB/dec RLCC11,TX TX Common Mode Return Loss (measured at 3.0 Gbps) 0 MHz - 300 MHz 8 — — dB 300 MHz - 600 MHz 5 — — 600 MHz - 1.2 GHz 2 — — 1.2 GHz - 2.4 GHz 1 — — 2.4 GHz - 3.0 GHz 1 — — 3.0 GHz - 5.0 GHz 1 — — Lane-to-Lane Output Skew — 5 10 Transmitter Return Loss RLDD11,TX Lane Skew LTX-SKEW ps Table 11 P0604SB Transmitter Electrical Requirements (Part 2 of 2) 1. Refer to Figure 12. 15 February 8, 2011 IDT 89HP0604SB Data Sheet A — FR4 Trace B — SMA Connector C — Measurement Point Note: FR4 test channel is bypassed for 1-inch input trace case. Figure 12 Residual Jitter Characterization Test Setup 16 February 8, 2011 IDT 89HP0604SB Data Sheet Pin Description Note: Unused pins can be left floating. Pin Name Input/ Output/ Power 2 or 3 Level Pin # Description VDD 5, 8, 11, 21, 24, 27 1.2V (typ) Power supply for Repeater high speed channels and internal logic. Each VDD pin should be connected to the VDD plane through a low inductance path, with a via located as close as possible to the landing pad of VDD pins. It is recommended to have a 0.01 µF or 0.1 µF, X7R, size-0402 bypass capacitor from each VDD pin to ground plane. Power VSS Center Pad VSS reference. VSS should be connected to the ground plane through a low inductance path, with a via located as close as possible to the landing pad. Power Power Data Signals A0RXN A0RXP 4 3 Channel A0 Receive Data Ports Input A0TXN A0TXP 28 29 Channel A0 Transmit Data Ports Output B0RXN B0RXP 25 26 Channel B0 Receive Data Ports Input B0TXN B0TXP 7 6 Channel B0 Transmit Data Ports Output A1RXN A1RXP 10 9 Channel A1 Receive Data Ports Input A1TXN A1TXP 22 23 Channel A1 Transmit Data Ports Output B1RXN B1RXP 19 20 Channel B1 Receive Data Ports Input B1TXN B1TXP 13 12 Channel B1 Transmit Data Ports Output 15 17 36 33 Receiver Equalization at F=3GHz (6Gbps). Programming of channel A0 via pins is shown below. To program other channels, use pins for those channels. A0RXEQ Setting VSS 2dB (3GHz) Open 6dB (3GHz) (Default) VDD 14dB (3GHz) Input - 3 level Channel Control and Status A0RXEQ (Channel A0) B0RXEQ (Channel B0) A1RXEQ (Channel A1) B1RXEQ (Channel B1) Table 12 Pin Description (Part 1 of 2) 17 February 8, 2011 IDT 89HP0604SB Data Sheet Input/ Output/ Power 2 or 3 Level Pin Name Pin # Description A0TXSW (Channel A0) B0TXSW (Channel B0) A1TXSW (Channel A1) B1TXSW (Channel B1) 1 32 14 18 Transmitter Voltage Swing (pk-pk). Programming of channel A0 via pins is shown below. To program other channels, use pins for those channels. A0TXSW Swing De-Emphasis VSS 0.5Vdiff-pkpk 0dB Open 0.8Vdiff-pkpk (Default) -3.5dB VDD 0.95Vdiff-pkpk -6.5dB Input - 3 level PDB 35 Power-down Enable. PDB Setting VSS Powerdown IC. RX terminations are in Hi-Z, TX is disabled VDD Normal operation (internal 11K ohm minimum pull-up applied) Input - 2 level CHSEL 30 Channel Transfer Mode. CHSEL Setting VSS Multi-cast mode Open Direct-connect mode (default) VDD Cross-connect mode Input - 3 level RSVD 2,16,31,34 Other Control Signals Reserved. Do not connect. Table 12 Pin Description (Part 2 of 2) 18 February 8, 2011 IDT 89HP0604SB Data Sheet Package Pinout — 36-QFN Signal Pinout Table 13 lists the pin numbers and signal names for the P0604SB device. Function Pin Function Pin Function Pin A0RXEQ 15 A1TXP 23 B1RXP 20 A0RXN 4 A1TXSW 14 B1TXN 13 A0RXP 3 B0RXEQ 17 B1TXP 12 A0TXN 28 B0RXN 25 B1TXSW 18 A0TXP 29 B0RXP 26 CHSEL 30 A0TXSW 1 B0TXN 7 PDB 35 A1RXEQ 36 B0TXP 6 RSVD 2,16,31,34 A1RXN 10 B0TXSW 32 VDD 5,8,11,21,24,27 A1RXP 9 B1RXEQ 33 A1TXN 22 B1RXN 19 Table 13 Alphabetical Pin List Pin Diagram The following figure lists the pin numbers and the signal names for the 36-QFN package. Figure 13 Pin Diagram — Top View 19 February 8, 2011 IDT 89HP0604SB Data Sheet QFN Package Dimension 20 February 8, 2011 IDT 89HP0604SB Data Sheet Revision History November 2, 2010: Initial publication of final datasheet. February 8, 2011: Removed black packaging options from Order page. 21 February 8, 2011 IDT 89HP0604SB Data Sheet Ordering Information NN A A NN NN AA AA AAA Product Operating Product Speed Chnls Protocol Device Pkg Family Voltage Detail Revision A Legend A = Alpha Character N = Numeric Character N Temp Tape & Range Reel 8 Tape & Reel Blank Commercial Temperature (0°C to +70°C Ambient) Industrial Temperature (-40° C to +85° C Ambient) I NRG NRG36 36-pin QFN, Green ZB ZB revision SB SAS/SATA Interface, “B” version 04 4 Channels 06 6Gbps P rePeater H 1.2V +/- 5% 89 Signal Integrity Product Valid Combinations 89HP0604SBZBNRG8 36-pin Green QFN package, Commercial Temperature 89HP0604SBZBNRGI8 36-pin Green QFN package, Industrial Temperature ® CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for Tech Support: email: [email protected] phone: 408-284-8208 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2011. All rights reserved. 22 February 8, 2011