LM3205 650mA Miniature, Adjustable, Step-Down DC-DC Converter for RF Power Amplifiers General Description Features The LM3205 is a DC-DC converter optimized for powering RF power amplifiers (PAs) from a single Lithium-Ion cell, however they may be used in many other applications. It steps down an input voltage from 2.7V to 5.5V to a variable output voltage from 0.8V(typ.) to 3.6V(typ.). Output voltage is set using a VCON analog input for controlling power levels and efficiency of the RF PA. The LM3205 offers superior performance for mobile phones and similar RF PA applications. Fixed-frequency PWM operation minimizes RF interference. Shutdown function turns the device off and reduces battery consumption to 0.01 µA (typ.). The LM3205 is available in micro SMD package and LLP package. For all other package options contact your local NSC sales office. A high switching frequency (2 MHz) allows use of tiny surfacemount components. Only three small external surface-mount components, an inductor and two ceramic capacitors are required. ■ ■ ■ ■ ■ ■ 2 MHz (typ.) PWM Switching Frequency Operates from a single Li-Ion cell (2.7V to 5.5V) Variable Output Voltage (0.8V to 3.6V) Fast Output Voltage Transient (0.8V to 3.6V in 20µs) 650mA Maximum load capability High Efficiency (96% Typ at 4.2VIN, 3.4VOUT at 400mA) from internal synchronous rectification ■ Current Overload Protection ■ Thermal Overload Protection Packages ■ 8-Pin microSMD (Lead Free) ■ 10-Pin LLP Applications ■ ■ ■ ■ Cellular Phones Hand-Held Radios RF PC Cards Battery Powered RF Devices Typical Application 20158001 FIGURE 1. LM3205 Typical Application © 2009 National Semiconductor Corporation 201580 www.national.com LM3205 650mA Miniature, Adjustable, Step-Down DC-DC Converter for RF Power Amplifiers May 27, 2009 LM3205 Connection Diagrams 20158099 8–Bump Thin Micro SMD Package, Large Bump NS Package Number TLA08GNA 20158004 10–Pin LLP NS Package Number SDA10A Order Information microSMD Order Number Package Marking (Note) Supplied As LM3205TL XTS/32 250 units, Tape-and-Reel LM3205TLX XTS/32 3000 units, Tape-and-Reel Note: The actual physical placement of the package marking will vary from part to part. The package marking “X” designates the date code. “T” is a NSC internal code for die traceability. “S” designates the device type as switcher device. Both will vary considerably. “32” identifies the device (part number, option, etc.). LLP Order Number Package Marking (Note) Supplied As LM3205SD-2 XXXX 1000 units, Tape-and-Reel LM3205SDX-2 YYYY = 3205 4500 units, Tape-and-Reel Note: The actual physical placement of the package marking will vary from part to part. The package marking “XXXXX” is a code for die traceability. “YYYYY” identifies the device (part number, voltage option, etc.). www.national.com 2 LM3205 Pin Descriptions Pin # Name Description 8, 9 PVIN Power Supply Voltage Input to the internal PFET switch. 7 VDD Analog Supply Input. 6 EN Enable Input. Set this digital input high for normal operation. For shutdown, set low. 4 VCON Voltage Control Analog input. VCON controls VOUT in PWM mode. 5 FB Feedback Analog Input. Connect to the output at the output filter capacitor. B3 3 SGND Analog and Control Ground A3 1, 2 PGND Power Ground A2 10 SW Switch node connection to the internal PFET switch and NFET synchronous rectifier. Connect to an inductor with a saturation current rating that exceeds the maximum Switch Peak Current Limit specification of the LM3205. microSMD LLP A1 B1 C1 C2 C3 3 www.national.com LM3205 Maximum Lead Temperature (Soldering, 10 sec) ESD Rating (Notes 4, 13) Human Body Model: Machine Model: Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VDD, PVIN to SGND PGND to SGND EN, FB, VCON −0.2V to +6.0V −0.2V to +0.2V (SGND −0.2V) to (VDD +0.2V) w/6.0V max (PGND −0.2V) to (PVIN +0.2V) w/6.0V max −0.2V to +0.2V SW PVIN to VDD Continuous Power Dissipation (Note 3) Junction Temperature (TJ-MAX) Storage Temperature Range Operating Ratings +260°C 2 kV 200V (Notes 1, 2) Input Voltage Range Recommended Load Current Junction Temperature (TJ) Range Ambient Temperature (TA) Range (Note 5) 2.7V to 5.5V 0mA to 650mA −30°C to +125°C −30°C to +85°C Thermal Properties Internally Limited +150°C −65°C to +150°C Junction-to-Ambient Thermal microSMD Resistance (θJA), microSMD TLA08 Package (Note 6) Junction-to-Ambient Thermal LLP 100°C/W 55°C/W Resistance (θJA), LLP SDA10A Package (Note 6) Electrical Characteristics (Notes 2, 7, 8) Limits in standard typeface are for TA = TJ = 25°C. Limits in boldface type apply over the full operating ambient temperature range (−30°C ≤ TA = TJ ≤ +85°C). Unless otherwise noted, all specifications apply to LM3205TL/LM3205SD with: PVIN = VDD = EN = 3.6V. Symbol Parameter Conditions Min Typ Max Units VFB, MIN Feedback Voltage at minimum setting VCON = 0.32V(Note 8) 0.75 0.8 0.85 V VFB, MAX Feedback Voltage at maximum setting VCON = 1.44V, VIN = 4.2V(Note 8) 3.537 3.6 3.683 V ISHDN Shutdown supply current EN = SW = VCON = 0V, (Note 9) 0.01 2 µA IQ DC bias current into VDD VCON = 2V, FB = 0V, No Switching (Note 10) 1 1.4 mA RDSON(P) micro Pin-pin resistance for PFET ISW = 200mA 140 200 230 mΩ Pin-pin resistance for NFET ISW = -200mA 300 415 485 mΩ RDSON(P)LLP Pin-pin resistance for PFET ISW = 200mA 170 230 260 mΩ RDSON(N)LLP Pin-pin resistance for NFET ISW = -200mA 330 445 515 mΩ ILIM,PFET Switch peak current limit (Note 11) 935 1100 1200 mA FOSC Internal oscillator frequency 1.7 2 2.3 MHz VIH,EN Logic high input threshold 1.2 VIL,EN Logic low input threshold IPIN,EN Pin pull down current ZCON VCON input resistance Gain VCON to VOUT Gain SMD RDSON(N) micro SMD www.national.com V 5 100 0.32V ≤ VCON ≤ 1.44V 4 0.5 V 10 µA kΩ 2.5 V/V The following spec table entries are guaranteed by design providing the component values in the typical application circuit are used. These parameters are not guaranteed by production testing. Min and Max limits apply over the full operating ambient temperature range (−30°C ≤ TA ≤ 85°C) and over the VIN range = 2.7V to 5.5V, TA = 25°C, PVIN = VDD = EN = 3.6V, L = 3.3µH, DCR of L ≤ 100mΩ, CIN = 10µF, 0603, 6.3V (4.7µF||4.7µF, 0603, 6.3V can be used), COUT = 4.7µF, 0603, 6.3V for LM3205TL/LM3205SD unless otherwise noted. Symbol TRESPONSE Typ Max Units Time for VOUT to rise from 0.8V VIN = 4.2V, COUT = 4.7µF, L = 3.3µH, to 3.6V RLOAD = 5.5Ω Parameter Conditions 20 30 µs Time for VOUT to fall from 3.6V to VIN = 4.2V, COUT = 4.7µF, L = 3.3µH, 0.8V RLOAD = 10Ω 20 30 µs 20 pF -3 +3 % -10 10 µA 100 µs CCON VCON input capacitance VCON = 1V, Test frequency = 100 kHz Linearity Linearity in control range 0.32V to 1.44V VIN = 3.9V Monotonic in nature ICON Control pin input current TON Turn on time (time for output to reach 3.6V from Enable low to high transition) Min EN = Low to High, VIN = 4.2V, VO = 3.6V, COUT = 4.7µF, IOUT ≤ 1mA 70 VIN = 3.6V, VOUT = 0.8V, IOUT = 90mA 83 % VIN = 4.2V, VOUT = 3.4V, IOUT = 400mA 96 % VOUT_ripple Ripple voltage, PWM mode VIN = 3V to 4.5V, VOUT = 0.8V, IOUT = 10mA to 400mA (Note 12) 10 mVp-p Line_tr VIN = 600mV perturbance, TRISE = TFALL = 10µs, VOUT = 0.8V, IOUT = 100mA 50 mVpk η Efficiency (L = 3.3µH, DCR ≤ 100mΩ) Line transient response Load_tr Load transient response VIN = 3.1/3.6/4.5V, VOUT = 0.8V, transients up to 100mA, TRISE = TFALL = 10µs 50 mVpk PSRR VIN = 3.6V, VOUT = 0.8V, IOUT = sine wave perturbation frequency = 10kHz, amplitude = 100mVp100mA p 40 dB Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: All voltages are with respect to the potential at the GND pins. The LM3205 is designed for mobile phone applications where turn-on after power-up is controlled by the system controller and where requirements for a small package size overrule increased die size for internal Under Voltage Lock-Out (UVLO) circuitry. Thus, it should be kept in shutdown by holding the EN pin low until the input voltage exceeds 2.7V. Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150°C (typ.) and disengages at TJ = 130°C (typ.). Note 4: The Human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. (MIL-STD-883 3015.7) The machine model is a 200pF capacitor discharged directly into each pin. Note 5: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). Note 6: microSMD:Junction-to-ambient thermal resistance (θJA) is taken from thermal measurements, performed under the conditions and guidelines set forth in the JEDEC standard JESD51-7. A 4 layer, 4" x 4", 2/1/1/2 oz. Cu board as per JEDEC standards is used for the measurements. LLP: The value of (θJA) in LLP-10 could fall in a range of 50°C/W to 150°C/W (if not wider), depending on PWB material, layout, and environmental conditions. In applications where high maximum power dissipation exits (high VIN , high IOUT ), special care must be paid to thermal dissipation areas. For more information on these topics for LLP, refer to Application Note 1187: Leadless Leadframe Package (LLP) and the Power Efficiency and Power Dissipation section of this datasheet Note 7: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm. Due to the pulsed nature of the testing TA = TJ for the electrical characteristics table. Note 8: The parameters in the electrical characteristics table are tested under open loop conditions at PVIN = VDD = 3.6V. For performance over the input voltage range and closed loop results refer to the datasheet curves. Note 9: Shutdown current includes leakage current of PFET. Note 10: IQ specified here is when the part is operating at 100% duty cycle. Note 11: Current limit is built-in, fixed, and not adjustable. Refer to datasheet curves for closed loop data and its variation with regards to supply voltage and temperature. Electrical Characteristic table reflects open loop data (FB = 0V and current drawn from SW pin ramped up until cycle by cycle limit is activated). Closed loop current limit is the peak inductor current measured in the application circuit by increasing output current until output voltage drops by 10%. 5 www.national.com LM3205 System Characteristics LM3205 Note 12: Ripple voltage should measured at COUT electrode on good layout PC board and under condition using suggested inductors and capacitors. Note 13: National Semiconductor recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper ESD handling techniques can result in damage. Typical Performance Characteristics (Circuit in Figure 3, PVIN = VDD = EN = 3.6V, L = 3.3uH, DCR of L ≤ 100mΩ, CIN = 10uF, 0603, 6.3V ( 4.7uF||4.7uF, 0603, 6.3V can be used), COUT = 4.7uF, 0603, 6.3V for LM3205TL/LM3205SD unless otherwise noted) Quiescent Current vs Supply Voltage (VCON = 2V, FB = 0V, No Switching) Shutdown Current vs Temperature (VCON = 0V, EN = 0V) 20158055 20158056 Switching Frequency Variation vs Temperature (VOUT = 1.3V, IOUT = 200mA) Output Voltage vs Supply Voltage (VOUT = 1.3V) 20158057 www.national.com 20158058 6 LM3205 Output Voltage vs Temperature (VIN = 3.6V, VOUT = 0.8V) Output Voltage vs Temperature (VIN = 3.6V, VOUT = 3.4V) 20158059 20158010 Open/Closed Loop Current Limit vs Temperature (PWM mode) VCON Voltage vs Output Voltage (VIN = 4.2V, RLOAD = 8Ω) 20158061 20158062 Efficiency vs Output Voltage (VIN = 3.9V) Efficiency vs Output Current (VOUT = 0.8V) 20158063 20158064 7 www.national.com LM3205 Efficiency vs Output Current (VOUT = 3.4V) Load Transient Response (VOUT = 0.8V) 20158016 20158065 Load Transient Response (VIN = 4.2V, VOUT = 3.4V) Startup (VIN = 3.6V, VOUT = 1.3V, RLOAD = 1kΩ) 20158017 20158084 Startup (VIN = 4.2V, VOUT = 3.4V, RLOAD = 5kΩ) Shutdown Response (VIN = 4.2V, VOUT = 3.4V, RLOAD = 10Ω) 20158085 www.national.com 20158019 8 VCON Voltage Response (VIN = 4.2V, VCON = 0.32V/1.44V, RLOAD = 10Ω) 20158020 20158021 VCON and Load Transient (VIN = 4.2V, VCON = 0.32V/1.44V, 15Ω/8Ω, same time) Timed Current Limit Response (VIN = 3.6V) 20158023 20158022 Output Voltage Ripple (VOUT = 1.3V) Output Voltage Ripple (VOUT = 3.4V) 20158024 20158083 9 www.national.com LM3205 Line Transient Response (VIN = 3.0V to 3.6V, IOUT = 100mA) LM3205 Output Voltage Ripple in Pulse Skip (VIN = 3.64V, VOUT = 3.4V, RLOAD = 5Ω) RDSON vs Temperature (microSMD) (P-ch, ISW = 200mA) 20158025 20158076 RDSON vs Temperature (microSMD) (N-ch, ISW = -200mA) EN High Threshold vs. Vin 20158079 20158077 www.national.com 10 LM3205 Block Diagram 20158035 FIGURE 2. Functional Block Diagram Additional features include current overload protection and thermal overload shutdown. The LM3205 is constructed using a chip-scale 8-pin microSMD or 10-pin LLP package. These packages offers the smallest possible size, for space-critical applications such as cell phones, where board area is an important design consideration. Use of a high switching frequency (2MHz) reduces the size of external components. As shown in Figure 1, only three external power components are required for implementation. Use of a microSMD package requires special design considerations for implementation. (See microSMD Package Assembly and use in the Applications Information section.) Its fine bump-pitch requires careful board design and precision assembly equipment. Use of this package is best suited for opaque-case applications, where its edges are not subject to high-intensity ambient red or infrared light. Also, the system controller should set EN low during power-up and other low supply voltage conditions. (See Shutdown Mode in the Device Information section.) Operation Description The LM3205 is a simple, step-down DC-DC converter optimized for powering RF power amplifiers (PAs) in mobile phones, portable communicators, and similar battery powered RF devices. It is designed to allow the RF PA to operate at maximum efficiency over a wide range of power levels from a single Li-Ion battery cell. It is based on a current-mode buck architecture, with synchronous rectification for high efficiency. It is designed for a maximum load capability of 650mA in PWM mode. Maximum load range may vary from this depending on input voltage, output voltage and the inductor chosen. Efficiency is typically around 96% for a 400mA load with 3.4V output, 4.2V input. The output voltage is dynamically programmable from 0.8V (typ.) to 3.6V (typ.) by adjusting the voltage on the control pin without the need for external feedback resistors. This ensures longer battery life by being able to change the PA supply voltage dynamically depending on its transmitting power. 11 www.national.com LM3205 20158036 FIGURE 3. Typical Operating System Circuit Before appearing at the PWM comparator, a slope compensation ramp from the oscillator is subtracted from the error signal for stability of the current feedback loop. The minimum on time of PFET is 50ns (typ.) Circuit Operation Referring to Figure 1 and Figure 2, the LM3205 operates as follows. During the first part of each switching cycle, the control block in the LM3205 turns on the internal PFET (Pchannel MOSFET) switch. This allows current to flow from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a ramp with a slope of around (VIN - VOUT) / L, by storing energy in a magnetic field. During the second part of each cycle, the controller turns the PFET switch off, blocking current flow from the input, and then turns the NFET (N-channel MOSFET) synchronous rectifier on. In response, the inductor’s magnetic field collapses, generating a voltage that forces current from ground through the synchronous rectifier to the output filter capacitor and load. As the stored energy is transferred back into the circuit and depleted, the inductor current ramps down with a slope around VOUT / L. The output filter capacitor stores charge when the inductor current is high, and releases it when low, smoothing the voltage across the load. The output voltage is regulated by modulating the PFET switch on time to control the average current sent to the load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and synchronous rectifier at SW to a low-pass filter formed by the inductor and output filter capacitor. The output voltage is equal to the average voltage at the SW pin. While in operation, the output voltage is regulated by switching at a constant frequency and then modulating the energy per cycle to control power to the load. Energy per cycle is set by modulating the PFET switch on-time pulse width to control the peak inductor current. This is done by comparing the signal from the current-sense amplifier with a slope compensated error signal from the voltage-feedback error amplifier. At the beginning of each cycle, the clock turns on the PFET switch, causing the inductor current to ramp up. When the current sense signal ramps past the error amplifier signal, the PWM comparator turns off the PFET switch and turns on the NFET synchronous rectifier, ending the first part of the cycle. If an increase in load pulls the output down, the error amplifier output increases, which allows the inductor current to ramp higher before the comparator turns off the PFET. This increases the average current sent to the output and adjusts for the increase in the load. www.national.com Shutdown Mode Setting the EN digital pin low (<0.5V) places the LM3205 in a 0.01µA (typ.) Shutdown mode. During shutdown, the PFET switch, NFET synchronous rectifier, reference voltage source, control and bias circuitry of the LM3205 are turned off. Setting EN high (>1.2V) enables normal operation. EN should be set low to turn off the LM3205 during power-up and under voltage conditions when the power supply is less than the 2.7V minimum operating voltage. The LM3205 is designed for compact portable applications, such as mobile phones. In such applications, the system controller determines power supply sequencing and requirements for small package size outweigh the additional size required for inclusion of UVLO (Under Voltage Lock-Out) circuitry. Internal Synchronous Rectification While in PWM mode, the LM3205 uses an internal NFET as a synchronous rectifier to reduce rectifier forward voltage drop and associated power loss. Synchronous rectification provides a significant improvement in efficiency whenever the output voltage is relatively low compared to the voltage drop across and ordinary rectifier diode. With medium and heavy loads, the internal NFET synchronous rectifier is turned on during the inductor current down slope in the second part of each cycle. The synchronous rectifier is turned off prior to the next cycle. The NFET is designed to conduct through its intrinsic body diode during transient intervals before it turns on, eliminating the need for an external diode. Current Limiting A current limit feature allows the LM3205 to protect itself and external components during overload conditions. In PWM mode, an 1200mA (max.) cycle-by-cycle current limit is normally used. If an excessive load pulls the output voltage down to approximately 0.375V, then the device switches to a timed current limit mode. In timed current limit mode the internal PFET switch is turned off after the current comparator trips and the beginning of the next cycle is inhibited for 3.5us to 12 an inductor with the lowest acceptable limit (as of Nov./05). Table 1 suggests some inductors and suppliers. TABLE 1. Suggested inductors and their suppliers Model Dynamically Adjustable Output Voltage The LM3205 features dynamically adjustable output voltage to eliminate the need for external feedback resistors. The output can be set from 0.8V(typ.) to 3.6V(typ.) by changing the voltage on the analog VCON pin. This feature is useful in PA applications where peak power is needed only when the handset is far away from the base station or when data is being transmitted. In other instances the transmitting power can be reduced. Hence the supply voltage to the PA can be reduced, promoting longer battery life. See Setting the Output Voltage in the Application Information section for further details. Size (WxLxH) [mm] Vendor NR3015T3R3M 3.0 x 3.0 x 1.5 TaiyoYuden DO3314-332MXC 3.3 x 3.3 x 1.4 Coilcraft If a smaller inductance inductor is used in the application, the LM3205 may become unstable during line and load transients and VCON transient response times may get affected. For low-cost applications, an unshielded bobbin inductor is suggested. For noise-critical applications, a toroidal or shielded-bobbin inductor should be used. A good practice is to lay out the board with footprints accommodating both types for design flexibility. This allows substitution of a low-noise toroidal inductor, in the event that noise from low-cost bobbin models is unacceptable. Saturation occurs when the magnetic flux density from current through the windings of the inductor exceeds what the inductor’s core material can support with a corresponding magnetic field. This can cause poor efficiency, regulation errors or stress to a DC-DC converter like the LM3205. Thermal Overload Protection The LM3205 has a thermal overload protection function that operates to protect itself from short-term misuse and overload conditions. When the junction temperature exceeds around 150°C, the device inhibits operation. Both the PFET and the NFET are turned off in PWM mode. When the temperature drops below 125°C, normal operation resumes. Prolonged operation in thermal overload conditions may damage the device and is considered bad practice. CAPACITOR SELECTION The LM3205 is designed for use with ceramic capacitors for its input and output filters. Use a 10µF ceramic capacitor for input and a 4.7µF ceramic capacitor for output. They should maintain at least 50% capacitance at DC bias and temperature conditions. Ceramic capacitors types such as X5R, X7R are recommended for both filters. These provide an optimal balance between small size, cost, reliability and performance for cell phones and similar applications. Table 2 lists some suggested part numbers and suppliers. DC bias characteristics of the capacitors must be considered when selecting the voltage rating and case size of the capacitor. A few manufactures can supply 4.7µF capacitors in the 0805 case size which maintain at least 50% of their value, but TDK is currently the only manufacturer which can provide such capacitors in the 0603 case size. As of November, 2005, no manufacture can supply 10µF capacitors in the 0603 case size which maintain 50% of their value. If it is necessary to choose a 0603-size capacitor for VIN, the operation of the LM3205 should be carefully evaluated on the system board. Output capacitors with smaller case sizes mitigate piezo electric vibrations when the output voltage is stepped up and down at fast rates. However, they have a larger percentage drop in value with dc bias. Use of multiple 2.2µF or 1µF capacitors in parallel may also be considered. Application Information SETTING THE OUTPUT VOLTAGE The LM3205 features a pin-controlled variable output voltage to eliminate the need for external feedback resistors. It can be programmed for an output voltage from 0.8V (typ.) to 3.6V (typ.) by setting the voltage on the VCON pin, as in the following formula: VOUT = 2.5 x VCON When VCON is between 0.32V and 1.44V, the output voltage will follow proportionally by 2.5 times of VCON. If VCON is over 1.44V (VOUT = 3.6V), sub-harmonic oscillation may occur because of insufficient slope compensation. If VCON voltage is less than 0.32V (VOUT = 0.8V), the output voltage may not be regulated due to the required on-time being less than the minimum on-time (50ns). The output voltage can go lower than 0.8V providing a limited VIN range is used. Refer to datasheet curve (VCON Voltage vs Output Voltage) for details. This curve is for a typical part and there could be part-to-part variation for output voltages less than 0.8V over the limited VIN range. TABLE 2. Suggested capacitors and their suppliers INDUCTOR SELECTION A 3.3µH inductor with saturation current rating over 1200mA and low inductance drop at the full DC bias condition is recommended for almost all applications. The inductor’s DC resistance should be less than 0.2Ω for good efficiency. For low dropout voltage, lower DCR inductors are advantageous. The lower limit of acceptable inductance is 2.3µH at 1200mA over the operating temperature range. Full attention should be paid to this limit, because some small inductors show large inductance drops at high DC bias. These can not be used with the LM3205. Taiyo-Yuden NR3015T3R3M is an example of Model Vendor 0805ZD475KA 4.7µF, 10V AVX C1608X5R0J475M, 4.7µF, 6.3V TDK C2012X5R0J106M,10µF, 6.3V TDK The input filter capacitor supplies AC current drawn by the PFET switch of the LM3205 in the first part of each cycle and reduces the voltage ripple imposed on the input power source. The output filter capacitor absorbs the AC inductor current, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR (Equivalent Series Resistance) to per- 13 www.national.com LM3205 force the instantaneous inductor current to ramp down to a safe value. The synchronous rectifier is off in timed current limit mode. Timed current limit prevents the loss of current control seen in some products when the output voltage is pulled low in serious overload conditions. LM3205 form these functions. The ESR of the filter capacitors is generally a major factor in voltage ripple. ners. Initially, the trace to each pad should be 7mil wide, for a section approximately 7mil long, as a thermal relief. Then each trace should neck up or down to its optimal width. The important criterion is symmetry. This ensures the solder bumps on the LM3205 re-flow evenly and that the device solders level to the board. In particular, special attention must be paid to the pads for bumps A1, A3 and B3. Because PGND and PVIN are typically connected to large copper planes, inadequate thermal relief’s can result in late or inadequate reflow of these bumps. The microSMD package is optimized for the smallest possible size in applications with red or infrared opaque cases. Because the microSMD package lacks the plastic encapsulation characteristic of larger devices, it is vulnerable to light. Backside metallization and/or epoxy coating, along with front-side shading by the printed circuit board, reduce this sensitivity. However, the package has exposed die edges. In particular, microSMD devices are sensitive to light, in the red and infrared range, shining on the package’s exposed die edges. EN PIN CONTROL Drive the EN pin using the system controller to turn the LM3205 ON and OFF. Use a comparator, Schmidt trigger or logic gate to drive the EN pin. Set EN high (>1.2V) for normal operation and low (<0.5V) for a 0.01µA (typ.) shutdown mode. Set EN low to turn off the LM3205 during power-up and under voltage conditions when the power supply is less than the 2.7V minimum operating voltage. The part is out of regulation when the input voltage is less than 2.7V. The LM3205 is designed for mobile phones where the system controller controls operation mode for maximizing battery life and requirements for small package size outweigh the additional size required for inclusion of UVLO (Under Voltage Lock-Out) circuitry. microSMD PACKAGE ASSEMBLY AND USE Use of the microSMD package requires specialized board layout, precision mounting and careful re-flow techniques, as detailed in National Semiconductor Application Note 1112. Refer to the section Surface Mount Technology (SMD) Assembly Considerations. For best results in assembly, alignment ordinals on the PC board should be used to facilitate placement of the device. The pad style used with microSMD package must be the NSMD (non-solder mask defined) type. This means that the solder-mask opening is larger than the pad size. This prevents a lip that otherwise forms if the soldermask and pad overlap, from holding the device off the surface of the board and interfering with mounting. See Application Note 1112 for specific instructions how to do this. The 8-Bump package used for LM3205 has 300micron solder balls and requires 10.82mil pads for mounting on the circuit board. The trace to each pad should enter the pad with a 90° entry angle to prevent debris from being caught in deep cor- www.national.com LLP PACKAGE ASSEMBLY AND USE Use of the LLP package requires specialized board layout, precision mounting and careful re-flow techniques, as detailed in National Semiconductor Application Note 1187. Refer to the section Surface Mount Technology (SMT) Assembly Recommendations. For best results in assembly, alignment ordinals on the PC board should be used to facilitate placement of the device and must attach to the DAP(Die Attach Pad) of the LLP package. The pad style used with LLP package must be the NSMD (non-solder mask defined) type. This means that the solder-mask opening is larger than the pad size. This prevents a lip that otherwise forms if the soldermask and pad overlap, from holding the device off the surface of the board and interfering with mounting. See Application Note 1187 for specific instructions how to do this. 14 LM3205 Board Layout Considerations 20158008 FIGURE 4. Current Loop The LM3205 converts higher input voltage to lower output voltage with high efficiency. This is achieved with an inductorbased switching topology. During the first half of the switching cycle, the internal PMOS switch turns on, the input voltage is applied to the inductor, and the current flows from PVDD line to the output capacitor (C2) through the inductor. During the second half cycle, the PMOS turns off and the internal NMOS turns on. The inductor current continues to flow via the inductor from the device PGND line to the output capacitor (C2). Referring toFigure 4 , the LM3205 has two major current loops where pulse and ripple current flow. The loop shown in the left hand side is most important, because pulse current shown inFigure 4 flows in this path. The right hand side is next. The current waveform in this path is triangular, as shown in Figure 4 . Pulse current has many high-frequency components due to fast di/dt. Triangular ripple current also has wide high-frequency components. Board layout and circuit pattern design of these two loops are the key factors for reducing noise radiation and stable operation. Other lines, such as from battery to C1(+) and C2(+) to load, are almost DC current, so it is not necessary to take so much care. Only pattern width (current capability) and DCR drop considerations are needed. 20158009 FIGURE 5. Evaluation Board Layout for microSMD 3. BOARD LAYOUT FLOW (microSMD) 1. Minimize C1, PVIN, and PGND loop. These traces should be as wide and short as possible. This is most important. 2. Minimize L1, C2, SW and PGND loop. These traces also should be wide and short. This is the second priority. 15 Above layout patterns should be placed on the component side of the PCB to minimize parasitic inductance and resistance due to via-holes. It may be a good idea that the SW to L1 path is routed between C2 (+) and C2(-) land patterns. If vias are used in these large current paths, multiple via-holes should be used if possible. www.national.com LM3205 4. 5. 6. Connect C1(-), C2(-) and PGND with wide GND pattern. This pattern should be short, so C1(-), C2(-), and PGND should be as close as possible. Then connect to a PCB common GND pattern with as many via-holes as possible. SGND should not connect directly to PGND. Connecting these pins under the device should be avoided. (If possible, connect SGND to the common port of C1(-), C2 (-) and PGND.) 7. VDD should not be connected directly to PVIN. Connecting these pins under the device should be avoided. It is good idea to connect VDD to the C1(+) to avoid switching noise injection to the VDD line. FB line should be protected from noise. It is a good idea to use an inner GND layer (if available) as a shield. 20158032 FIGURE 6. Evaluation Board for LLP 5. BOARD LAYOUT FLOW (LLP) 1. Minimize C1, PVIN, and PGND loop. These traces should be as wide and short as possible. This is most important. 2. Minimize L1, C2, SW and PGND loop. These traces also should be wide and short. This is the second priority. 3. Above layout patterns should be placed on the component side of the PCB to minimize parasitic inductance and resistance due to via-holes. It may be a good idea that the SW to L1 path is routed between C2 (+) and C2(-) land patterns. If vias are used in these large current paths, multiple via-holes should be used if possible. 4. Connect C1(-), C2(-) and PGND with wide GND pattern. This pattern should be short, so C1(-), C2(-), and PGND should be as close as possible. Then connect to a PCB common GND pattern with as many via-holes as possible. www.national.com 6. 7. SGND should connect directly to PGND through a single common via as close to C1 as possible. Connecting these pins under the LLP device on a different layer should be avoided. VDD should not be connected directly to PVIN. Connecting these pins under the device should be avoided. It is good idea to connect VDD to the C1(+) to avoid switching noise injection to the VDD line. FB line should be protected from noise. It is a good idea to use an inner GND layer (if available) as a shield. Note: The evaluation board shown inFigure 5and Figure 6 for the LM3205TL/LM3205SD were designed with these considerations, and it shows good performance. However some aspects have not been optimized because of limitations due to evaluation-specific requirements. The board can be used as a reference, but it is not the best. Please refer questions to a National representative. 16 LM3205 Physical Dimensions inches (millimeters) unless otherwise noted 8-Bump Thin Micro SMD, Large Bump X1 = 1.666mm ± 0.030mm X2 = 1.819mm ±0.030mm X3 = 0.600mm ±0.075mm NS Package Number TLA08GNA 10-Pin LLP NS Package Number SDA10A 17 www.national.com LM3205 650mA Miniature, Adjustable, Step-Down DC-DC Converter for RF Power Amplifiers Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Design Support Amplifiers www.national.com/amplifiers WEBENCH® Tools www.national.com/webench Audio www.national.com/audio App Notes www.national.com/appnotes Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns Data Converters www.national.com/adc Samples www.national.com/samples Interface www.national.com/interface Eval Boards www.national.com/evalboards LVDS www.national.com/lvds Packaging www.national.com/packaging Power Management www.national.com/power Green Compliance www.national.com/quality/green Switching Regulators www.national.com/switchers Distributors www.national.com/contacts LDOs www.national.com/ldo Quality and Reliability www.national.com/quality LED Lighting www.national.com/led Feedback/Support www.national.com/feedback Voltage Reference www.national.com/vref Design Made Easy www.national.com/easy www.national.com/powerwise Solutions www.national.com/solutions Mil/Aero www.national.com/milaero PowerWise® Solutions Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors SolarMagic™ www.national.com/solarmagic Wireless (PLL/VCO) www.national.com/wireless www.national.com/training PowerWise® Design University THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS. EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. Copyright© 2009 National Semiconductor Corporation For the most current product information visit us at www.national.com National Semiconductor Americas Technical Support Center Email: [email protected] Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Technical Support Center Email: [email protected] National Semiconductor Asia Pacific Technical Support Center Email: [email protected] National Semiconductor Japan Technical Support Center Email: [email protected]