ARA2004 Address-Programmable Reverse Amplifier with Step Attenuator Data Sheet - rev 2.2 features • Low cost integrated amplifier with Step Attenuator • Attenuation Range: 0 - 59 dB, adjustable in 1 dB increments via a 3-wire Serial Control • Meets DOCSIS distortion requirements at a +60 dBmV output signal level • Low distortion and low noise • Frequency range: 5 - 100 MHz • 5 Volt Operation • -40 to +85 8C temperature range • RoHS Compliant Package Option Applications S12 Package 28-Pin SSOP with Heat Slug • MCNS/DOCSIS Compliant Cable Modems • CATV Interactive Set-Top Box • Telephony over Cable Systems • OpenCable Set-Top Box • Residential Gateway PRODUCT DESCRIPTION The ARA2004 is designed to provide the reverse path amplification and output level control functions in a CATV Set-Top Box or Cable Modem. It incorporates a digitally controlled precision step attenuator that is preceded by an ultra low noise amplifier stage, and followed by an ultra-linear output driver amplifier. This device uses a balanced circuit design that exceeds the MCNS/DOCSIS requirement for harmonic performance at a +60 dBmV output level while only requiring a single polarity +5 V supply. Both the input and output are matched to 75 ohms with an appropriate transformer. The precision attenuator provides up to 58 dB of attenuation in 1 dB increments via a three-wire serial interface. With external passive components, this device meets IEC 1000-4-12 and ANSI/IEEE C62.411991 100KHz ringwave tests, as well as IEC1000-4-5 1.2/50 µS surge tests. The ARA2004 is offered in a 28-pin SSOP package featuring a heat slug on the bottom of the package. Clock Data Enable Balun Upstream QPSK/16QAM Modulator Low Pass Filter ARA2000 Transmit Enable/Disable 2 5-42 MHz Clock Address Control Diplexer 54-860 MHz DoubleConversion Tuner SAW Filter QAM Receiver with FEC ROM Data Microcontroller with Ethernet MAC MAC Clock 44 MHz RAM Data 10Base-T Transceiver Figure 1: Functional Block Diagram for DOCSIS 3.0 Application 04/2011 RJ45 Connector ARA2004 GaAs IC ATTOUT (+) ATTIN (+) A1OUT (+) A2IN (+) A1IN (+) ISET1 Vg1 32 dB 16 dB 8 dB 4 dB 2 dB A2OUT (+) 1 dB ISET2 EFET EFET A1IN (-) A2OUT (-) A1OUT (-) A2IN (-) ATTIN (-) ATTOUT (-) 32 dB 16 dB 8 dB 4 dB 2 dB 1 dB P5 P4 P3 P2 P1 P0 Buffer Clock Data 8 8-Bit Shift Register/ Address Control Latch Enable CMOS IC (Serial to Parallel Interface) Figure 2: Functional Block Diagram 1 GND GND 28 2 VATTN N/C 27 3 ATTIN (+) ATTOUT (+) 26 4 A1OUT (+) A2IN (+) 25 5 A1IN (+) A2OUT (+) 24 6 Vg1 Vg2 23 7 ISET1 8 A1IN (-) 9 ISET2 22 A2OUT (-) 21 A1OUT (-) A2IN (-) 20 10 ATTIN (-) ATTOUT (-) 19 11 VCMOS GNDCMOS 18 12 CLK N/C 17 13 DAT C1 16 14 EN C0 15 Figure 3: Pin Out 2 Vg2 Data Sheet- Rev 2.2 04/2011 ARA2004 Table 1: Pin Description pin nAMe 1 GND 2 DescRiption pin nAMe Ground 15 N/C No Connection (1) VATTN Supply Attenuator 16 N/C No Connection (1) 3 ATTIN (+) Attenuator (+) Input 17 N/C No Connection (1) 4 A1Out (+) Amplifier A1 (+) Output 18 GNDCMOS Ground for Digital CMOS Circuit 5 A1IN (+) Amplifier A1 (+) Input 19 ATTOUT (-) Attenuator (-) Output (2) 6 Vg1 Amplifier A1 (+/-) Control 20 A2IN (-) Amplifier A2 (-) Input (2) 7 ISET1 Amplifier A1 (+/-) Current Adjust 21 A2OUT (-) Amplifier A2 (-) Output 8 A1IN (-) Amplifier A1 (-) Input 22 ISET2 Amplifier A2 (+/-) Current Adjust 9 A1OUT (-) Amplifier A1 (-) Output 23 Vg2 Amplifier A2 (+/-) Control 10 ATTIN (-) Attenuator (-) Input (2) 24 A2OUT (+) Amplfiier A2 (+) Output 11 VCMOS Supply For Digital CMOS Circuit 25 A2IN (+) Amplifier A2 (+) Input (2) 12 CLK Clock 26 ATTOUT (+) Attenuator (+) Output (2) 13 DAT Data 27 N/C No Connection (1) 14 EN Enable 28 GND Ground (2) (2) (2) DescRiption Notes: (1) All N/C pins should be grounded. (2) Pins should be AC-coupled. No external DC bias should be applied. Data Sheet- Rev 2.2 04/2011 3 ARA2004 ELECTRICAL CHARACTERISTICS Table 2: Absolute Minimum and Maximum Ratings pARAMeteR Min MAX unit Analog Supply (pins 2, 4, 9, 21, 24) 0 9 VDC Digital Supply: VCMOS (pin 11) 0 6 VDC Amplifier Controls: Vg1, Vg2 (pins 6, 23) -5 2 V RF Power at Inputs ( pins 5, 8) - +60 dBmV Digital Interface (pins 12, 13, 14) -0.5 VCMOS+0.5 V Storage Temperature -55 +200 8C Soldering Temperature - 260 8C Soldering TIme - 5 Sec Stresses in excess of the absolute ratings may cause permanent damage. Functional operation is not implied under these conditions. Exposure to absolute ratings for extended periods of time may adversely affect reliability. Notes: (1) Pins 3, 5, 8, 10, 19, 20, 25, 26 should be AC-coupled. No external DC bias should be applied. (2) Pins 7 and 22 should be grounded or pulled to ground through a resistor. No external DC bias Table 3: Operating Ranges pARAMeteR Min tYp MAX unit Amplifier Supply: VDD (pins 4, 9, 21, 24) 4.5 5 7 VDC VDD-0.5 5 7 VDC 3.0 - 5.5 VDC Digital Interface 0 - VCMOS V Amplifier Controls Vg1, Vg1 (pins 6, 23) -5 1 2 V Case Temperature -40 25 85 8C Attenuator Supply: VATTN (pin 2) Digital Supply: VCMOS (pin 11) The device may be operated safely over these conditions; however, parametric performance is guaranteed only over the conditions defined in the electrical specifications. 4 Data Sheet- Rev 2.2 04/2011 ARA2004 Table 4: DC Electrical Specifications TA = 25 8C; VDD, VATTN, VCMOS = +5.0 VDC; Vg1, Vg2 = +1.0 V (Tx enabled); Vg1, Vg2 = 0 V (Tx disabled) pARAMeteR Min tYp MAX unit coMMents Amplifier A1 Current (pins 4, 9) - 48 2.4 80 6 mA Tx enabled Tx disabled Amplifier A2 Current (pins 21, 24) - 77 3.7 120 9 mA Tx enabled Tx disabled Attenuator Current (pin 2) - 9 15 mA Total Power Consumption - 0.67 75 1.08 150 w mW Thermal Resistance (JC) - 38 - 8C/W Tx enabled Tx disabled Table 5a: AC Electrical Specifications TA = 25 8C; VDD, VATTN, VCMOS = +5.0 VDC; Vg1, Vg2 = +1.0 V (Tx enabled); Vg1, Vg2 = 0 V (Tx disabled) pARAMeteR Min tYp MAX unit Gain (10 MHz) 27.5 29.3 30.5 dB 0 dB attenuation setting Gain Flatness - 0.75 1.5 - dB 5 to 42 MHz 5 to 65 MHz Gain Variation over Temperature - -0.006 - dB/8C 0.65 1.6 3.6 7.5 15.0 30.2 0.83 1.70 3.75 7.75 15.40 30.75 1.00 2.05 4.0 8.0 15.8 31.3 58.6 60.3 - dB 2nd Harmonic Distorion Level (10 MHz) - -75 -53 dBc +60 dBmV into 75 Ohms 3rd Harmonic Distorion Level (10 MHz) - -60 -53 dBc +60 dBmV into 75 Ohms 78 - - dBmV 1 dB Gain Compression Point - 68.5 - dBmV Noise Figure - 3.0 4.0 dB Attenuation Steps: 1 2 4 8 16 32 dB dB dB dB dB dB Maximum Attenuation 3rd Order Output Intercept dB coMMents Monotonic Includes input balun loss Note: As measured in ANADIGICS test fixture. Data Sheet- Rev 2.2 04/2011 5 ARA2004 Table 5b: AC Electrical Specifications (Continued) TA = 25 8C; VDD, VATTN, VCMOS = +5.0 VDC; Vg1, Vg2 = +1.0 V (Tx enabled); Vg1, Vg2 = 0 V (Tx disabled) pARAMeteR Min tYp MAX unit coMMents Output Noise Power Active / No Signal / Min. Atten. Set. Active / No Signal / Max. Atten. Set. - - -38.5 -53.8 dBmV Any 160 kHz bandwidth from 5 to 42 MHz Isolation (45 MHz) in Tx disable mode - 65 - dB Difference in output signal between Tx enable and Tx disable Differential Input Impedance - 300 - Ohms between pins 5 and 8 (Tx enabled) Input Impedance - 75 - Ohms with transformer (Tx enabled) Input Return Loss (75 Ohm characteristic impedance) - -20 -5 -12 - dB Differential Output Impedance - 300 - Ohms between pins 21 and 24 Output Impedance - 75 - Ohms with transformer Output Return Loss (75 Ohm characteristic impedance) - -17 -15 -12 -10 dB Output Voltage Transient Tx enable / Tx disable - 4 100 7 mVp-P Note: As measured in ANADIGICS test fixture. 6 Data Sheet- Rev 2.2 04/2011 Tx enabled Tx disabled Tx enabled Tx disabled 0 dB attenuator setting 24 dB attenuator setting RF Input (75 Ohms) 1.2K Ohms Turns Ratio 1:2 2K Ohms 2K Ohms 1000pF 3.9 Ohms 1000pF 10uH +5 V 0.1uF 0.1uF +5 V 1uF 10uH 1000pF 0.1uF 1uF 1000pF 1.2K Ohms 470pF 1K Ohms 1uF Clock Data Sheet- Rev 2.2 04/2011 Data +5 V Enable Control A1 0 / +3 V 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ARA2000 A2OUT (+) A1IN (+) GNDCMOS EN DAT C0 C1 N/C ATTOUT (-) ATTIN (-) VCMOS CLK A2IN (-) A1OUT (-) ISET2 A2OUT (-) A1IN (-) ISET1 Vg2 A2IN (+) Vg1 27 28 15 16 17 18 19 20 21 22 23 24 25 ATTOUT (+) 26 N/C GND A1OUT (+) ATTIN (+) VATTN GND 470pF 1K Ohms Turns Ratio 2:1 0.1uF 1uF Toko Balun 616PT-1030 +5 V 1500pF RF Output (75 Ohms) Note: Pins 15 and 16 are grounded on the ANADIGICS test fixture, identifying device address "00". Note: Tx Enable: Control A1 and Control A2 = +3V Tx Disable: Control A1 and Control A2 = 0V 470pF 470pF 2K Ohms 2K Ohms Control A2 0 / +3 V ARA2004 Figure 4: Test Circuit 7 Attenuation (dB) ARA2004 Figure 5: Attenuation Level vs Control Word 64 60 56 52 48 44 40 36 32 28 24 20 16 12 8 4 0 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 control Word Figure 6: Gain & Noise Figure vs Frequency Gain (dB) noise figure 8 30 7 25 6 20 5 15 4 10 3 5 nf (dB) Gain 35 2 10 30 50 70 90 frequency (MHz) Figure 7: Gain & Noise Figure vs VDD GAin (dB) noise figure 6 32 5 29 4 26 3 23 2 Measured @ 30 MHz 20 1 3 4 5 VDD ( Volts ) 8 Data Sheet- Rev 2.2 04/2011 6 7 nf (dB) Gain 35 ARA2004 Figure 8: Gain & Noise Figure vs Temperature 6 32 5 29 4 26 3 23 2 Measured @ 30 MHz 20 1 -40 -25 -10 5 20 35 50 65 80 o temperature (c ) Figure 9: Harmonic Distortion vs VDD POUT = 58 dBmV 2nd Harmonic -20 Harmonic level (dBc) 3rd Harmonic -30 -40 -50 -60 -70 Measured @ 5 MHz -80 3 4 5 6 7 VDD ( Volts ) Figure 10: Harmonic Distortion vs VDD POUT = 58 dBmV 2nd Harmonic -20 3rd Harmonic -30 Harmonic level (dBc) GAin (dB) noise figure nf (dB) Gain 35 -40 -50 -60 -70 Measured @ 12 MHz -80 3 4 5 6 7 VDD ( Volts ) Data Sheet- Rev 2.2 04/2011 9 ARA2004 Figure 11: Harmonic Distortion vs Temperature POUT = 58 dBmV 2nd Harmonic -40 3rd Harmonic Harmonic level (dBc) -45 -50 -55 -60 -65 -70 -75 Measured @ 5 MHz -80 -40 -25 -10 5 20 35 50 65 80 o temperature (c ) Figure 12: Harmonic Distortion vs Power Out 2nd -30 3rd -35 Harmonics (dBc) -40 -45 -50 -55 -60 -65 -70 -75 49 51 53 55 57 59 61 63 pout (dBmV) Figure 13: Transients vs Attenuation POUT = 55 dBmV at 0 dB attenuation ARA2000 10 Data Sheet- Rev 2.2 04/2011 65 67 ARA2004 Figure 14: Harmonic Performance over Frequency POUT =+62 dBmV 2nd Harmonic -50 3rd Harmonic Harmonic level (dBc) -52 -54 -56 -58 -60 -62 -64 -66 -68 -70 -72 5 15 20 frequency (MHz) 25 30 35 40 Figure 15: IIP2 & IIP3 vs Frequency iip2 iip3 40 14 36 12 32 10 28 8 24 6 Measured @ V DD = 5 Volts Pin = -20 dBm per tone 20 5 15 25 35 45 55 65 75 85 4 95 frequency (MHz) Figure 16: IIP2 & IIP3 vs VDD iip3 15 36 11 32 7 28 3 24 -1 Measured @ 65 MHz Two tones @ 29.5 MHz & 35.5 MHz 20 3 4 5 VDD (Volts) Data Sheet- Rev 2.2 04/2011 6 iip3 (dBm) iip2 40 iip2 (dBm) iip2 (dBm) 10 iip3 (dBm) 0 -5 7 11 ARA2004 LOGIC PROGRAMMING Programming Instructions The programming word is set through an 8 bit shift register via the data, clock and enable lines. The data is entered in order with the most significant bit (MSB) first and the least significant bit (LSB) last. The enable line must be low for the duration of the data entry, then set high to latch the shift register. The rising edge of the clock pulse shifts each data value into the register. Software is Available from ANADIGICS Application Engineering to set the data bits through the serial cable on the ARA2004 evaluation board. Table 6: Programming Register DAtA Bit D7 D6 D5 D4 D3 D2 D1 D0 function P7 P6 P5 P4 P3 P2 P1 P0 Table 7: Data Description 12 VAlue function (1 = on, 0 = bypass) P7 N/A P6 N/A P5 32 dB Atenuator Bit P4 16 dB Attenuator Bit P3 8 dB Attenuator Bit P2 4 dB Attenuator Bit P1 2 dB Attenuator Bit P0 1 dB Attenuator Bit Data Sheet- Rev 2.2 04/2011 ARA2004 Table 8: Digital Interface Specification pARAMeteR Min tYp MAX unit Logic High Input: VH 2.0 - - V Logic Low Input: VL - - 0.8 V Logic Input Current Consumption - - 0.01 mA Data to Clock Set Up Time: tCS 50 - - ns Data to Clock Hold Time: tCH 10 - - ns Clock Pulse Width High: tCWH 50 - - ns Clock Pulse Width Low: tCWL 50 - - ns Clock to Load Enable Setup Time: tES 50 - - ns Load Enable Pulse Width: tEW 50 - - ns Rise Time: tR - 10 - ns Fall Time: tF - 10 - ns DATA D7 : MSB D6 D4 D3 D1 D0: LSB CLOCK tCWL ENABLE OR tCS tCH tCWH tES tEW ENABLE Figure 17: Serial Data Input Timing Data Sheet- Rev 2.2 04/2011 13 ARA2004 APPLICATION INFORMATION Transmit Enable / Disable The ARA2004 includes two amplification stages that each can be shut down through external control pins Vg1 and Vg2 (pins 6 and 23, respectively.) By applying a slightly positive bias of typically +1.0 Volts, the amplifier is enabled. In order to disable the amplifier, the control pin needs to be pulled to ground. A practical way to implement the necessary control is to use bias resistor networks similar to those shown in the test circuit schematic (Figure 4.) Each network includes a resistor shunted to ground that serves as a pull-down to disable the amplifier when no control voltage is applied. When a positive voltage is applied, the network acts as a voltage divider that presents the required +1.0 Volts to enable the amplifier. By selecting different resistor values for the voltage divider, the network can accommodate different control voltage inputs. The Vg1 and Vg2 pins may be connected together directly, and controlled through a single resistor network from a common control voltage. Amplifier Bias Current The Iset pins (7 and 22) set the bias current for the amplification stages. Grounding these pins results in the maximum possible current. By placing a resistor from the pin to ground, the current can be reduced. The recommended bias conditions use the configuration shown in the test circuit schematic in Figure 4. Thermal Layout Considerations The device package for the ARA2004 features a heat slug on the bottom of the package body. Use of the heat slug is an integral part of the device design. Soldering this slug to the ground plane of the PC board will ensure the lowest possible thermal resistance for the device, and will result in the longest MTF (mean time to failure.) A PC board layout that optimizes the benefits of the heat slug is shown in Figure 18. The via holes located under the body of the device must be plated through to a ground plane layer of metal, in order to provide a sufficient heat sink. The recommended solder mask outline is shown in Figure 19. Figure 18: PC Board Layout 14 Data Sheet- Rev 2.2 04/2011 ARA2004 Output Transformer Matching the output of the ARA2004 to a 75 Ohm load is accomplished using a 2:1 turns ratio transformer. In addition to providing an impedance transformation, this transformer provides the bias to the output amplifier stage via the center tap. The transformer also cancels even mode distortion products and common mode signals, such as the voltage transients that occur while enabling and disabling the amplifiers. As a result, care must be taken when selecting the transformer to be used at the output. It must be capable of handling the RF and DC power requirements without saturating the core, and it must have adequate isolation and good phase and amplitude balance. It also must operate over the desired frequency and temperature range for the intended application. ESD Sensitivity Electrostatic discharges can cause permanent damage to this device. Electrostatic charges accumulate on test equipment and the human body, and can discharge without detection. Although the ARA2004 has some built-in ESD protection, proper precautions and handling are strongly recommended. Refer to the ANADIGICS application note on ESD precautions. Figure 19: Solder Mask Outline Data Sheet- Rev 2.2 04/2011 15 ARA2004 Figure 20: S12 Package Outline - 28 SSOP with Heat Slug 16 Data Sheet- Rev 2.2 04/2011 ARA2004 COMPONENT PACKAGING Volume quantities for the ARA2000 are supplied on tape and reel. Each reel holds 3,500 pieces. Figure 21: Reel Dimensions Figure 22: Tape Dimensions Data Sheet- Rev 2.2 04/2011 17 ARA2004 NOTES 18 Data Sheet- Rev 2.2 04/2011 ARA2004 NOTES Data Sheet- Rev 2.2 04/2011 19 ARA2004 NOTES 20 Data Sheet- Rev 2.2 04/2011 ARA2004 ANADIGICS 141 Mount Bethel Road Warren, New Jersey 07059, U.S.A. Tel: +1 (908) 668-5000 Fax: +1 (908) 668-5132 URL: http://www.anadigics.com IMPORTANT NOTICE ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without notice. The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are subject to change prior to a product’s formal introduction. Information in Data Sheets have been carefully checked and are assumed to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges customers to verify that the information they are using is current before placing orders. warning ANADIGICS products are not intended for use in life support appliances, devices or systems. Use of an ANADIGICS product in any such application without written consent is prohibited. 21 Data Sheet - Rev 2.2 04/2011